DP AK BUK92150-55A N-channel TrenchMOS logic level FET 12 June 2014 Product data sheet 1. General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product has been designed and qualified to the appropriate AEC standard for use in automotive critical applications. 2. Features and benefits • • • • Low conduction losses due to low on-state resistance Q101 compliant Suitable for logic level gate drive sources Suitable for thermally demanding environments due to 175 °C rating 3. Applications • • • 12 V and 24 V loads Automotive and general purpose power switching Motors, lamps and solenoids 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - - 55 V ID drain current VGS = 5 V; Tmb = 25 °C; Fig. 2; Fig. 3 - - 11 A Ptot total power dissipation Tmb = 25 °C; Fig. 1 - - 36 W VGS = 10 V; ID = 5 A; Tj = 25 °C - 97 125 mΩ VGS = 5 V; ID = 5 A; Tj = 175 °C; - - 280 mΩ VGS = 4.5 V; ID = 5 A; Tj = 25 °C - - 155 mΩ VGS = 5 V; ID = 5 A; Tj = 25 °C; Fig. 11; - 120 140 mΩ - 2.6 - nC Static characteristics RDSon drain-source on-state resistance Fig. 11; Fig. 12 Fig. 12 Dynamic characteristics QGD gate-drain charge VGS = 5 V; ID = 5 A; VDS = 44 V; Tj = 25 °C; Fig. 13 Scan or click this QR code to view the latest information for this product BUK92150-55A NXP Semiconductors N-channel TrenchMOS logic level FET Symbol Parameter Conditions Min Typ Max Unit ID = 11 A; Vsup ≤ 55 V; RGS = 50 Ω; - - 16 mJ Avalanche ruggedness EDS(AL)S non-repetitive drainsource avalanche energy VGS = 5 V; Tj(init) = 25 °C; unclamped 5. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline 1 G gate 2 D Drain 3 S source mb D mounting base; connected to drain Graphic symbol D mb G mbb076 2 1 S 3 DPAK (SOT428) 6. Ordering information Table 3. Ordering information Type number Package Name Description Version BUK92150-55A DPAK plastic single-ended surface-mounted package (DPAK); 3 leads (one lead cropped) SOT428 BUK92150-55A/CD DPAK plastic single-ended surface-mounted package (DPAK); 3 leads (one lead cropped) SOT428 7. Marking Table 4. Marking codes Type number Marking code BUK92150-55A 9215055A BUK92150-55A/CD 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - 55 V BUK92150-55A Product data sheet All information provided in this document is subject to legal disclaimers. 12 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved 2 / 13 BUK92150-55A NXP Semiconductors N-channel TrenchMOS logic level FET Symbol Parameter Conditions Min Max Unit VDGR drain-gate voltage RGS 20 kΩ - 55 V VGS gate-source voltage -15 15 V Ptot total power dissipation Tmb = 25 °C; Fig. 1 - 36 W ID drain current Tmb = 25 °C; VGS = 5 V; Fig. 2; Fig. 3 - 11 A Tmb = 100 °C; VGS = 5 V; Fig. 3 - 7.8 A Tmb = 25 °C; pulsed; tp ≤ 10 µs; Fig. 2 - 44 A IDM peak drain current Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C Source-drain diode IS source current Tmb = 25 °C - 11 A ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 44 A ID = 11 A; Vsup ≤ 55 V; RGS = 50 Ω; - 16 mJ Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy VGS = 5 V; Tj(init) = 25 °C; unclamped 03na19 120 Pder (%) 80 40 0 Fig. 1. 0 50 100 150 Tmb (°C) 200 Normalized total power dissipation as a function of mounting base temperature BUK92150-55A Product data sheet All information provided in this document is subject to legal disclaimers. 12 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved 3 / 13 BUK92150-55A NXP Semiconductors N-channel TrenchMOS logic level FET 03nf47 102 ID (A) tp = 10 µs Limit RDSon = VDS / ID 10 100 µs 1 ms DC 1 10- 1 Fig. 2. 10 ms 100 ms 1 10 102 VDS (V) Safe operating area; continuous and peak drain currents as a function of drain-source voltage 03nf49 12 ID (A) 8 4 0 Fig. 3. 0 50 100 150 Tmb (°C) 200 Continuous drain current as a function of mounting base temperature 9. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from junction to mounting base Fig. 4 - - 4.1 K/W Rth(j-a) thermal resistance from junction to ambient - 71.4 - K/W BUK92150-55A Product data sheet All information provided in this document is subject to legal disclaimers. 12 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved 4 / 13 BUK92150-55A NXP Semiconductors N-channel TrenchMOS logic level FET 03nf48 10 Zth(j-mb) (K/W) 1 δ = 0.5 0.2 0.1 0.05 0.02 P 10- 1 tp δ= T single shot tp 10- 2 Fig. 4. 10- 6 10- 5 10- 4 10- 3 10- 2 t T 10- 1 1 tp (s) Transient thermal impedance from junction to ambient as a function of pulse duration 10. Characteristics Table 7. Characteristics Symbol Parameter Conditions Min Typ Max Unit drain-source breakdown voltage ID = 0.25 mA; VGS = 0 V; Tj = 25 °C 55 - - V ID = 0.25 mA; VGS = 0 V; Tj = -55 °C 50 - - V gate-source threshold voltage ID = 1 mA; VDS = VGS; Tj = -55 °C; - - 2.3 V 1 1.5 2 V 0.5 - - V VDS = 55 V; VGS = 0 V; Tj = 175 °C - - 500 µA VDS = 55 V; VGS = 0 V; Tj = 25 °C - 0.05 10 µA VGS = 10 V; VDS = 0 V; Tj = 25 °C - 2 100 nA VGS = -10 V; VDS = 0 V; Tj = 25 °C - 2 100 nA VGS = 10 V; ID = 5 A; Tj = 25 °C - 97 125 mΩ VGS = 5 V; ID = 5 A; Tj = 175 °C; - - 280 mΩ VGS = 4.5 V; ID = 5 A; Tj = 25 °C - - 155 mΩ VGS = 5 V; ID = 5 A; Tj = 25 °C; Fig. 11; - 120 140 mΩ Static characteristics V(BR)DSS VGS(th) Fig. 10 ID = 1 mA; VDS = VGS; Tj = 25 °C; Fig. 10 ID = 1 mA; VDS = VGS; Tj = 175 °C; Fig. 10 IDSS IGSS RDSon drain leakage current gate leakage current drain-source on-state resistance Fig. 11; Fig. 12 Fig. 12 BUK92150-55A Product data sheet All information provided in this document is subject to legal disclaimers. 12 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved 5 / 13 BUK92150-55A NXP Semiconductors N-channel TrenchMOS logic level FET Symbol Parameter Conditions Min Typ Max Unit total gate charge ID = 5 A; VDS = 44 V; VGS = 5 V; - 6 - nC QGS gate-source charge Tj = 25 °C; Fig. 13 - 0.76 - nC QGD gate-drain charge - 2.6 - nC Ciss input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz; - 240 338 pF Coss output capacitance Tj = 25 °C; Fig. 14 - 50 65 pF Crss reverse transfer capacitance - 40 58 pF td(on) turn-on delay time VDS = 20 V; RL = 3.3 Ω; VGS = 5 V; - 8 - ns tr rise time RG(ext) = 10 Ω; Tj = 25 °C - 57 - ns td(off) turn-off delay time - 16 - ns tf fall time - 13 - ns LD internal drain inductance measured from drain to centre of die; Tj = 25 °C - 2.5 - nH LS internal source inductance measured from source lead to source bond pad; Tj = 25 °C - 7.5 - nH Dynamic characteristics QG(tot) Source-drain diode VSD source-drain voltage IS = 15 A; VGS = 0 V; Tj = 25 °C; Fig. 15 - 0.85 1.2 V trr reverse recovery time IS = 20 A; dIS/dt = -100 A/µs; - 24 - ns recovered charge VGS = -10 V; VDS = 30 V; Tj = 25 °C - 26 - nC Qr 03nf44 16 10 5 ID (A) label is VGS (V) RDSon (mΩ) 4 12 03nf43 140 3.8 120 3.6 8 3.4 3.2 4 0 Fig. 5. 100 3 2.8 2.6 2.4 2.2 0 2 4 6 8 VDS (V) 80 10 Output characteristics: drain current as a Fig. 6. function of drain-source voltage; typical values BUK92150-55A Product data sheet 0 10 VGS (V) 15 Drain-source on-state resistance as a function of gate-source voltage; typical values All information provided in this document is subject to legal disclaimers. 12 June 2014 5 © NXP Semiconductors N.V. 2014. All rights reserved 6 / 13 BUK92150-55A NXP Semiconductors N-channel TrenchMOS logic level FET 03aa36 10-1 ID (A) gfs (S) 10-2 8 10-3 6 min typ max 10-4 4 10-5 2 10-6 0 1 2 VGS (V) 0 3 Tj = 25 °C; VDS = 5 V Fig. 7. 03nf41 10 Fig. 8. Sub-threshold drain current as a function of gate-source voltage 03nf42 8 0 4 8 12 03aa33 2 6 16 Forward transconductance as a function of drain current; typical values 2.5 VGS(th) (V) ID (A) ID (A) max 1.5 typ 1 min 4 2 0 Fig. 9. Tj = 175 °C 0 1 2 0.5 Tj = 25 °C 3 VGS (V) 0 -60 4 Transfer characteristics: drain current as a function of gate-source voltage; typical values BUK92150-55A Product data sheet 0 60 120 Tj (° C) 180 Fig. 10. Gate-source threshold voltage as a function of junction temperature All information provided in this document is subject to legal disclaimers. 12 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved 7 / 13 BUK92150-55A NXP Semiconductors N-channel TrenchMOS logic level FET 03nf45 300 3 RDSon (mΩ) 3.2 03ne89 2 3.4 a 3.6 1.5 250 3.8 1 200 4 150 100 0.5 VGS = 5 V 2 6 10 ID (A) 0 -60 14 Fig. 11. Drain-source on-state resistance as a function of drain current; typical values VGS (V) 60 120 Tj (°C) 180 Fig. 12. Normalized drain-source on-state resistance factor as a function of junction temperature 03nf40 5 0 03nf46 600 C (pF) 4 400 3 VDD = 14 V Ciss VDD = 44 V 2 Coss 200 1 Crss 0 0 2 4 QG (nC) 6 Fig. 13. Gate-source voltage as a function of gate charge; typical values BUK92150-55A Product data sheet 0 10- 2 10- 1 1 10 VDS (V) 102 Fig. 14. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values All information provided in this document is subject to legal disclaimers. 12 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved 8 / 13 BUK92150-55A NXP Semiconductors N-channel TrenchMOS logic level FET 03nf39 30 IS (A) 20 10 0 Tj = 175 °C 0 0.5 Tj = 25 °C 1.0 1.5 VSD (V) 2.0 Fig. 15. Reverse diode current as a function of reverse diode voltage; typical values BUK92150-55A Product data sheet All information provided in this document is subject to legal disclaimers. 12 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved 9 / 13 BUK92150-55A NXP Semiconductors N-channel TrenchMOS logic level FET 11. Package outline Plastic single-ended surface-mounted package (DPAK); 3 leads (one lead cropped) SOT428 y E A A A1 b2 see Note 1 E1 mounting base D2 D1 HD 2 L2 L 1 L1 3 b1 b w c A e e1 0 5 10 mm scale Dimensions (mm are the original dimensions) Unit A A1 b max 2.38 0.93 0.89 nom min 2.22 0.46 0.71 mm b1 b2 c D1 1.1 5.46 0.56 6.22 0.9 5.00 0.20 5.98 D2 E E1 6.73 4.0 6.47 4.45 e e1 2.285 4.57 HD L L1 10.4 2.95 9.6 2.55 L2 0.9 0.5 0.5 w 0.2 Note 1. Plastic body may have 45° chamfer. Outline version SOT428 0.2 sot428_po References IEC y JEDEC JEITA TO-252 SC-63 European projection Issue date 06-03-16 14-06-10 Fig. 16. Package outline DPAK (SOT428) BUK92150-55A Product data sheet All information provided in this document is subject to legal disclaimers. 12 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved 10 / 13 BUK92150-55A NXP Semiconductors N-channel TrenchMOS logic level FET In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. 12. 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BUK92150-55A Product data sheet Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 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NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. 12 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved 11 / 13 BUK92150-55A NXP Semiconductors N-channel TrenchMOS logic level FET No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 12.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV, FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, ICODE, ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse, QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET, TrenchMOS, TriMedia and UCODE — are trademarks of NXP Semiconductors N.V. HD Radio and HD Radio logo — are trademarks of iBiquity Digital Corporation. BUK92150-55A Product data sheet All information provided in this document is subject to legal disclaimers. 12 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved 12 / 13 BUK92150-55A NXP Semiconductors N-channel TrenchMOS logic level FET 13. Contents 1 General description ............................................... 1 2 Features and benefits ............................................1 3 Applications ........................................................... 1 4 Quick reference data ............................................. 1 5 Pinning information ............................................... 2 6 Ordering information ............................................. 2 7 Marking ................................................................... 2 8 Limiting values .......................................................2 9 Thermal characteristics .........................................4 10 Characteristics ....................................................... 5 11 Package outline ................................................... 10 12 12.1 12.2 12.3 12.4 Legal information .................................................11 Data sheet status ............................................... 11 Definitions ...........................................................11 Disclaimers .........................................................11 Trademarks ........................................................ 12 © NXP Semiconductors N.V. 2014. All rights reserved For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 12 June 2014 BUK92150-55A Product data sheet All information provided in this document is subject to legal disclaimers. 12 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved 13 / 13