P3P8203A General Purpose Peak EMI Reduction Device Functional Description P3P8203A is a versatile, 3.3 V LVCMOS Peak EMI reduction device. P3P8203A accepts an input clock either from a Fundamental Crystal or from an external reference and locks on to it delivering a 1x modulated clock. P3P8203A has an SSEXTR pin to select different deviations depending upon the value of an external resistor connected between SSEXTR and GND. P3P8203A operates with 3.3 V ± 0.3 V supply and is available in an 8 Pin, WDFN (2 mm X 2 mm) Package, over a temperature range of 0°C to +70°C. http://onsemi.com MARKING DIAGRAM 1 1 GJ MG G GJ = Specific Device Code M = Date Code G = Pb−Free Device (*Note: Microdot may be in either location) Features • • • • • • • • WDFN8 CASE 511AQ 1x, LVCMOS Peak EMI Reduction Supports non-continuous input clock applications Input / output frequency range: 18 MHz − 36 MHz Analog Deviation Selection Supply Voltage: 3.3 V ± 0.3 V 8 pin, WDFN (2 mm X 2 mm) package Operating Temperature range: 0°C to +70°C These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant PIN CONFIGURATION XIN/CLKIN 1 XOUT 2 NC 3 GND 4 Application 8 VDD 7 SSEXTR 6 NC 5 ModOUT • P3P8203A is targeted for use in a broad range of note book and desktop PCs and consumer electronic applications. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. VDD XIN/CLKIN XOUT Crystal Oscillator Digital Frequency Modulation ModOUT Analog Deviation Control SSEXTR GND Figure 1. Block Diagram © Semiconductor Components Industries, LLC, 2012 August, 2012 − Rev. 0 1 Publication Order Number: P3P8203A/D P3P8203A Table 1. PIN DESCRIPTION Pin # Pin Name Type Description 1 XIN/CLKIN Input Crystal connection or External reference clock input. 2 XOUT Output 3 NC 4 GND Power Ground 5 ModOUT Output Buffered Modulated Clock output. Crystal connection. If using an external reference, this pin should be left open. No connection 6 NC 7 SSEXTR Input No connection 8 VDD Power Analog Deviation Selection through external resistor to GND. Supply Voltage Table 2. OPERATING CONDITIONS Symbol VDD Description Supply Voltage Min Max Unit 3.0 3.6 V 0 TA Operating Temperature (Ambient Temperature) 70 °C CL Load Capacitance 15 pF CIN Input Capacitance 7 pF Table 3. ABSOLUTE MAXIMUM RATING Symbol VDD, VIN TSTG Description Rating Unit Voltage on any input pin with respect to Ground −0.5 to +4.6 V Storage temperature −65 to +125 °C Ts Max. Soldering Temperature (10 sec) 260 °C TJ Junction Temperature 150 °C 2 KV TDV Static Discharge Voltage (As per JEDEC STD22−A114−B) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 4. ELECTRICAL CHARACTERISTICS Symbol Parameter Test Conditions VDD Supply Voltage VIL Input LOW Voltage VIH Input HIGH Voltage VOL Output LOW Voltage IOL = 8 mA VOH Output HIGH Voltage IOH = -8 mA ICC Static Supply Current CLKIN pulled LOW Dynamic Supply Current Load Capacitance Z0 Output Impedance Typ Max Unit 3.0 3.3 3.6 V 0.35 * VDD V 0.65 * VDD Unloaded output IDD CL Min V 0.25 * VDD 0.75 * VDD V 1 mA 18 MHz 5 mA 24 MHz 6 36 MHz 8 15 24 http://onsemi.com 2 V pF W P3P8203A Table 5. SWITCHING CHARACTERISTICS Max Unit Input Clock Frequency Parameter Test Conditions Min 18 Typ 36 MHz ModOUT 18 36 Output Rise Time (Notes 1 and 2) Measured between 20% to 80% 1.0 1.6 nS Output fall Time (Notes 1 and 2) Measured between 80% to 20% 1.0 1.6 nS 50 55 % Output Duty Cycle (Notes 1 and 2) Cycle-to-Cycle Jitter (Note 2) Measured at 50% (with Input Duty Cycle of 50%) Unloaded output with SSEXTR pin OPEN Part-Part Frequency Deviation Variation 1. All parameters are measured with 15pF load on ModOUT. 2. Parameter is guaranteed by design and characterization. Not tested in production. http://onsemi.com 3 45 ±100 pS ±20 % P3P8203A SWITCHING WAVEFORMS 80% 80% 20% 20% OUTPUT t3 t4 Figure 2. Output Rise/Fall Time t1 t2 50% 50% OUTPUT Figure 3. Duty Cycle Timing R Crystal CL Rx CL Figure 4. Typical Crystal Interface Circuit CL = 2*(CP − CS), Where CP = Load capacitance of crystal specified in a Crystal Datasheet CS = Stray capacitance due to CIN, PCB, Trace etc CL =Load capacitance to be used Rx is used to reduce power dissipation in the Crystal http://onsemi.com 4 P3P8203A 0.060 DEVIATION (±%) 0.055 0.050 0.045 0.040 0.035 0.030 5 5.5 6 RESISTANCE (kW) 6.5 7 Figure 5. Deviation vs. SSEXTR (@ 27 MHz) (NOTE: Parameter is guaranteed by design and characterization. Not tested in production.) VDDIN R C1 0.1 mF C2 2.2 mF CL is the load capacitance for proper XTAL operation 8 VDD 1 Rs XIN/C LKIN CL Y1 ModOUT 5 SSEXTR 7 ModOUT Cloc k 2 XOUT CL R1 Analog D eviation C ontrol P3P8203A 3, 6 NC 4 GND Note: Refer Pin Description table for Functionality details Figure 6. Typical Application Circuit Rs = Trace Impedance of PCB − Output Impedance of Device (Z0) ORDERING INFORMATION Ordering Code P3P8203AMTTBG Marking Temperature Package Type Shipping† GJ 0°C to +70°C 8−pin (2 mm x 2 mm) WDFN (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *A “microdot” placed at the end of last row of marking or just below the last row toward the center of package indicates Pb−Free. http://onsemi.com 5 P3P8203A PACKAGE DIMENSIONS WDFN8 2x2, 0.5P CASE 511AQ ISSUE A D PIN ONE REFERENCE 2X A B L1 ÍÍÍ ÍÍÍ ÍÍÍ DETAIL A E OPTIONAL CONSTRUCTIONS 0.10 C 2X 0.10 C ÉÉ ÉÉ TOP VIEW EXPOSED Cu A3 DETAIL B 0.05 C 0.05 C MOLD CMPD OPTIONAL CONSTRUCTION C MILLIMETERS MIN MAX 0.80 0.70 0.05 0.00 0.20 REF 0.20 0.30 2.00 BSC 2.00 BSC 0.50 BSC 0.50 0.60 --0.15 RECOMMENDED SOLDERING FOOTPRINT* A1 SIDE VIEW DIM A A1 A3 b D E e L L1 DETAIL B A 8X SEATING PLANE 7X 0.78 PACKAGE OUTLINE DETAIL A 1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL. L L 8X 4 L 2.30 0.88 8 5 e/2 e 8X b 0.10 C A 0.05 C 8X 1 0.35 B 0.50 PITCH DIMENSIONS: MILLIMETERS NOTE 3 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. BOTTOM VIEW ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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