PCS3P8504A General Purpose Peak EMI Reduction IC Functional Description PCS3P8504A is a versatile, 3.3 V Timing−Safe™ Peak EMI reduction IC. PCS3P8504A accepts an input clock either from a fundamental Crystal or from an external reference (AC or DC coupled to XIN/CLKIN) and locks on to it delivering a 1x modulated clock output. PCS3P8504A has a SSON pin for enabling and disabling Spread Spectrum function. PCS3P8504A has an SSEXTR pin to select different deviations depending upon the value of an external resistor connected between SSEXTR and GND. Modulation Rate (MR) control selects one of the two different Modulation Rates. PCS3P8504A operates from a 3.3 V supply, and is available in an 8−pin, WDFN(2 mm x 2 mm) package. General Features • 1x, LVCMOS Peak EMI Reduction • Input frequency: • • • • • • • 15 MHz − 50 MHz Output frequency: ♦ 15 MHz − 50 MHz Analog Deviation Selection ModRate selection option Spread Spectrum Enable/Disable Supply Voltage: 3.3 V $ 0.3 V 8−pin, WDFN 2 mm x 2 mm (TDFN) Package These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant ♦ Application • PCS3P8504A is targeted for consumer electronics application like http://onsemi.com MARKING DIAGRAMS 1 1 WDFN8 CASE 511AQ DAMG G DA = Specific Device Code M = Date Code G = Pb−Free Device (Note: Microdot may be in either location) PIN CONFIGURATION XIN/CLKIN 1 8 VDD 7 SSEXTR SSON 3 6 MR GND 4 5 ModOUT XOUT 2 PCS3P8504A ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. DPF, MFP. © Semiconductor Components Industries, LLC, 2013 August, 2013 − Rev. 3 1 Publication Order Number: PCS3P8504A/D PCS3P8504A SSON MR VDD XIN/CLKIN ModOUT Crystal Oscillator XOUT PLL SSEXTR GND Figure 1. Block Diagram Table 1. PIN DESCRIPTION Pin# Pin Name Type Description 1 XIN / CLKIN I Crystal connection or External reference clock input. 2 XOUT O Crystal connection. If using an external reference, this pin should be left open. 3 SSON I Spread Spectrum ON/OFF. Spread Spectrum function enabled when HIGH, disabled when LOW. Has an internal pull−up resistor. 4 GND P Ground 5 ModOUT O Modulated clock output 6 MR I Modulation Rate Select. When LOW selects Low Modulation Rate. Selects High Modulation Rate when pulled HIGH. Has an internal pull−up resistor. 7 SSEXTR I Analog Deviation Selection through external resistor to GND. 8 VDD P 3.3 V supply Voltage. Table 2. OPERATING CONDITIONS Symbol VDD Parameter Supply Voltage Commercial Min Max Unit 3 3.6 V 0 70 °C TA Operating Temperature CL Load Capacitance 10 pF CIN Input Capacitance 7 pF Table 3. ABSOLUTE MAXIMUM RATING Symbol VDD, VIN TSTG Ts Parameter Rating Unit Voltage on any input pin with respect to Ground −0.5 to +4.6 V Storage Temperature −65 to +125 °C 260 °C Max. Soldering Temperature (10 sec) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. http://onsemi.com 2 PCS3P8504A Table 3. ABSOLUTE MAXIMUM RATING Symbol TJ TDV Parameter Rating Unit 150 °C 2 kV Junction Temperature Static Discharge Voltage (As per JEDEC STD22− A114−B) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 4. DC ELECTRICAL CHARACTERISTICS Symbol VDD Parameter Test Conditions Supply Voltage VIL Input LOW Voltage VIH Input HIGH Voltage Min Typ Max Unit 3.0 3.3 3.6 V 0.8 V 2.0 V IIL Input LOW Current VIN = 0 V 25 mA IIH Input HIGH Current VIN = VDD 25 mA VOL Output LOW Voltage IOL = 8 mA 0.4 V VOH Output HIGH Voltage IOH = −8 mA ICC Static Supply Current XIN / CLKIN pulled low 50 mA IDD Dynamic Supply Current Unloaded Output 20 mA Zo Output Impedance 2.4 V 30 W Table 5. SWITCHING CHARACTERISTICS Parameter Test Conditions Input Frequency* / ModOUT Min Typ 15 45 Unit 50 MHz 55 % Duty Cycle (Notes 1 and 2) Measured at VDD / 2 Output Rise Time (Notes 1 and 2) Measured between 20% to 80% 1.8 ns Output Fall Time (Notes 1 and 2) Measured between 80% to 20% 1.6 ns Cycle−to−Cycle Jitter (Note 2) Unloaded output with SSEXTR OPEN @ 27 MHz PLL Lock Time (Note 2) Stable power supply, valid clock presented on XIN / CLKIN *Functionality with Crystal is guaranteed by design and characterization. Not tested in production. 1. All parameters are specified with10 pF loaded outputs. 2. Parameter is guaranteed by design and characterization. Not tested in production. http://onsemi.com 3 50 Max $150 $250 ps 3 ms PCS3P8504A TYPICAL CRYSTAL SPECIFICATIONS FUNDAMENTAL AT CUT PARALLEL RESONANT CRYSTAL Nominal frequency 27 MHz Frequency tolerance $50 ppm or better at 25°C Operating temperature range −25°C to +85°C Storage temperature −40°C to +85°C Load capacitance (CP) 18 pF Shunt capacitance 7 pF maximum ESR 25 W NOTE: CL is the Load Capacitance and Rx is used to prevent oscillations at overtone frequency of the Fundamental frequency. PCS3P8504A R XIN/CLKIN XOUT Rx Crystal CL CL CL = 2 * (CP – CS), Where CP = Load capacitance of crystal from crystal vendor datasheet CS = Stray capacitance due to CIN, PCB, Trace etc. Figure 2. Typical Crystal Interface Circuit SWITCHING WAVEFORMS t1 t2 VDD/2 VDD/2 OUTPUT Figure 3. Duty Cycle Timing 80% 80% 20% 20% OUTPUT t3 t4 Figure 4. Output Rise/Fall Time http://onsemi.com 4 VDD/2 PCS3P8504A Noise Reduction Filter VDD R CL is the load capacitance for proper XTAL operation PCS3P8504A C VDD 8 SSEXTR 7 1 XIN/CLKIN CL 2 XOUT VDD CL External Deviation Control R1 VDD 3 SSON SSON Control MR 6 ModOUT 5 Analog Deviation Control SSEXTR can be Pulled HIGH to turn OFF Deviation MR Control 4 GND NOTE: SSON (Pin#3) MR (Pin#6): Connect to VDD or GND Refer to Pin Description table for Functionality details Figure 5. Application Schematic 2.5 2.5 MR = 0 2.0 DEVIATION ($%) DEVIATION ($%) 2.0 1.5 1.0 NOTE: 1.5 1.0 0.5 0.5 0.0 MR = 1 0 50 100 150 200 250 300 0.0 0 50 100 150 200 250 300 350 400 450 500 550 600 650 RESISTANCE (kW) RESISTANCE (kW) Figure 6. Deviation vs SSEXTR Resistance Chart at 27 MHz Figure 7. Deviation vs SSEXTR Resistance Chart at 27 MHz Device to Device variation of Deviation is $10% (Commercial Temperature Range) and $25% (Industrial Temperature Range) ORDERING INFORMATION Part Number PCS3P8504AG−08CR Top Marking Temperature Package Type Shipping† DA 0°C to +70°C 8−Pin (2 mm x 2 mm) WDFN(TDFN) (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *A “microdot” placed at the end of last row of marking or just below the last row toward the center of package indicates Pb−Free. http://onsemi.com 5 PCS3P8504A PACKAGE DIMENSIONS WDFN8 2x2, 0.5P CASE 511AQ ISSUE A D A B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL. L L L1 PIN ONE REFERENCE 2X ÍÍÍ ÍÍÍ DETAIL A E OPTIONAL CONSTRUCTIONS 0.10 C 2X 0.10 C ÉÉ ÉÉ TOP VIEW EXPOSED Cu A3 DETAIL B 0.05 C 0.05 C MOLD CMPD DETAIL B A 8X DIM A A1 A3 b D E e L L1 OPTIONAL CONSTRUCTION A1 C SIDE VIEW RECOMMENDED SOLDERING FOOTPRINT* SEATING PLANE 7X 0.78 DETAIL A 1 MILLIMETERS MIN MAX 0.70 0.80 0.00 0.05 0.20 REF 0.20 0.30 2.00 BSC 2.00 BSC 0.50 BSC 0.50 0.60 --0.15 8X 4 L PACKAGE OUTLINE 2.30 0.88 8 5 e/2 e 8X b 0.10 C A 0.05 C 8X B 0.35 NOTE 3 1 0.50 PITCH DIMENSIONS: MILLIMETERS BOTTOM VIEW *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Timing−Safe is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. 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