LM8335 www.ti.com SNVS840 – JUNE 2012 LM8335 General Purpose Output Expander with MIPI® RFFE Host Interface Check for Samples: LM8335 FEATURES 1 • • MIPI RFFE Interface Version 1.10 Compliant Supports Output Expansion Host Interface Address Select Pin: – ADR=GND, USID[3:0]=0001 – ADR=VDD, USID[3:0]=1001 Pin-Configurable Initial State: VIO – CFG=GND, GPO High-z, with Weak Internal Pull-Down Resistor Enabled; GPO_OUT_DATA is Unmasked – CFG=VDD, GPO High-z, with Weak Internal Pull-Down Resistor Enabled; GPO_OUT_DATA is Masked Three Sources for Chip Reset: – VIO Input Pin – POR – Software-Commanded Reset APPLICATIONS: • • Smart Handheld Devices RF Transceiver Applications KEY SPECIFICATIONS • • • • • • • 1.8 ± 0.15V MIPI RFFE Operation (VIO) 1.8 ± 0.15V Core Supply (VDD) 1.65 to 3.6V GPO Supply (VDDIO) Low Standby and Active Current On-Chip Power-On Reset (POR) −30 to +85°C Ambient Temperature Range 16-Bump DSBGA Package – 1.965 mm x 1.965 mm x 0.6 mm, 0.5 mm Pitch (Nominal) DESCRIPTION The LM8335 General Purpose Output Expander is a dedicated device to provide flexible and general purpose, host programmable output expansion functions. This device communicates with a host processor through a MIPI® RFFE Interface (Mobile Industry Processor Interface RF Front-End). Eight general purpose outputs (GPO) can be configured by the host controller as drive high/low/high-z. Weak pull-ups (PU) or weak pulldowns (PD) can be enabled. Upon power-on, the LM8335 default configuration is for all GPO to be set based on the state of the CFG pin. After startup, any changes to the default configuration must be sent from the host via the MIPI RFFE host interface.. The LM8335 is available in a 16-bump lead-free DSBGA package of size 1.965 mm x 1.965 mm x 0.6 mm (0.5 mm pitch). 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. Copyright © 2012, Texas Instruments Incorporated PRODUCT PREVIEW • • • 2 LM8335 SNVS840 – JUNE 2012 www.ti.com Single RFFE Slave Application Block Diagram PRODUCT PREVIEW 2 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LM8335 LM8335 www.ti.com SNVS840 – JUNE 2012 PRODUCT PREVIEW Dual RFFE Slave Application Block Diagram Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LM8335 3 LM8335 SNVS840 – JUNE 2012 www.ti.com Connection Diagram and Package Mark Information 1 2 3 4 A VDD VIO SCLK SDATA B VDDIO GND ADR GPO_0 C GPO_6 GPO_7 CFG GPO_1 D GPO_5 GPO_4 GPO_3 GPO_2 Top View Note: This is a preliminary pinout (pin sequence not fixed) Figure 1. 16-Bump DSBGA Pinout 1.965mm x 1.965mm x 0.6mm (nom), 0.5mm pitch See Package Number YZR0016 PRODUCT PREVIEW PIN A1 IDENTIFIER Figure 2. A1 Pin Identifier PIN DESCRIPTIONS Pin Number Name 8 GPO_0 through GPO_7 Description General purpose outputs 1 SCLK RFFE clock input 1 SDATA RFFE data input RFFE chip address input 1 ADR ADR = VDD: USID[3:0] = b1001 ADR = GND: USID[3:0] = b0001 Initial configuration select 1 CFG CFG = VDD: GPO high-z with weak internal pull-down resistor enabled, GPO_OUT_DATA masked CFG = GND: GPO high-z, with weak internal pull-down resistor enabled, GPO_OUT_DATA unmasked 4 1 VIO MIPI RFFE VIO (1.8V ± 0.15V) 1 VDD Core supply VDD (1.8V ± 0.15V) 1 VDDIO 1 GND GPO supply VDDIO (1.65V to 3.6V) Ground Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LM8335 LM8335 www.ti.com SNVS840 – JUNE 2012 ADR INPUT PIN The state of the ADR pin determines the MIPI RFFE USID as described in the table above. This enables two devices to be used on the same RFFE bus thereby doubling the number of GPOs available in the system (see Dual RFFE Slave Application Block Diagram). DEFAULT GPO_x PIN CONFIGURATION Upon power-on all GPOs will default based on the state of the CFG pin. CFG INPUT PIN = GND CFG INPUT PIN = VDD The CFG1 mode is a more general purpose mode where the outputs must be configured during initialization prior to use. In this mode, the GPOs will default as high-z with internal pull-down resistors enabled and GPO_OUT_DATA will be masked. During initialization, the host must first write to the GPO_OUT_DATA register (Note: this will transition all of the GPOs from high-z with internal pull-down to Full-Buffer driven low with internal pull-down regardless of the value written to the GPO_OUT_DATA register). The host must then write to the GPO_PULL_DIR, GPO_PULL_ENABLE, & GPO_OUT_HIGH_CFG registers to configure each GPO into the desired output configuration. Once that is complete, the host then writes the GPO_DATA_MASK and GPO_OUT_DATA registers to set the GPO outputs in the desired state. Refer to Figure 8. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) RFFE Supply Voltage (VIO) −0.3V to 2.2V Core Supply Voltage (VDD) −0.3V to 2.2V −0.3V to 4.0V GPO Supply Voltage (VDDIO) DC Input Voltage for SCLK & SDATA pins −0.3V to (VIO+0.3V) DC Input Voltage for ADR & CFG pins −0.3V to (VDD+0.3V) −0.3V to (VDDIO+0.3V) DC Output Voltage for GPO pins −40°C to +125° C Storage Temperature Range −0°C to +85°C Operating Ambient Temperature (TA) Lead Temperature (TL) (Soldering, 10 sec.) 260°C ESD Rating (CZAP=120 pF, RZAP=1500Ω) (3) 1000V Charge Device Model: 250V Human Body Model (1) (2) (3) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not specified. For specifications and test conditions, see the Electrical Characteristics tables. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF capacitor discharged directly into each pin. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LM8335 5 PRODUCT PREVIEW The CFG0 mode is an automatic initialization mode. It allows the host to not have to first configure any registers before writing the GPO_OUT_DATA register to set the GPOs high or low. In this mode, the GPOs will default as high-z with weak pull-down resistors enabled and the GPO_OUT_DATA will be unmasked. When the host writes the GPO_OUT_DATA register, the weak pull-down resistor will be disabled. The output driver will immediately be enabled and will drive high or low based on the value written to the GPO_OUT_DATA register. In configuration mode CFG0 the GPO data mask function is available but the GPO pull resistor, and high-z functions cannot be changed. Writing to the GPO_PULL_DIR, GPO_PULL_ENABLE, and GPO_OUT_HIGH_CFG registers will have no effect. If control of the GPO pull resistor or output configuration is required then the CFG1 mode must be used. LM8335 SNVS840 – JUNE 2012 www.ti.com Operating Ratings RFFE Supply Voltage (VIO) Min Max 1.65 1.95 V 25 mVpp 1.65 1.95 V 25 mVpp 1.65 3.60 V 50 mVpp RFFE Supply Noise (VIO) Core Supply Voltage (VDD) Core Supply Noise (VDD) GPO Supply Voltage (VDDIO) GPO Supply Noise (VDDIO) Unit DC Electrical Characteristics: General (ADR, CFG) (1) (2) TA: −30°C to +85°C, VIO = 1.8V ± 0.15V, VDD = 1.8V ± 0.15V, VDDIO = 3.3V ± 0.3V (unless otherwise specified). Symbol Parameter Conditions Min Typ Max PRODUCT PREVIEW VIH Minimim high-level input voltage (ADR, CFG) 0.7 * VDD VDD+ 0.2 VIL Maximum low-level input voltage (ADR, CFG) −0.2 0.3 * VDD IIH Logic high-level input current (ADR, CFG) IIL Logic low-level input current (ADR, VIN = GND CFG) (1) (2) Units V VIN = VDD 2 µA −2 All voltages are with respect to the GND pin. Min and Max Limits are specified by design, test, or statistical analysis. Typical (Typ.) numbers are not specified, but do represent the most likely norm. Unless otherwise specified conditions for typical specifications are: VDD = 1.8V, VDDIO = 3.3V, VIO = 1.8V, TA = +25°C. DC Electrical Characteristics: GPO (GPO_x, VDD, VDDIO) (1) (2) TA: −30°C to +85°C, VIO = 1.8V ± 0.15V, VDD = 1.8V ± 0.15V; VDDIO = 3.3V ± 0.3V (unless otherwise specified). Symbol Parameter Conditions IOH = −12 mA (VDDIO = 3.3V ± 0.3V) VOH Minimum high-level output voltage IOH = −4 mA (VDDIO = 1.8V ± 0.15V) IOH = −10 µA VOL Maximum low-level output voltage IOH Logic high-level output current IOL Logic low-level output current IOZ High-Z leakage current IPU Pull-Up current IPD Pull-Down current ISTBY VDD supply standby current ISTBYIO VDDIO supply standby current (1) (2) 6 Min Typ Max 0.7 * VDDIO V VDDIO − 0.2 IOL = 12 mA (VDDIO = 3.3V ± 0.3V) 0.4 IOL = 4 mA (VDDIO = 1.8V ± 0.15V) 0.4 IOL = 10 µA 0.2 (VDDIO = 3.3V ± 0.3V) −12 (VDDIO = 1.8V ± 0.15V) −4 V mA (VDDIO = 3.3V ± 0.3V) 12 (VDDIO = 1.8V ± 0.15V) 4 0 < VPIN < VDDIO −2 2 (VDDIO = 3.3V ± 0.3V) −60 −200 (VDDIO = 1.8V ± 0.15V) −9 -60 (VDDIO = 3.3V ± 0.3V) 60 200 (VDDIO = 1.8V ± 0.15V) 9 60 TA = 25°C, VIO = 1.8V, VDD = 1.8V, VDDIO = 3.3V, GPO_X = high-z, PU & PD disabled SCLK = Low Units mA µA µA µA 2.5 2.5 µA All voltages are with respect to the GND pin. Min and Max Limits are specified by design, test, or statistical analysis. Typical (Typ.) numbers are not specified, but do represent the most likely norm. Unless otherwise specified conditions for typical specifications are: VDD = 1.8V, VDDIO = 3.3V, VIO = 1.8V, TA = +25°C. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LM8335 LM8335 www.ti.com SNVS840 – JUNE 2012 DC Electrical Characteristics: GPO (GPO_x, VDD, VDDIO)(1)(2) (continued) TA: −30°C to +85°C, VIO = 1.8V ± 0.15V, VDD = 1.8V ± 0.15V; VDDIO = 3.3V ± 0.3V (unless otherwise specified). Symbol IVDD IVDDIO Parameter Conditions Min Typ Max VDD supply current TA = 25°C, VDD = 1.8V 225 400 VDDIO supply current TA = 25°C VDDIO = 3.3V 200 450 Units µA DC Electrical Characteristics: RFFE (SCLK, SDATA, VIO) (1) (2) TA: −30°C to +85°C, VIO = 1.8V ± 0.15V, VDD = 1.8V ± 0.15V; VDDIO = 3.3V ± 0.3V (unless otherwise specified). Parameter Conditions Min Typ Max Units 2.5 pF CIN Input pin capacitance (SCLK, SDATA) (2) VTP Positive edge threshold voltage (SCLK, SDATA) 0.4 * VIO 0.7 * VIO VTN Negative edge threshold voltage (SCLK, SDATA) 0.3 * VIO 0.6 * VIO VHYST Input hysteresis voltage (SDATA) 0.1 * VIO 0.4 * VIO VIORST RFFE I/O voltage reset voltage level VIO toggled low IINVIO Input current (VIO) 0 < VIO < 0.2V −1 1 IIN Input current (SCLK, SDATA) VIO = Max, 0.2 * VIO < VIN < 0.8 * VIO −1 1 IVIO VIO supply input current VIO = 1.8, RFFE write only mode (1) (2) V 0.2 µA 100 All voltages are with respect to the GND pin. Min and Max Limits are specified by design, test, or statistical analysis. Typical (Typ.) numbers are not specified, but do represent the most likely norm. Unless otherwise specified conditions for typical specifications are: VDD = 1.8V, VDDIO = 3.3V, VIO = 1.8V, TA = +25°C. AC Electrical Characteristics: Internal POR, VIO, GPO_x, SCLK (1) (2) TA: −30°C to +85°C, VIO = 1.8V ± 0.15V, VDD = 1.8V ± 0.15V; VDDIO = 3.3V ± 0.3V (unless otherwise specified). Symbol Parameter Conditions Min Typ Max tPORC1 VDD POR reset complete VDD ramp rate = 100 µS 1 tPORC2 VDDIO POR reset complete VDDIO ramp rate = 100 µS 1 tREADY VIO input signal reset delay time VIO = 1.65V, SCLK, SDATA = Low, tPORC1, tPORC2 = complete fSCLK SCLK frequency tD GPO_x output delay time (1) (2) 0.032 VDDIO = 1.8V ± 0.15V, CLOAD = 10 pf Units mS 120 nS 26 MHz 25 nS All voltages are with respect to the GND pin. Min and Max Limits are specified by design, test, or statistical analysis. Typical (Typ.) numbers are not specified, but do represent the most likely norm. Unless otherwise specified conditions for typical specifications are: VDD = 1.8V, VDDIO = 3.3V, VIO = 1.8V, TA = +25°C. SDATA D1 D0 P VTP Max SCLK tD VOH Min GPO_x VOL Max Figure 3. GPO Delay Timing Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LM8335 7 PRODUCT PREVIEW Symbol LM8335 SNVS840 – JUNE 2012 www.ti.com MIPI RFFE INTERFACE The LM8335 provides RFFE compatible slave access to the device specific and RFFE defined registers on a single master bidirectional serial bus interface. The LM8335 uses the three interface signals SCLK, SDATA, and VIO as defined in MIPI RFFE Version 1.10 – 26 July 2011. The VIO voltage supply provides power to the LM8335 RFFE Interface and doubles as an asynchronous enable and reset. Whenever VIO is low the SCLK and SDATA lines must be held low. When the VIO voltage is applied, the LM8335 enables the slave interface and resets the user defined slave registers to the default settings. The LM8335 enters the power down mode via the asynchronous VIO signal. The LM8335 does not support read access. The LM8335 contains fewer than 28 user defined registers but supports the Extended Register Write Command to allow a burst write of configuration registers during initialization. Any write outside of the range from 0x00 to 0x1F will have no effect on device operation. The LM8335 recognizes the broadcast Slave Identifier (SID) of 0000b and is configured internally with a Unique Slave Identifier (USID) and a Group Slave Identifier (GSID). The USID is set based on the state of the ADR pin and the GSID is set to 0000b. The USID may be reprogrammed via the RFFE Interface by performing the Register Write USID Command Sequence. The LM8335 supports only the 1.8V VIO supply levels. The LM8335 utilizes a power-detect reset circuit that resets the RFFE interface and internal registers when VIO is removed. PRODUCT PREVIEW SCLK SA3 SDATA SSC SA2 SA1 SA0 1 D6 D5 D4 Slave Address D3 Data D2 D1 D0 P Parity 0 Bus Park Signal driven by Master. Signal not driven; pull-down only. For reference only. Figure 4. Register 0 Write Command Sequence Figure 5. Register Write Command Sequence 8 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LM8335 LM8335 SNVS840 – JUNE 2012 PRODUCT PREVIEW www.ti.com Figure 6. Extended Register Write Command Sequence INTERNAL POR OPERATION There are two internal POR circuits: one on the VDD supply and one on the VDDIO supply that initialize the LM8335 when power is applied. The duration of the reset is an RC delay which is based on the ramp rate and not a threshold voltage of the VDD/VDDIO supply. VIO can be activated as soon as VDD and VDDIO have reached their minimum respective voltage levels however the LM8335 may still be in reset due to the internal POR timing. When VIO is asserted after VDD and VDDIO tPORC Max, the device reset will be released based on the VIO tREADY timing. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LM8335 9 LM8335 SNVS840 – JUNE 2012 www.ti.com VDD or VDDIO VIO VVIO-RST POR (Internal) tRAMP tPORC Min tPORC Max tREADY Max Figure 7. Internal VDD or VDDIO POR Timing PRODUCT PREVIEW Register Information Table 1. Register Listing Register Name Addr Bit Default Description Software reset register CNTL_REG 0x00 7:0 0x00 Bit 0 = 0, no effect Bit 0 = 1, reset registers to default values (self-clearing) GPO pin pull resistor direction 0 = pull-down GPO_PULL_DIR 0x01 7:0 0x00 1 = pull-up Note: When CFG = GND, writing to this register has no effect. The pull-down resistor will be disabled after the first write to the GPO_OUT_DATA register. GPO pin internal pull resistor enable 0 = disabled GPO_PULL_ENABLE 0x02 0xFF 0xFF 1 = enabled Note: GPO_PULL_DIR register selects if the resistor is a pullup or a pull-down. When CFG = GND, writing to this register has no effect. The pull-down resistor will be disabled after the first write to the GPO_OUT_DATA register. GPO output high state (full buffer or high-z). 0 = full buffer GPO_OUT_HIGH_CFG 10 0x03 7:0 0xFF 1 = high-z (open-drain behavior) Note: When CFG = GND, writing to this register has no effect. The pull-down resistor will be disabled, and all GPO outputs will be in the actively driven state (not high-z) after the first write to the GPO_OUT_DATA register. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LM8335 LM8335 www.ti.com SNVS840 – JUNE 2012 Table 1. Register Listing (continued) Register Name Addr Bit Default Description GPO output data mask 0 = GPO_OUT_DATA masked GPO_OUT_MASK 0x04 0xFF (CFG=0) or 0x00 (CFG=1) 7:0 1 = GPO_OUT_DATA unmasked Note: Only the GPO_OUT_DATA register write is affected by the GPO_OUT_MASK register. When the GPO_OUT_MASK bit is set low (masked), writing to GPO_OUT_DATA register will leave the pin state unchanged. When the GPO_OUT_MASK bit is set high (unmasked), the GPO output will be updated when the GPO_OUT_DATA is written (only GPOs that are unmasked will be changed). GPO output data 0 = pin set low GPO_OUT_DATA 0x05 7:0 0x00 PM_TRIG 0x1C 7:0 0x00 1 = pin set high Note: GPO_OUT_HIGH_CFG register selects if the pin is driven or high-z. The pin state will follow GPO_OUT_DATA only if the corresponding bit is unmasked in the GPO_OUT_MASK register. Bits 7:6 = PWR_MODE Bits 5:0 = TRIG_REG This is a MIPI RFFE reserved read only register and can not be read since readback is not supported on this device. PROD_ID 0x1D 7:0 0xC4 Bits 7:0 = PRODUCT_ID [7:0] The product ID is provided as information only to support the RFFE USID programming feature. This is a MIPI RFFE reserved read-only register and can not be read since readback is not supported on this device. MAN_ID 0x1E 7:0 0x02 Bits 7:0 = MANUFACTURER_ID [7:0] The manufacturer ID is provided as information only to support the RFFE USID programming feature. 0x11 (ADR=0) or 0x19 (ADR=1) USID_REG 0x1F This MIPI RFFE reserved register Bits 7:6 = SPARE Bits 5:4 = MANUFACTURER_ID [9:8] = 1 Bits 3:0 = Programmable Unique Slave Identifier — ADR=Low, USID[3:0]=0001 7:0 — ADR=High, USID[3:0]=1001 Note: The USID is initially set based on the state of the ADR pin (default value when ADR=Low shown). This register can not be read since readback is not supported on this device. USID_REG[5:4] are provided as information only to support the RFFE USID programming feature. Table 2. General Bit Field Layout for GPO_x Registers 7 6 5 4 3 2 1 0 GPO_7 GPO_6 GPO_5 GPO_4 GPO_3 GPO_2 GPO_1 GPO_0 Table 3. CNTL_REG Register Bit Fields 7 6 5 4 3 2 1 0 rsvd rsvd rsvd rsvd rsvd rsvd rsvd SW_RESET Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LM8335 11 PRODUCT PREVIEW MIPI RFFE power mode and trigger register LM8335 SNVS840 – JUNE 2012 www.ti.com PRODUCT PREVIEW Figure 8. CFG1 MODE Recommended Initialization Sequence 12 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LM8335 LM8335 SNVS840 – JUNE 2012 PRODUCT PREVIEW www.ti.com Figure 9. Update GPO Pin State Sequence Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LM8335 13 PACKAGE OPTION ADDENDUM www.ti.com 24-Jan-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Qty Drawing Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) (4) LM8335TLE PREVIEW 16 TBD Call TI Call TI -30 to 85 LM8335TLE NOPB PREVIEW 16 TBD Call TI Call TI -30 to 85 LM8335TLE/NOPB ACTIVE 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM LM8335TLX PREVIEW TBD Call TI Call TI LM8335TLX/NOPB ACTIVE 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM DSBGA YZR DSBGA YZR 16 16 16 Top-Side Markings (3) 8335 -30 to 90 8335 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Only one of markings shown within the brackets will appear on the physical device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 Samples MECHANICAL DATA YZR0016xxx D 0.600±0.075 E TLA16XXX (Rev C) D: Max = 2.01 mm, Min = 1.91 mm E: Max = 2.01 mm, Min = 1.91 mm 4215051/A NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994. B. This drawing is subject to change without notice. www.ti.com 12/12 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. 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