CD40182BMS CMOS Look-Ahead Carry Generator December 1992 Features Description • High Voltage Type (20V Rating) The CD40182BMS is a high-speed look-ahead carry generator capable of anticipating a carry across four binary adders or groups of adders. The CD40182BMS is cascadable to perform full look-ahead across n-bit adders. Carry, propagate-carry, and generate-carry functions are provided as enumerated in the terminal designation below. • Generates High-Speed Carry Across Four Adders or Adder Groups • High-Speed Operation - tPHL, tPLH =100 ns (typ) at VDD = 10V • Cascadable for Fast Carries Over N Bits • Designed for Use with CD40181BMS ALU • 100% Tested for Quiescent Current at 20V • 5V, 10V and 15V Parametric Ratings • Standardized Symmetrical Output Characteristics • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” The CD40182BMS, when used in conjuction with the CD40181BMS arithmetic logic unit (ALU), provides full highspeed look-ahead carry capability for up to n-bit words. Each CD40182BMS generates the look-ahead (anticipated carry) across a group of four ALU’s. In addition, other CD40182BMS’s may be employed to anticipate the carry across sections of four look-ahead blocks up to n-bits. Carry inputs and outputs of the CD40181BMS are active-high logic, and carry-generate (G) and carry-propagate (P) outputs are active-low. Therefore the inputs and outputs of the CD40182BMS are compatible. The CD40182BMS is supplied in these 16-lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack H4V H1E H6P The CD40182BMS is similar to industry type MC14582. Applications • High-Speed Parallel Arithmetric Units • Multi-Level Look-Ahead Carry Generation for Long Word Lengths Pinout Functional Diagram CD40182BMS TOP VIEW G1 1 16 VDD P1 2 15 P2 G0 3 14 G2 P0 4 13 Cn G3 5 12 Cn + x P3 6 11 Cn + y P 7 VSS 8 G P 10 G VDD = 16 VSS = 8 9 Cn + z CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 7-1410 3 G0 1 G1 14 G2 5 G3 4 P0 2 P1 15 P2 6 P3 Cn 13 12 Cn + x 11 Cn + y 9 7 10 Cn + z P G File Number 3362 Specifications CD40182BMS Absolute Maximum Ratings Reliability Information DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Thermal Resistance θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W Maximum Package Power Dissipation (PD) at +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current SYMBOL IDD CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20V VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20V VDD = 18V Output Voltage Output Voltage VOL15 VOH15 VDD = 15V, No Load VDD = 15V, No Load (Note 3) LIMITS GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS 1 +25oC - 10 µA 2 +125oC - 1000 µA 3 -55oC - 10 µA 1 +25oC -100 - nA 2 +125oC -1000 - nA 3 -55oC -100 - nA 1 +25oC - 100 nA 2 +125oC - 1000 nA 3 -55oC - 100 nA 1, 2, 3 +25oC, +125oC, -55oC - 50 mV 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA 1 +25oC 3.5 - mA 1 +25oC - -0.53 mA Output Current (Sink) Output Current (Source) IOL15 IOH5A VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA 1 +25oC - -3.5 mA 1 +25oC -2.8 -0.7 V VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V VDD = 2.8V, VIN = VDD or GND 7 +25oC VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B -55oC Output Current (Source) N Threshold Voltage P Threshold Voltage Functional IOH15 VNTH VPTH F VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10µA VOH > VOL < VDD/2 VDD/2 V Input Voltage Low (Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V Input Voltage High (Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V Input Voltage Low (Note 2) VIL VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC - 4 V Input Voltage High (Note 2) VIH VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC 11 - V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 7-1411 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. Specifications CD40182BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS (NOTES 1, 2) Propagation Delay P, G In to P, G Out and Carry Outs TPHL1 TPLH1 VDD = 5V, VIN = VDD or GND Propagation Delay Cn to Carry Outs TPHL2 TPLH2 VDD = 5V, VIN = VDD or GND Transition Time TTHL TTLH GROUP A SUBGROUPS TEMPERATURE 9 10, 11 9 10, 11 VDD = 5V, VIN = VDD or GND +25oC +125oC, -55oC +25oC o o +125 C, -55 C o LIMITS MIN MAX UNITS - 400 ns - 540 ns - 480 ns - 648 ns 9 +25 C - 200 ns 10, 11 +125oC, -55oC - 270 ns NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC - 5 µA +125oC - 150 µA VDD = 10V, VIN = VDD or GND VDD = 15V, VIN = VDD or GND Output Voltage VOL VDD = 5V, No Load 1, 2 1, 2 1, 2 -55 C, +25 C - 10 µA +125oC - 300 µA o o - 10 µA +125oC - 600 µA +25oC, +125oC, - 50 mV -55oC, +25oC -55oC Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC 4.95 - V Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC 9.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA -55oC 0.64 - mA +125oC 0.9 - mA -55oC 1.6 - mA +125oC 2.4 - mA -55oC 4.2 - mA Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) Input Voltage Low IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VIL VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V 1, 2 1, 2 1, 2 VDD = 5V, VOUT = 2.5V 1, 2 VDD = 10V, VOUT = 9.5V VDD =15V, VOUT = 13.5V VDD = 10V, VOH > 9V, VOL < 1V 7-1412 1, 2 1, 2 1, 2 +125oC - -0.36 mA -55oC - -0.64 mA +125oC - -1.15 mA -55oC - -2.0 mA +125oC - -0.9 mA -55oC - -1.6 mA +125oC - -2.4 mA -55oC - -4.2 mA +25oC, +125oC, -55oC - 3 V Specifications CD40182BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Input Voltage High SYMBOL VIH CONDITIONS VDD = 10V, VOH > 9V, VOL < 1V NOTES TEMPERATURE MIN MAX UNITS 1, 2 +25oC, +125oC, 7 - V -55oC 1, 2, 3 +25oC - 200 ns VDD = 15V 1, 2, 3 +25o C - 150 ns VDD = 10V 1, 2, 3 +25oC - 240 ns VDD = 15V 1, 2, 3 +25oC - 180 ns 1, 2, 3 +25oC - 100 ns 1, 2, 3 +25oC - 80 ns 1, 2 +25oC - 7.5 pF Propagation Delay P, G In to P, G Out and Carry Outs TPHL1 TPLH1 VDD = 10V Propagation Delay Cn to Carry Outs TPHL2 TPLH2 Transition Time Input Capacitance TTHL TTLH VDD = 10V VDD = 15V CIN Any Input NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K., Input TR, TF < 20ns. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC - 25 µA o -2.8 -0.2 V o N Threshold Voltage VNTH N Threshold Voltage Delta ∆VTN P Threshold Voltage VTP P Threshold Voltage Delta ∆VTP Functional F VDD = 10V, ISS = -10µA 1, 4 +25 C VDD = 10V, ISS = -10µA 1, 4 +25 C - ±1 V VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V VSS = 0V, IDD = 10µA VDD = 18V, VIN = VDD or GND 1, 4 +25 C - ±1 V 1 +25oC VOH > VDD/2 VOL < VDD/2 V 1, 2, 3, 4 +25oC - 1.35 x +25oC Limit ns o VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 3. See Table 2 for +25oC limit. NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-2 IDD ± 1.0µA Output Current (Sink) IOL5 ± 20% x Pre-Test Reading IOH5A ± 20% x Pre-Test Reading Output Current (Source) 7-1413 Specifications CD40182BMS TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD GROUP A SUBGROUPS Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A 100% 5004 1, 7, 9, Deltas 100% 5004 1, 7, 9 100% 5004 1, 7, 9, Deltas CONFORMANCE GROUP PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group B IDD, IOL5, IOH5A 100% 5004 2, 3, 8A, 8B, 10, 11 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample 5005 1, 7, 9 Sample 5005 1, 2, 3, 8A, 8B, 9 Group A Group D READ AND RECORD Subgroups 1, 2, 3, 9, 10, 11 Subgroups 1, 2 3 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS Group E Subgroup 2 TEST READ AND RECORD MIL-STD-883 METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD 5005 1, 7, 9 Table 4 1, 9 Table 4 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD Static Burn-In 1 (Note 1) 7, 9 - 12 1 - 6, 8, 13 - 15 16 Static Burn-In 2 (Note 1) 7, 9 - 12 8 1 - 6, 13 - 16 Dynamic BurnIn (Note 1) - 8 16 7, 9 - 12 8 1 - 6, 13 - 16 Irradiation (Note 2) 9V ± -0.5V 50kHz 25kHz 7, 9 - 12 1 - 6, 14, 15 13 NOTES: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V TABLE 9. TERMINAL DESIGNATIONS DESIGNATION TERM. G0, G1, G2, G3 3, 1, 14, 5 Active-Low Carry-Generate Inputs P0, P1, P2, P3 4, 2, 15, 6 Active-Low Carry-Propagate Inputs Cn 13 Cn + x, Cn + y, Cn + z 12, 11, 9 7-1414 FUNCTION Active-High Carry Input Active-High Carry Outputs Specifications CD40182BMS TABLE 9. TERMINAL DESIGNATIONS (Continued) DESIGNATION TERM. FUNCTION G 10 Active-Low Group Carry-Generate Output P 7 Active-Low Group Carry-Propagate Output Logic Diagram P 7 G P3 10 * 6 G3 * 5 Cn + z P2 * 9 15 G2 * 14 P1 * Cn + y 2 VDD 11 G1 * 1 P0 * 4 Cn + x VSS G0 * 12 3 *ALL INPUTS ARE PROTECTED BY COS/MOS PROTECTION NETWORK Cn * 13 FIGURE 1. CD40182BMS LOGIC DIAGRAM CD40182BMS LOGIC EQUATIONS Cn + x = G0 + P0 • Cn Cn + y = G1 + P1 • G0 + P1 • P0 • Cn Cn + z = G2 + P2 • G1 + P2 • P1 • G0 + P2 • P1 • P0 • Cn G = G3 + P3 • G2 + P3 • P2 • G1 + P3 • P2 • P1 • G0 P = P3 • P2 • P1 • P0 7-1415 CD40182BMS AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = 15V 25 20 15 10V 10 5 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) GATE-TO-SOURCE VOLTAGE (VGS) = -5V 0 -5 -15 -20 -25 -15V 10.0 10V 7.5 5.0 2.5 5V 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 0 -10 -10V GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 FIGURE 3. MIMIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS -30 0 AMBIENT TEMPERATURE (TA) = +25oC OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC 15.0 0 FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC 0 GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 -10V -15V FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS -10 -15 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) 30 OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) Typical Performance Characteristics FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 1416 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 CD40182BMS Typical Performance Characteristics PROPAGATION DELAY TIME (tPHL, tPLH) (ns) (Continued) TRANSITION TIME (tTHL, tTLH) (ns) AMBIENT TEMPERATURE (TA) = +25oC 200 150 SUPPLY VOLTAGE (VDD) = 5V 100 10V 15V 50 0 0 20 AMBIENT TEMPERATURE (TA) = +25oC 350 300 250 200 150 10V 100 20 30 40 50 60 70 80 90 FIGURE 7. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (P, G IN TO P, G OUT AND CARRY-OUTS) 2 SUPPLY VOLTAGE (VDD) = 15V 8 6 4 104 2 8 6 4 103 10V 2 10V 8 6 4 102 5V CL = 50pF CL = 15pF 2 2 4 6 8 2 4 6 8 2 4 6 8 2 4 6 8 103 10 102 INPUT FREQUENCY (fI) (kHz) 1 104 FIGURE 8. TYPICAL POWER DISSIPATION AS A FUNCTION OF INPUT FREQUENCY (4) CD40181BMS CARRY IN Cn Cn G P G0 P0 Cn Cn + x 100 LOAD CAPACITANCE (CL) (pF) AMBIENT TEMPERATURE (TA) = +25oC 6 4 POWER DISSIPATION (PD) (µW) 10 0 FIGURE 6. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE 105 15V 50 40 60 80 100 LOAD CAPACITANCE (CL) (pF) 106 8 SUPPLY VOLTAGE (VDD) = 5V G P G1 P1 Cn Cn + y G P G2 P2 Cn + z Cn G P G3 P3 G P CD40182BMS CARRY OUT LOOK-AHEAD OUTPUTS FIGURE 9. 16-BIT TWO-LEVEL LOOK-AHEAD ALU 7-1417 CD40182BMS (16) CD40181BMS Cn G P Cn Cn G P G0 P0 Cn + x G1 P1 Cn G P Cn + y G2 P2 Cn G P Cn + z G3 P3 G P Cn Cn G P G0 P0 Cn + x G1 P1 Cn Cn G P Cn + y G2 P2 Cn G P G0 P0 Cn + z G3 P3 Cn Cn CD40182BMS CD40182BMS G P G0 P0 G P G1 P1 Cn + x Cn + y Cn CD40182BMS FIGURE 10. 64-BIT FULL CARRY LOOK-AHEAD ALU IN 3 LEVELS CD40181BMS Cn Cn + 4 Cn Cn + 4 Cn G P Cn G P Cn Cn Cn+4 G P Cn+4 Cn G0 P0 Cn + x G1 P1 Cn + y G2 P2 Cn + z G3 P3 Cn Cn G P G0 P0 Cn + x Cn G P G1 P1 Cn + y Cn CD40182BMS CD40181BMS G P FIGURE 11. COMBINED TWO-LEVEL LOOK-AHEAD AND RIPPLE-CARRY ALU Chip Dimensions and Pad Layout METALLIZATION: PASSIVATION: BOND PADS: Thickness: 11kÅ − 14kÅ, AL. 10.4kÅ - 15.6kÅ, Silane 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches The photographs and dimensions of each CMOS chip represent a chip when it is part of the wafer. When the wafer is separated into individual chips, the angle of cleavage may vary with respect to the chip face for different chips. The actual dimensions of the isolated chip, therefore, may differ slightly from the nominal dimensions shown. The user should consider a tolerance of -3 mils to +16 mils applicable to the nominal dimensions shown. Dimension in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). 7-1418