CM1230 2, 4, and 8-Channel Low-Capacitance ESD Protection Array Product Description The CM1230 is a family of 2, 4 and 8 channel, very low capacitance ESD protection diode arrays in a CSP form factor. It is ideal for protecting systems with high data and clock rates or for circuits that need low capacitive loading. Each channel consists of a pair of ESD diodes that act as clamp diodes to steer ESD current pulses to either the positive or negative supply rail. A Zener diode is integrated between the positive and negative supply rails. The VCC rail is protected from ESD strikes and eliminates the need for a bypass capacitor to absorb positive ESD strikes to ground. Each channel can safely dissipate ESD strikes of ±8 kV, meeting the Level 4 requirement of the IEC61000−4−2 international standard as well as ±15 kV air discharges per the IEC61000−4−2 specification. Using the MIL−STD−883 (Method 3015) specification for Human Body Model (HBM) ESD, the pins are protected for contact discharges at greater than ±15 kV. This device is well−suited for next generation wireless handsets that implement high−speed serial interface solutions for the LCD display and camera interfaces. In these designs, a tolerance above 1.5 pF cannot be tolerated when high data rates are transferred between the baseband choppiest and the LCD driver/controller Is. Higher capacitive loading normally causes the rise and fall times to slow which hampers the functionality of circuit and operation of the wireless handset. The CM1230 incorporates OptiGuardt which results in improved reliability at assembly. The CM1230 is available in a s p a c e −s a v i n g , l o w p r o f i l e C h i p S c a l e P a c k a g e w i t h RoHS−compliant, lead−free finishing. Features • Two, Four, and Eight Channels of ESD Protection • Provides ESD Protection to IEC61000−4−2 Level 4 • • • • • • • • • ±8 kV Contact Discharge & ±15 kV Air Discharge Low Loading Capacitance of 0.8 pF Typical Minimal Capacitance Change with Temperature and Voltage Channel I/O to GND Capacitance Difference of 0.02 pF Typical is Ideal for Differential Signals Channel I/O to I/O Capacitance 0.15 pF Typical Zener Diode Protects Supply Rail and Eliminates the Need for External By−pass Capacitors Each I/O Pin Can Withstand Over 1000 ESD Strikes* Available in 4, 6 and 10 Bump Chip Scale Packages (CSP) OptiGuardt Coated for Improved Reliability at Assembly These Devices are Pb−Free and are RoHS Compliant Applications • I/O Port Protection for Mobile Handsets, Notebook Computers, http://onsemi.com WLCSP4 CP SUFFIX CASE 567CS WLCSP6 CP SUFFIX CASE 567BB WLCSP10 CP SUFFIX CASE 567BG MARKING DIAGRAM L MG G L30 MG G L308 MG G CSP−4 CSP−6 CSP−10 Lxxx = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Device Package Shipping† CM1230−02CP (Note 1) CSP−4 3,500/Tape & Reel (Pb−Free) CM1230−J2CP (Note 1) CSP−4 3,500/Tape & Reel (Pb−Free) CM1230−04CP CSP−6 3,500/Tape & Reel (Pb−Free) CM1230−08CP CSP−10 3,500/Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. *Standard test condition is IEC61000−4−2 level 4 test circuit with each (AOUT/BOUT) pin subjected to ±12 kV contact discharge for 1000 pulses. Discharges are timed at 1 second intervals and all 1000 strikes are completed in one continuous test run. 1. CM1230−02CP and CM1230−J2CP are the same mechanical package. Only difference is the Pin 1 orientation (‘+’ mark) on the tape and reel. DSCs, MP3 Players, PDAs, etc. Including USB, 1394 and Serial ATA • Handheld PCs/PDAs use High−speed Serial Interfaces • LCD and Camera Modules Wireless Handsets • LCD and Camera Data Lines in Wireless Handsets that • © Semiconductor Components Industries, LLC, 2012 January, 2012 − Rev. 4 1 Publication Order Number: CM1230/D CM1230 ELECTRICAL SCHEMATIC VP VP CH3 CH1 VN CH2 CH8 CM1230−02CP/ CM1230−J2CP CH1 CH2 CH6 CH5 CH3 CH4 CM1230−08CP PACKAGE / PINOUT DIAGRAMS 2−Channel, 4−Bump CSP Name Type Description A1 VN GND B1 CH2 I/O ESD Channel A2 CH1 I/O ESD Channel B2 VP PWR Top View (Bumps Down View) Bottom View (Bumps Up View) Orientation Marking Orientation Marking Negative Voltage Supply Rail Positive Voltage Supply Rail A + 1 A2 L B 4−Channel, 6−Bump CSP 2 A1 B2 B1 CM1230−02/J2 4−bump CSP Package Description CH1 I/O ESD Channel CH2 I/O ESD Channel A2 VP PWR Positive Voltage Supply Rail B2 VN GND Negative Voltage Supply Rail A3 CH3 I/O ESD Channel B3 CH4 I/O ESD Channel Orientation Marking A + 1 Orientation Marking 2 3 A1 A1 B1 A3 A2 A1 L30 B B3 B2 B1 8−Channel, 10−Bump CSP CM1230−04 6−bump CSP Package Pin Name Type Description A1 CH1 I/O ESD Channel B1 CH2 I/O ESD Channel A2 CH3 I/O ESD Channel B2 CH4 I/O ESD Channel A3 VP PWR Positive Voltage Supply Rail A B3 VN GND Negative Voltage Supply Rail B A4 CH5 I/O ESD Channel B4 CH6 I/O ESD Channel A5 CH7 I/O ESD Channel B5 CH8 I/O ESD Channel Orientation Marking + 1 2 Orientation Marking 3 4 L308 5 A5 A4 A3 A2 A1 B5 B4 B3 B2 B1 CM1230−08 10−bump CSP Package http://onsemi.com 2 A1 Pin Type VN CM1230−04CP Table 1. PIN DESCRIPTIONS Name VP CH2 VN Pin CH7 A1 CH1 CH4 CM1230 SPECIFICATIONS Table 2. ABSOLUTE MAXIMUM RATINGS Parameter Rating Units 6.0 V Operating Temperature Range –40 to +85 °C Storage Temperature Range –65 to +150 °C (VN − 0.5) to (VP + 0.5) V Operating Supply Voltage (VP − VN) DC Voltage at any Channel Input Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 3. STANDARD OPERATING CONDITIONS Parameter Operating Temperature Range Rating Units –40 to +85 °C Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note2) Symbol Conditions VP Operating Supply Voltage (VP−VN) IP Operating Supply Current (VP−VN) = 3.3 V VF Diode Forward Voltage Top Diode Bottom Diode IF = 8 mA; TA = 25°C Channel Leakage Current Channel Input Capacitance ILEAK CIN DCIN CMUTUAL VESD 2. 3. 4. 5. 6. Parameter Min Max Units 3.3 5.5 V 8.0 mA V 0.80 0.80 0.95 0.95 TA = 25°C; VP = 5 V, VN = 0 V, VIN = 0 V to 5 V ±0.1 ±1.0 mA At 1 MHz, VP = 3.3 V, VN = 0 V, VIN = 1.65 V 0.80 1.2 pF Channel Input Capacitance Matching At 1 MHz, VP = 3.3 V, VN = 0 V, VIN = 1.65 V 0.02 pF Mutual Capacitance between signal pin and adjacent signal pin At 1 MHz, VP = 3.3 V, VN = 0 V, VIN = 1.65 V 0.15 pF In−system ESD Protection Peak Discharge Voltage at any channel input, in system a) Contact discharge per IEC 61000−4−2 standard b) Human Body Model, MIL−STD−883, Method 3015 0.60 0.60 Typ kV TA = 25°C (Notes 4 and 5) ±8 TA = 25°C (Notes 3 and 5) ±15 VCL Channel Clamp Voltage Positive Transients Negative Transients TA = 25°C, IPP = 1A, tP = 8/20 mS (Note 5) RDYN Dynamic Resistance Positive Transients Negative Transients IPP = 1 A, tP = 8/20 mS Any I/O pin to Ground (Note 5) +9.8 –1.8 0.76 0.56 All parameters specified at TA = –40°C to +85°C unless otherwise noted. Human Body Model per MIL−STD−883, Method 3015, CDischarge = 100 pF, RDischarge = 1.5 KW, VP = 3.3 V, VN grounded. Standard IEC 61000−4−2 with CDischarge = 150 pF, RDischarge = 330 W, VP = 3.3 V, VN grounded. These measurements performed with no external capacitor on VP. Measured under pulsed conditions, pulse width = 0.7 ms, maximum current = 1.5 A. http://onsemi.com 3 V W CM1230 PERFORMANCE INFORMATION Input Channel Capacitance Performance Curves Figure 1. Typical Variation of CIN vs. VIN (f = 1 MHz, VP = 3.3 V, VN = 0 V, 0.1 mF chip capacitor between VP and VN, TA = 255C) Figure 2. Typical Variation of CIN vs. Temp (f = 1 MHz, VIN = 30 mV, VP = 3.3 V, VN = 0 V, 0.1 mF chip capacitor between VP and VN) http://onsemi.com 4 CM1230 PERFORMANCE INFORMATION (Cont’d) Typical Filter Performance (nominal conditions unless specified otherwise, 50 W Environment) Figure 3. Insertion Loss vs. Frequency (0 V DC Bias, VP = 3.3 V) Figure 4. Insertion Loss vs. Frequency (2.5 V DC Bias, VP = 3.3 V) http://onsemi.com 5 CM1230 APPLICATION INFORMATION Table 5. PRINTED CIRCUIT BOARD RECOMMENDATIONS Parameter Value Pad Size on PCB 0.275 mm Pad Shape Round Pad Definition Non−Solder Mask defined pads Solder Mask Opening 0.325 mm Round Solder Stencil Thickness 0.125 − 0.150 mm Solder Stencil Aperture Opening (laser cut, 5% tapered walls) 0.330 mm Round Solder Flux Ratio 50/50 by volume Solder Paste Type No Clean Pad Protective Finish OSP (Entek Cu Plus 106A) Tolerance − Edge To Corner Ball ±50 mm Solder Ball Side Coplanarity ±20 mm Maximum Dwell Time Above Liquidous 60 seconds Maximum Soldering Temperature for Lead−free Devices using a Lead−free Solder Paste Non−Solder Mask Defined Pad 0.275 mm DIA. Solder Stencil Opening 0.330 mm DIA. Solder Mask Opening 0.325 mm DIA. Figure 5. Recommended Non−Solder Mask Defined Pad Illustration Figure 6. Lead−free (SnAgCu) Solder Ball Reflow Profile http://onsemi.com 6 260°C CM1230 PACKAGE DIMENSIONS WLCSP4, 0.96x0.96 CASE 567CS ISSUE O ÈÈ ÈÈ D PIN A1 REFERENCE 2X A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO SPHERICAL CROWNS OF SOLDER BALLS. B E DIM A A1 A2 b D E e 0.05 C 2X 0.05 C TOP VIEW A2 MILLIMETERS MIN MAX 0.61 0.69 0.21 0.28 0.41 REF 0.29 0.34 0.96 BSC 0.96 BSC 0.50 BSC 0.05 C RECOMMENDED SOLDERING FOOTPRINT* A A1 0.05 C NOTE 3 SIDE VIEW A1 e b 4X PACKAGE OUTLINE SEATING PLANE C B 0.03 C 4X 0.50 PITCH e 0.05 C A B 0.25 0.50 DIMENSIONS: MILLIMETERS A 1 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 2 BOTTOM VIEW WLCSP6, 1.46x0.96 CASE 567BB ISSUE O D ÈÈ PIN A1 REFERENCE 2X 0.05 C 2X A 0.05 C E DIM A A1 A2 b D E e TOP VIEW OptiGuard Option ÉÉÉÉ 0.05 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO SPHERICAL CROWNS OF SOLDER BALLS. B A2 RECOMMENDED SOLDERING FOOTPRINT* A 0.05 C NOTE 3 6X 0.03 C e b 0.05 C A B C SIDE VIEW A1 MILLIMETERS MIN MAX 0.56 0.72 0.21 0.27 0.42 REF 0.29 0.35 1.46 BSC 0.96 BSC 0.50 BSC A1 SEATING PLANE e 0.50 PITCH B A PACKAGE OUTLINE 6X 0.25 0.50 DIMENSIONS: MILLIMETERS 1 2 3 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. BOTTOM VIEW http://onsemi.com 7 CM1230 PACKAGE DIMENSIONS WLCSP10, 2.46x0.96 CASE 567BG ISSUE O È È PIN A1 REFERENCE 2X 0.05 C 2X 0.05 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO SPHERICAL CROWNS OF SOLDER BALLS. A B D E DIM A A1 A2 b D E e TOP VIEW OptiGuard Option ÉÉÉÉÉÉ 0.05 C A2 RECOMMENDED SOLDERING FOOTPRINT* A A1 0.05 C NOTE 3 10X 0.03 C C SIDE VIEW A1 e b 0.05 C A B MILLIMETERS MIN MAX 0.56 0.72 0.21 0.27 0.42 REF 0.29 0.35 2.46 BSC 0.96 BSC 0.50 BSC PACKAGE OUTLINE SEATING PLANE 10X 0.50 e 0.50 PITCH B 0.25 DIMENSIONS: MILLIMETERS A 1 2 3 4 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 5 BOTTOM VIEW OptiGuard is a trademark of Semiconductor Components Industries, LLC. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 http://onsemi.com 8 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative CM1230/D