MC74HCT4094A D

MC74HCT4094A
8-Bit Shift and Store
Register with LSTTL
Compatible Inputs
High−Performance Silicon−Gate CMOS
The MC74HCT4094A is a high speed CMOS 8−bit serial shift and
storage register. This device consists of an 8−bit shift register and latch
with 3−state output buffers. Data is shifted on positive clock (CP)
transitions. The data in the shift register is transferred to the storage
register when the Strobe (STR) input is high. The output buffers are
enabled when the Output Enable (OE) input is set high. Two serial
outputs (QS1, QS2) are available for cascading multiple devices.
The MC74HCT4094A can be used to interface TTL or CMOS
outputs to high speed CMOS inputs.
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MARKING
DIAGRAMS
16
SOIC−16
D SUFFIX
CASE 751B
16
1
HCT4094AG
AWLYWW
1
16
Features
• Wide Operating Voltage Range: 4.5 to 5.5 V
• Low Power Dissipation: ICC = < 10 mA
• In Compliance with the Requirements Defined by JEDEC
16
1
HCT
4094A
ALYWG
G
TSSOP−16
DT SUFFIX
CASE 948F
Standard No. 7A
1
• These are Pb−Free Devices
A
WL, L
YY, Y
WW, W
G, G
Typical Applications
• Serial−to−Parallel Conversion
• Remote Control Storage Register
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
March, 2011 − Rev. 0
1
Publication Order Number:
MC74HCT4094A/D
MC74HCT4094A
3
1
1
C2
15
CP
EN3
STR
QS1
9
SRG8
3
C1/
STR
1
16
VCC
QS2
10
D
2
15
OE
QP0
4
CP
3
14
QP4
QP1
4
13
QP5
5
5
QP0
QP1
5
12
QP6
QP2
6
6
QP2
6
11
QP7
QP3
7
7
QP3
7
10
QS2
QP4
14
14
GND
8
9
QS1
QP5
13
13
QP6
12
12
QP7
11
11
2
D
Figure 1. Pin Assignment
2
1D
2D
3
OE
9
10
15
Figure 2. Logic Symbol
2
D
3
CP
1
STR
15
OE
Figure 3. IEC Logic Symbol
8 – Stage Shift Register
8 – Bit Storage Register
3 – Stage Outputs
QP0
4
QP1
5
QP2
6
4
QP3
7
QP4
14
QP5
13
Figure 4. Functional Diagram
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2
QP6
12
QP7
11
QS2
10
QS1
9
MC74HCT4094A
STAGE 0
D
STAGES 1 TO 6
Q
D
Q
D
STAGE 7
CP
CP
Q
QS1
CP
FF7
CP
FF0
D
Q
D
CP
latch
D
D
Q
Q
CP
latch
CP
latch
STR
OE
QP0
QP1 QP2 QP3 QP4 QP5 QP6
Figure 5. Logic Diagram
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3
QP7
QS2
MC74HCT4094A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
– 0.5 to + 7.0
V
DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
VCC
DC Supply Voltage (Referenced to GND)
Vin
Vout
Iin
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 35
mA
ICC
DC Supply Current, VCC and GND Pins
± 75
mA
PD
Power Dissipation in Still Air,
500
450
mW
Tstg
Storage Temperature
– 65 to + 150
°C
SOIC Package†
TSSOP Package†
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating − SOIC Package: – 7 mW/°C from 65° to 125°C
TSSOP Package: − 6.1 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
DC Supply Voltage (Referenced to GND)
Min
Max
Unit
4.5
5.5
V
0
VCC
V
–55
+125
°C
0
500
ns
DC Input Voltage, Output Voltage
(Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time (Figure 1)
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4
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
MC74HCT4094A
FUNCTIONAL TABLE
INPUTS
PARALLEL OUTPUTS
SERIAL OUTPUTS
CP
OE
STR
D
QP0
QPn
QS1
QS2
↑
L
X
X
Z
Z
Q’6
NC
↓
L
X
X
Z
Z
NC
QP7
↑
H
L
X
NC
NC
Q’6
NC
↑
H
H
L
L
QPn−1
Q’6
NC
↑
H
H
H
H
QPn−1
Q’6
NC
↓
H
H
H
NC
NC
NC
QP7
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
Z = high impedance OFF−state
NC = no change
↑ = LOW−to−HIGH CP transition
↓ = HIGH−to−LOW CP transition
Q’6 = the information in the seventh register stage is transferred to the 8th register stage and QSn output at the positive clock edge
CLOCK INPUT
CP
DATA INPUT
D
STROBE INPUT
STR
OUTPUT ENABLE INPUT
OE
INTERNAL Q’0
FF0
OUTPUT
QP0
INTERNAL Q’6
FF6
OUTPUT
QP6
SERIAL OUTPUT
QS1
SERIAL OUTPUT
QS2
Z−state
Z−state
Figure 6. Timing Diagram
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5
MC74HCT4094A
DC CHARACTERISTICS
Guaranteed Limits
Symbol
VIH
VIL
VOH
VOL
Parameter
Test Conditions
VCC (V)
−555C to 255C
≤ 855C
≤ 1255C
Unit
V
Minimum High−Level Input
Voltage
VOUT = 0.1 V or VCC – 0.1 V
⎟IOUT⎟ ≤ 20 mA
4.5
2.0
2.0
2.0
5.5
2.0
2.0
2.0
Maximum Low−Level Input
Voltage
VOUT = 0.1 V or VCC – 0.1 V
⎟IOUT⎟ ≤ 20 mA
4.5
0.8
0.8
0.8
5.5
0.8
0.8
0.8
Minimum High−Level Output
Voltage
VIN = VIH or VIL
⎟IOUT⎟ ≤ 20 mA
4.5
4.4
4.4
4.4
5.5
5.4
5.4
5.4
VIN = VIH or VIL, ⎟IOUT⎟ = 6 mA
4.5
4.25
4.2
4.1
VIN = VIH or VIL, ⎟IOUT⎟ ≤ 20 mA
4.5
0.1
0.1
0.1
5.5
0.1
0.1
0.1
VIN = VIH or VIL, ⎟IOUT⎟ = 6 mA
4.5
0.25
0.3
0.4
Maximum Low−Level Output
Voltage
V
V
V
IIN
Maximum Input Leakage
Current
VIN = VCC or GND
5.5
±0.1
±1
±1
mA
IOZ
Maximum Tri−State Output
Leakage Current
VIN = VCC or GND
VOUT = VCC or GND
5.5
±0.5
±5
±10
mA
ICC
Maximum Quiescent Supply
Current
VIN = VCC or GND
5.5
4.0
40
80
mA
DICC
Additional Quiescent Supply
Current
Vin = 2.4V, Any One Input
Vin = VCC or GND, Other Inputs
Iout = 0mA
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6
5.5
≥ −55°C
25 to 125°C
2.9
2.4
mA
MC74HCT4094A
AC CHARACTERISTICS (tf = tr = 6 ns, CL = 50 pF)
Guaranteed Limits
Test Conditions
VCC (V)
−555C to 255C
tPHL, tPLH Maximum Propagation Delay
CP to QS1
Figure 7
4.5
30
38
45
ns
tPHL, tPLH Maximum Propagation Delay
CP to QS2
Figure 7
4.5
27
34
41
ns
tPHL, tPLH Maximum Propagation Delay
CP to QPn
Figure 7
4.5
39
49
59
ns
tPHL, tPLH Maximum Propagation Delay
STR to QPn
Figure 8
4.5
36
45
54
ns
tPZH, tPZL Maximum 3−State Output Enable Time
OE to QPn
Figure 9
4.5
35
44
53
ns
tPHZ, tPLZ Maximum 3−State Output Enable Time
OE to QPn
Figure 9
4.5
25
31
38
ns
tTHL, tTLH
Symbol
Parameter
≤ 855C
≤ 1255C
Unit
Maximum Output Transition Time
Figure 7
4.5
18
22
25
ns
tW
Minimum Clock Pulse Width
High or Low
Figure 7
4.5
16
20
24
ns
tW
Minimum Strobe Pulse Width
High
Figure 8
4.5
16
20
24
ns
tSU
Minimum Set−up Time
D to CP
Figure 10
4.5
10
13
15
ns
tSU
Minimum Set−up Time
CP to STR
Figure 8
4.5
20
25
30
ns
th
Minimum Hold Time
D to CP
Figure 10
4.5
3
3
3
ns
th
Minimum Hold Time
CP to STR
Figure 8
4.5
0
0
0
ns
Minimum Clock Pulse Frequency
Figure 7
4.5
30
24
20
MHz
10
10
10
pF
fMAX
Cin
Maximum Input Capacitance
−
Cout
Maximum Output Capacitance
−
15
15
15
pF
CPD
Power Dissipation Capacitance (Note 2)
−
140
140
140
pF
2. CPD is defined as the value of the IC’s equivalent capacitance from which the operating current can be calculated from:
ICC(operating) ≈ CPD x VCC x fIN x NSW where NSW = total number of outputs switching and fIN = switching frequency.
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7
MC74HCT4094A
AC WAVEFORMS
(VM = 1.3 V)
1/fMAX
3.0 V
3.0 V
CP Input
CP Input
VM
tw
tPLH
QPn, QS1
Output
tsu
tPHL
STR Input
50%
tTLH
QS2 Output
tPLH
tTHL
tW
tPLH
QPn Output
tTLH
OE Input
tPHL
50%
tTHL
Figure 7. Waveforms showing the clock
(CP) to output (QPn, QS1, QS2) propagation
delays, the clock pulse width and the
maximum clock frequency.
tf
th
50%
tPHL
50%
90%
VM
Figure 8. Waveforms showing the strobe
(STR) to output (QPn) propagation delays,
the strobe pulse width, the clock set−up
and hold times for the strobe input.
tr
3.0 V
3.0 V
VM
10%
D Input
50%
10%
tPZH
tPHZ
90%
QPn Output:
High − to − Off
Off − to − High
QPn, QS1, QS2
Output
50%
Outputs
Enabled
Outputs
Disabled
ÉÉÉ ÉÉÉÉ ÉÉÉ
ÉÉÉ ÉÉÉÉ ÉÉÉ
ÉÉÉ ÉÉÉÉ ÉÉÉ
tsu
tPZL
tPLZ
QPn Output:
Low − to − Off
Off − to − Low
VM
CP Input
Outputs
Enabled
tsu
th
th
VM
50%
The shaded areas indicate when
the input is permitted to change for
predictable output performance.
Figure 9. Waveforms showing the 3−state
enable and disable times for input OE.
Figure 10. Waveforms showing the data
set−up and hold times for the data input.
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8
MC74HCT4094A
TEST CIRCUITS
TEST POINT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
OUTPUT
DEVICE
UNDER
TEST
CL*
*Includes all probe and jig capacitance
1 kW
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
*Includes all probe and jig capacitance
Figure 11. AC Characteristics Load Circuits
ORDERING INFORMATION
Package
Shipping†
MC74HCT4094ADG
SOIC−16
(Pb−Free)
48 Units / Rail
MC74HCT4094ADR2G
SOIC−16
(Pb−Free)
2500 Tape & Reel
Device
MC74HCT4094ADT
TSSOP−16*
96 Units / Rail
MC74HCT4094ADTR2G
TSSOP−16*
2500 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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9
MC74HCT4094A
PACKAGE DIMENSIONS
TSSOP−16
DT SUFFIX
CASE 948F−01
ISSUE B
16X K REF
0.10 (0.004)
0.15 (0.006) T U
T U
M
V
S
S
S
ÇÇÇ
ÇÇÇ
ÉÉ
ÇÇÇ
ÉÉ
K
K1
2X
L/2
16
9
J1
B
−U−
L
SECTION N−N
J
PIN 1
IDENT.
8
1
N
0.15 (0.006) T U
S
0.25 (0.010)
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
N
F
DETAIL E
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
H
G
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
DETAIL E
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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10
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193 0.200
0.169 0.177
−−− 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.007
0.011
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0_
8_
MC74HCT4094A
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
−A−
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
9
−B−
1
P
8 PL
0.25 (0.010)
8
B
M
S
DIM
A
B
C
D
F
G
J
K
M
P
R
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
16 PL
0.25 (0.010)
M
T B
S
A
S
SOLDERING FOOTPRINT*
8X
6.40
16X
1.12
1
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
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MC74HCT4094A/D