NB7V33M D

NB7V33M
1.8V / 2.5V, 10GHz ÷4 Clock
Divider with CML Outputs
Multi−Level Inputs w/ Internal Termination
http://onsemi.com
Description
The NB7V33M is a differential B4 Clock divider with
asynchronous reset. The differential Clock inputs incorporate internal
50 W termination resistors and will accept LVPECL, CML and LVDS
logic levels. The NB7V33M produces a ÷4 output copy of an input
Clock operating up to 10 GHz with minimal jitter. The Reset pin is
asserted on the rising edge. Upon powerup, the internal flip*flops
will attain a random state; the Reset allows for the synchronization of
multiple NB7V33M’s in a system. The 16 mA differential CML
output provides matching internal 50 W termination which guarantees
400 mV output swing when externally receiver terminated with 50 W
to VCC.
The NB7V33M is the B4 version of the NB7V32M (B2) and is
offered in a low profile 3 mm x 3 mm 16−pin QFN package.
The NB7V33M is a member of the GigaComm™ family of high
performance clock products. Application notes, models, and support
documentation are available at www.onsemi.com.
Features
•
•
•
•
•
•
•
•
•
•
Maximum Input Clock Frequency > 10 GHz, typical
260 ps Typical Propagation Delay
35 ps Typical Rise and Fall Times
Differential CML Outputs, 400 mV Peak−to−Peak, Typical
Operating Range: VCC = 1.71 V to 2.625 V with GND = 0 V
Internal 50 W Input Termination Resistors
Random Clock Jitter < 0.8 ps RMS
QFN−16 Package, 3 mm x 3 mm
−40ºC to +85°C Ambient Operating Temperature
These are Pb−Free Devices
MARKING
DIAGRAM*
16
1
NB7V
33M
ALYW G
G
1
QFN16
MN SUFFIX
CASE 485G
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
R
RESET
VTCLK
50 W
CLK
CLK
B4
50 W
Q0
Q0
VTCLK
VREFAC
VCC
GND
Figure 1. Simplified Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2010
January, 2010 − Rev. 2
1
Publication Order Number:
NB7V33M/D
NB7V33M
VCC
R
16
15
Exposed
Pad (EP)
VCC VCC
14
13
VTCLK
1
12 VCC
CLK
2
11 Q
CLK
3
10 Q
VTCLK
4
9
NB7V33M
5
6
Table 1. TRUTH TABLE
7
CLK
CLK
R
Q
Q
x
x
H
L
H
Z
W
L
CLK ÷ 4
CLK ÷ 4
Z = Low to High Transition
W = High to Low Transition
X = Don’t Care
VCC
8
VREFAC GND GND GND
Figure 2. Pin Configuration (Top View)
Table 2. PIN DESCRIPTION
Pin
Name
I/O
Description
1
VTCLK
−
2
CLK
LVPECL, CML,
LVDS Input
Non−inverted Differential CLK Input. Note 1.
3
CLK
LVPECL, CML,
LVDS Input
Inverted Differential CLK Input. Note 1.
4
VTCLK
−
Internal 50 W Termination Pin for CLK
5
VREFAC
−
Internally Generated Output Voltage Reference for Capacitor−Coupled Inputs, Only
6
GND
−
Negative Supply Voltage
7
GND
−
Negative Supply Voltage
8
GND
−
Negative Supply Voltage
9
VCC
−
Positive Supply Voltage. Note 2.
10
Q
CML Output
Inverted Differential Output
11
Q
CML Output
Non−Inverted Differential Output
12
VCC
−
Positive Supply Voltage. Note 2.
13
VCC
−
Positive Supply Voltage. Note 2.
14
VCC
−
Positive Supply Voltage. Note 2.
15
R
LVCMOS Input
16
VCC
−
Positive Supply Voltage. Note 2.
−
EP
−
The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for
improved heat transfer out of package. The exposed pad must be attached to a heat−sinking
conduit. The pad is electrically connected to the die, and must be electrically and thermally connected to GND on the PC board.
Internal 50 W Termination Pin for CLK
Asynchronous Reset Input. Internal 75 kW pulldown to GND.
1. In the differential configuration when the input termination pins (VTCLK/VTCLK) are connected to a common termination voltage or left open,
and if no signal is applied on CLK/CLK input, then the device will be susceptible to self−oscillation. Q/Q outputs have internal 50 W source
termination resistors.
2. All VCC and GND pins must be externally connected to a power supply for proper operation.
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NB7V33M
Table 3. ATTRIBUTES
Characteristics
ESD Protection
Value
Human Body Model
Machine Model
> 4 kV
> 200 V
QFN16
Level 1
RPD − Reset Input Pulldown Resistor
75 kW
Moisture Sensitivity (Note 3)
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Transistor Count
190
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
3. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC
Positive Power Supply
GND = 0 V
3.0
V
VIN
Positive Input Voltage
GND = 0 V
−0.5 to VCC +0.5
V
VINPP
Differential Input Voltage |D − D|
1.89
V
IIN
Input Current Through RT (50 W Resistor)
$40
mA
IOUT
Output Current Through RT (50 W Resistor)
$40
mA
IVFREFAC
VREFAC Sink/Source Current
$1.5
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
(Note 4)
QFN−16
QFN−16
42
35
°C/W
qJC
Thermal Resistance (Junction−to−Case)
(Note 4)
QFN−16
4
°C/W
Tsol
Wave Solder Pb−Free
265
°C
0 lfpm
500 lfpm
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
4. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NB7V33M
Table 5. DC CHARACTERISTICS POSITIVE CML OUTPUT VCC = 1.71 V to 2.625 V; GND = 0 V; TA = −40°C to 85°C (Note 5)
Symbol
Characteristic
Min
Typ
Max
Unit
95
85
115
100
mA
VCC – 30
2470
1770
VCC – 10
2490
1790
VCC
2500
1800
mV
VCC – 650
1850
VCC – 600
1200
VCC – 550
1950
VCC – 500
1300
VCC – 450
2050
VCC – 400
1400
mV
1050
VCC − 100
mV
POWER SUPPLY CURRENT
ICC
Power Supply Current (Inputs and Outputs Open)
VCC = 2.5 V ± 5%
VCC = 1.8 V ± 5%
CML OUTPUTS
VOH
Output HIGH Voltage (Note 6)
VOL
Output LOW Voltage (Note 6)
VCC = 2.5 V
VCC = 1.8 V
VCC = 2.5 V
VCC = 1.8 V
DIFFERENTIAL INPUTS DRIVEN SINGLE−ENDED (Note 7) (Figures 5 & 6)
Vth
Input Threshold Reference Voltage Range (Note 8)
VIH
Single−ended Input HIGH Voltage
Vth + 100
VCC
mV
VIL
Single−ended Input LOW Voltage
GND
Vth − 100
mV
VISE
Single−ended Input Voltage (VIH − VIL)
200
1200
mV
VCC – 850
VCC – 750
VCC – 500
VCC – 450
VREFAC
VREFAC
Output Reference Voltage @100 mA for Capacitor− Coupled Inputs, Only
VCC = 2.5 V
VCC = 1.8 V
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 7 & 8) (Note 9)
VIHD
Differential Input HIGH Voltage
1100
VCC
mV
VILD
Differential Input LOW Voltage
GND
VCC − 100
mV
VID
Differential Input Voltage (VIHD − VILD)
100
1200
mV
VCMR
Input Common Mode Range (Differential Configuration, Note 10) (Figure 9)
1050
VCC − 50
mV
IIH
Input HIGH Current (VTx/VTx Open)
−150
150
mA
IIL
Input LOW Current (VTx/VTx Open)
−150
150
mA
CONTROL INPUT (Reset pin)
VIH
Input HIGH Voltage for Control Pin
VCC − 200
VCC
mV
VIL
Input LOW Voltage for Control Pin
GND
200
mV
IIH
Input HIGH Current
−150
150
mA
IIL
Input LOW Current
−150
150
mA
TERMINATION RESISTORS
RTIN
Internal Input Termination Resistor
45
50
55
W
RTOUT
Internal Output Termination Resistor
45
50
55
W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with VCC.
6. CML outputs loaded with 50−W to VCC for proper operation.
7. Vth, VIH, VIL,, and VISE parameters must be complied with simultaneously.
8. Vth is applied to the complementary input when operating in single−ended mode.
9. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously.
10. VCMR min varies 1:1 with GND, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential
input signal.
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NB7V33M
Table 6. AC CHARACTERISTICS VCC = 1.71 V to 2.625 V; GND = 0 V; TA = −40°C to 85°C (Note 11)
Symbol
Min
Typ
fMAX
Maximum Input Clock Frequency
Characteristic
10
11
GHz
VOUTPP
Output Voltage Amplitude (@ VINPPmin) fin ≤ 10 GHz
(Note 12) (Figure 3)
260
400
mV
tPLH,
tPHL
Propagation Delay to Differential Outputs,
@ 1 GHz, measured at differential crosspoint
150
500
200
600
tPLH TC
Propagation Delay Temperature Coefficient
tskew
Duty Cycle Skew (Note 13)
Device − Device skew (tpdmax – tpdmin)
tRR
Reset Recovery (See Figure 16)
550
135
tPW
Minimum Pulse Width R
500
200
tDC
Output Clock Duty Cycle (Reference Duty Cycle = 50%) fin v 10 GHz
45
50
fN
Phase Noise, fc = 1 GHz
tŘfN
CLK/CLK to Q, Q
R to Q, Q
Max
Unit
350
700
50
ps
Dfs/°C
20
50
10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
40 MHz
ps
ps
ps
55
%
−144
−147
−152
−152
−152
−153
dBc
Integrated Phase Jitter (Figure x) fc = 1 GHz, 12 kHz − 20 MHz Offset
35
fs
tJITTER
RJ – Output Random Jitter (Note 14) fin v 10.0 GHz
0.2
VINPP
Input Voltage Swing (Differential Configuration) (Figure 11) (Note 15)
200
tr, tf
Output Rise/Fall Times @ 1 GHz (20% − 80%), Q, Q
20
35
0.8
ps RMS
1200
mV
60
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Measured using a 1 GHz, VINPPmin, 50% duty−cycle clock source. All output loading with external 50 W to VCC. Input edge rates 40 ps
(20% − 80%).
12. Output voltage swing is a single−ended measurement operating in differential mode.
13. Duty cycle skew is defined only for differential operation when the delays are measured from cross−point of the inputs to the cross−point
of the outputs. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 1 GHz. Skew
is measured between outputs under identical transitions and conditions.
14. Additive RMS jitter with 50% duty cycle clock signal.
15. Input voltage swing is a single−ended measurement operating in differential mode.
VOUTPP, OUTPUT VOLTAGE
AMPLITUDE (mV)
500
450
400
350
300
250
200
0
2
4
6
8
10
fin, CLOCK INPUT FREQUENCY (GHz)
Figure 3. Output Voltage Amplitude (VOUTPP) vs. Input Frequency (fin) at Ambient Temperature (Typical)
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NB7V33M
VTCLK
VCC
50 W
CLK
I
CLK
50 W
VTCLK
Figure 4. Input Structure
VCC
Vthmax
CLK
VIH
VIHmax
VILmax
Vth
VIH
Vth
VIL
Vth
VIL
Vthmin
CLK
Vth
Figure 6. Vth Diagram
CLK
CLK
CLK
CLK
VIHD(MAX)
VIHD
VILD
CLK
VILD(MAX)
VINPP = VIH(CLK) − VIL(CLK)
CLK
VIHD
VID = VIHD − VILD
Q
VILD
VOUTPP = VOH(Q) − VOL(Q)
Q
VIHD(MIN)
GND
VID = |VIHD(D) − VILD(D)|
Figure 8. Differential Inputs Driven Differentially
Figure 7. Differential Inputs
Driven Differentially
VCMR
VILmin
GND
Figure 5. Differential Input Driven
Single−Ended
VCC
VIHmin
tPHL
tPLH
VILD(MIN)
Figure 9. VCMR Diagram
Figure 10. AC Reference Measurement
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NB7V33M
VCC
VCC
VCC
ZO = 50 W
LVPECL
Driver
Vth
ZO = 50 W
VCC
ZO = 50 W CLK
NB7V33M
CLK
50 W
VTCLK
VTCLK
VTCLK
LVDS
Driver
VTCLK
ZO = 50 W
50 W
CLK
50 W
50 W
CLK
Vth = VCC − 2 V
VEE
NB7V33M
GND
GND
GND
Figure 11. LVPECL Interface
Figure 12. LVDS Interface
VCC
VCC
ZO = 50 W
CML
Driver
VCC
CLK
NB7V33M
50 W
VTCLK
VTCLK
ZO = 50 W
VT = VT = VCC
50 W
CLK
GND
GND
Figure 13. Standard 50 W Load CML Interface
VCC
ZO = 50 W
Differential
Driver
VCC
VCC
Vth
CLK
VTCLK
VTCLK
ZO = 50 W
VCC
ZO = 50 W
NB7V33M
50 W
Single−Ended
Driver
50 W
Vth
VTCLK
VTCLK
CLK
NB7V33M
50 W
50 W
CLK
Vth = VREFAC
GND
CLK
Vth = VREFAC
GND
GND
GND
Figure 15. Capacitor−Coupled Single−Ended Interface
(VTCLK/VTCLK Connected to VREFAC; VREFAC Bypassed
to Ground with 0.1 mF Capacitor)
Figure 14. Capacitor−Coupled Differential Interface
(VTCLK/VTCLK Connected to VREFAC; VREFAC Bypassed
to Ground with 0.1 mF Capacitor)
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NB7V33M
50%
50%
VOUTPP = VOH(Q) − VOL(Q)
Q
tPLH
tPHL
50%
50%
CLK
tRR(MIN)
R
50%
Figure 16. AC Reference Measurement (Timing Diagram)
VCC
VCC (Receiver)
50 W
50 W
50 W
50 W
16 mA
GND
Figure 17. Typical CML Output Structure and Termination
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VINPP = VIH(CLK) − VIL(CLK)
NB7V33M
VCC
50 W
Z = 50 W
DUT
Driver
Device
50 W
Q
D
Receiver
Device
Z = 50 W
Q
D
Figure 18. Typical Termination for CML Output Driver and Device Evaluation
DEVICE ORDERING INFORMATION1
Package
Shipping†
NB7V33MMNG
QFN−16
(Pb−Free)
123 Units / Rail
NB7V33MMNHTBG
QFN−16
(Pb−Free)
100 / Tape & Reel
NB7V33MMNTXG
QFN−16
(Pb−Free)
3000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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NB7V33M
PACKAGE DIMENSIONS
16 PIN QFN
CASE 485G−01
ISSUE D
D
ÇÇÇ
ÇÇÇ
L1
DETAIL A
PIN 1
LOCATION
ALTERNATE TERMINAL
CONSTRUCTIONS
E
ÉÉ
ÉÉ
EXPOSED Cu
0.15 C
TOP VIEW
0.15 C
DETAIL B
0.10 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM
MINIMUM SPACING BETWEEN LEAD TIP
AND FLAG
L
L
A
B
ÉÉ
ÉÉ
ÇÇ
A3
MOLD CMPD
A1
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
DETAIL B
(A3)
ALTERNATE
CONSTRUCTIONS
A
16 X
SEATING
PLANE
0.08 C
SIDE VIEW
16X
L
A1
5
NOTE 5
8
4
16X
0.575
0.022
e
EXPOSED PAD
3.25
0.128
0.30
0.012
EXPOSED PAD
9
E2
K
12
1
16
16X
1.50
0.059
3.25
0.128
e
13
b
0.10 C A B
0.05 C
SOLDERING FOOTPRINT*
C
D2
DETAIL A
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.18
0.30
3.00 BSC
1.65
1.85
3.00 BSC
1.65
1.85
0.50 BSC
0.18 TYP
0.30
0.50
0.00
0.15
BOTTOM VIEW
0.30
0.012
0.50
0.02
NOTE 3
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
The products described herein (NB7V33M), may be covered by U.S. patents including 6,362,644. There may be other patents pending.
GigaComm is a trademark of Semiconductor Component Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
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USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
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Phone: 81−3−5773−3850
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ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NB7V33M/D