MC100EPT21 D

MC100EPT21
3.3V Differential
LVPECL/LVDS/CML to
LVTTL/LVCMOS Translator
The MC100EPT21 is a Differential LVPECL/LVDS/CML to
LVTTL/LVCMOS translator. Because LVPECL (Positive ECL),
LVDS, and positive CML input levels and LVTTL/LVCMOS output
levels are used, only +3.3 V and ground are required. The small
outline 8−lead SOIC package makes the EPT21 ideal for applications
which require the translation of a clock or data signal.
The VBB output allows this EPT21 to be cap coupled in either
single−ended or differential input mode. When single−ended cap
coupled, VBB output is tied to the D input and D is driven for a
non−inverting buffer, or VBB output is tied to the D input and D is
driven for an inverting buffer. When cap coupled differentially, VBB
output is connected through a resistor to each input pin. If used, the
VBB pin should be bypassed to VCC via a 0.01 mF capacitor. For
additional information see AND8020/D. For a single−ended direct
connection use an external voltage reference source such as a resistor
divider. Do not use VBB for a single−ended direct connection or port to
another device.
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MARKING
DIAGRAMS*
8
SO−8
D SUFFIX
CASE 751
8
1
1
KPT21
ALYW
G
8
TSSOP−8
DT SUFFIX
CASE 948R
8
1
1
KA21
ALYWG
G
Features
•
•
•
•
•
•
•
•
1.4 ns Typical Propagation Delay
Maximum Frequency > 275 MHz Typical
DFN8
MN SUFFIX
CASE 506AA
LVPECL/LVDS/CML Inputs, LVTTL/LVCMOS Outputs
1
3RMG
G
24 mA TTL outputs
A
L
Y
W
M
G
Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V
The 100 Series Contains Temperature Compensation
VBB Output
These Devices are Pb−Free and are RoHS Compliant
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
© Semiconductor Components Industries, LLC, 2012
September, 2012 − Rev. 22
1
Publication Order Number:
MC100EPT21/D
MC100EPT21
Table 1. PIN DESCRIPTION
NC
D
D
VBB
1
8
LVTTL
2
3
7
6
LVPECL
4
5
VCC
FUNCTION
PIN
Q
NC
Q
LVTTL/LVCMOS Output
D*, D*
Differential LVPECL/LVDS/CML Input
VCC
Positive Supply
VBB
Output Reference Voltage
GND
Ground
NC
No Connect
EP
(DFN8 only) Thermal exposed pad must be
connected to a sufficient thermal conduit. Electrically connect to the most negative supply
(GND) or leave unconnected, floating open.
GND
* Pin will default to 1/2 of VCC when left open.
Figure 1. Logic Diagram and 8−Lead Pinout (Top View)
Table 2. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
D
50 kW
Internal Input Pulldown Resistor
D
50 kW
D, D
50 kW
Internal Input Pullup Resistor
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 1.5 kV
> 100 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
SOIC−8
TSSOP−8
DFN8
Level 1
Level 3
Level 1
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
UL 94 V−0 @ 0.125 in
81 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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2
MC100EPT21
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Rating
Unit
3.8
V
0 to 3.8
V
± 0.5
mA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
SO−8
SO−8
190
130
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
SO−8
41 to 44
°C/W
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
TSSOP−8
TSSOP−8
185
140
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
TSSOP−8
41 to 44
°C/W
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
DFN8
DFN8
129
84
°C/W
°C/W
Tsol
Wave Solder
< 2 to 3 sec @ 248°C
<2 to 3 sec @ 260°C
265
265
°C
qJC
Thermal Resistance (Junction−to−Case)
35 to 40
°C/W
VCC
PECL Power Supply
GND = 0 V
VIN
PECL Input Voltage
GND = 0 V
IBB
VBB Sink/Source
TA
Pb
Pb−Free
Condition 2
VI VCC
(Note 2)
DFN8
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)
Table 4. PECL INPUT DC CHARACTERISTICS VCC = 3.3 V, GND = 0.0 V (Note 3)
−40°C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
VIH
Input HIGH Voltage (Single−Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
Input LOW Voltage (Single−Ended)
1355
1675
1355
1675
1355
1675
mV
VBB
Output Voltage Reference
1775
1975
1775
1975
1775
1975
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 4)
3.3
1.2
3.3
1.2
3.3
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
1875
1.2
150
−150
1875
150
−150
−150
1875
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Input parameters vary 1:1 with VCC.
4. VIHCMR min varies 1:1 with GND, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the
differential input signal.
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3
MC100EPT21
Table 5. LVTTL/LVCMOS OUTPUT DC CHARACTERISTICS VCC = 3.3 V, GND = 0.0 V, TA = −40°C to 85°C
Symbol
Characteristic
Condition
Min
Typ
Max
Unit
VOH
Output HIGH Voltage
IOH = −3.0 mA
2.4
V
VOL
Output LOW Voltage
IOL = 24 mA
0.5
V
ICCH
Power Supply Current
Outputs set to HIGH
5
17
25
mA
ICCL
Power Supply Current
Outputs set to LOW
8
21
30
mA
IOS
Output Short Circuit Current
−80
mA
−130
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
Table 6. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0.0 V (Note 5)
−40°C
Symbol
Min
Characteristic
25°C
Typ
fmax
Maximum Frequency
(Figure 2)
275
350
tPLH,
tPHL
Propagation Delay to
Output Differential
800
1200
1400
1400
tSKEW
Duty Cycle Skew (Note 6)
45
50
tSKPP
Part−to−Part Skew (Note 6)
tJITTER
Random Clock Jitter (RMS)
VPP
Input Voltage Swing
(Differential Configuration)
tr
tf
Output Rise/Fall Times
(0.8V − 2.0V)
Max
Min
Typ
275
350
2050
1800
800
1200
1400
1400
55
45
50
500
Q, Q
3.5
5
150
800
1200
250
600
900
85°C
Max
Min
Typ
Max
Unit
MHz
275
350
2250
1800
900
1100
1600
1300
2950
1900
ps
55
45
50
55
%
500
3.5
5
150
800
1200
250
600
900
500
ps
3.5
5
ps
150
800
1200
mV
250
600
900
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Measured with a 750 mV 50% duty−cycle clock source. RL = 500 W to GND and CL = 20 pF to GND. Refer to FIgure 3.
6. Skews are measured between outputs under identical transitions. Duty cycle skew is measured between differential outputs using the
deviations of the sum Tpw− and Tpw+.
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4
MC100EPT21
3000
VOH
VOUTpp (mV)
2500
2000
VOL 0.5 V
1500
1000
500
0
0
50
100
150
200
250
300
350
400
450
500
FREQUENCY (MHz)
Figure 2. Fmax
APPLICATION
TTL RECEIVER
CHARACTERISTIC TEST
*CL includes
fixture
capacitance
CL*
RL
AC TEST LOAD
GND
Figure 3. TTL Output Loading Used For Device Evaluation
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5
550
600
MC100EPT21
ORDERING INFORMATION
Package
Shipping†
MC100EPT21DG
SOIC−8
(Pb−Free)
98 Units / Rail
MC100EPT21DR2G
SOIC−8
(Pb−Free)
2500 / Tape & Reel
MC100EPT21DTG
TSSOP−8
(Pb−Free)
100 Units / Rail
MC100EPT21DTR2G
TSSOP−8
(Pb−Free)
2500 / Tape & Reel
MC100EPT21MNR4G
DFN8
(Pb−Free)
1000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
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6
MC100EPT21
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8 _
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
MC100EPT21
PACKAGE DIMENSIONS
TSSOP−8
DT SUFFIX
CASE 948R−02
ISSUE A
8x
0.15 (0.006) T U
0.10 (0.004)
S
2X
L/2
L
8
5
1
PIN 1
IDENT
0.15 (0.006) T U
K REF
M
T U
S
V
0.25 (0.010)
B
−U−
4
M
A
−V−
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
S
F
DETAIL E
C
0.10 (0.004)
−T− SEATING
PLANE
D
−W−
G
DETAIL E
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8
DIM
A
B
C
D
F
G
K
L
M
MILLIMETERS
MIN
MAX
2.90
3.10
2.90
3.10
0.80
1.10
0.05
0.15
0.40
0.70
0.65 BSC
0.25
0.40
4.90 BSC
0_
6_
INCHES
MIN
MAX
0.114
0.122
0.114
0.122
0.031
0.043
0.002
0.006
0.016
0.028
0.026 BSC
0.010
0.016
0.193 BSC
0_
6_
MC100EPT21
PACKAGE DIMENSIONS
DFN8 2x2, 0.5P
CASE 506AA
ISSUE E
D
PIN ONE
REFERENCE
2X
0.10 C
2X
A
B
L1
ÇÇÇ
ÇÇÇ
0.10 C
DETAIL A
E
OPTIONAL
CONSTRUCTIONS
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
ÉÉÉ
ÉÉÉ
EXPOSED Cu
TOP VIEW
A
DETAIL B
0.10 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.20 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L
L
MOLD CMPD
DETAIL B
OPTIONAL
CONSTRUCTION
0.08 C
(A3)
NOTE 4
SIDE VIEW
DETAIL A
A1
D2
1
4
C
8X
SEATING
PLANE
RECOMMENDED
SOLDERING FOOTPRINT*
L
8
5
e/2
e
8X
1.30
PACKAGE
OUTLINE
E2
K
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.20
0.30
2.00 BSC
1.10
1.30
2.00 BSC
0.70
0.90
0.50 BSC
0.30 REF
0.25
0.35
−−−
0.10
0.90
b
8X
0.50
2.30
1
0.10 C A B
0.05 C
8X
0.30
NOTE 3
BOTTOM VIEW
0.50
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
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any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
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MC100EPT21/D