[AKD5703-B] AKD5703-B Evaluation board Rev.0 for AK5703 GENERAL DESCRIPTION The AKD5703-B is an evaluation board for the AK5703 4ch 24bit A/D Converter with built-in PLL and MIC Amplifier. On-board USB port enables a GUI on Windows to control various settings. The AKD5703-B has the interface with AKM’s D/A evaluation boards. Therefore, it is easy to evaluate the AK5703. The AKD5703-B also has a digital audio interface, achieving an interface with digital audio systems via opt-connector. ■ Ordering Guide AKD5703-B --- Evaluation board for AK5703 (Cable for connecting with USB port and control software are included in this package. This control software does not operate on Windows NT.) FUNCTION Compatible with 2 types of interface - Direct interface with AKM’s D/A converter evaluation boards - DIT/DIR with optical input/output USB port for board control REG1 TVDD DVDD AVDD GND1 3.0V 1.8V 3.0V 0V 5V 3.0V 1.8V LINA+ REG REG LINALDO J1 Mini Jack LIN1 (T3) RIN1 PIC4550 RINA+ RINA- AK5703 J2 Mini Jack LINB+ USB PORT3 LINB- PORT4 (DSP) PORT1 Opt In LIN2 AK4118A (DIT/DIR) RIN2 RINB+ Opt Out PORT2 RINB- Figure 1. AKD5703-B Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual. <KM112900> 2013/02 -1- [AKD5703-B] 1. Evaluation Board Manual ■ Operation Sequence (1) Set up the power supply lines. (1-1) In case of supplying the power from a regulator. JP15 USB5V Name of Jack REG1 GND1 Color Default Setting Red Black Using For regulator input 5V Ground 0V Table 1. Set up of power supply lines (1-2) In case of using the power supply connectors. <Default> JP15 USB5V (2) Set up the evaluation mode, jumper pins and DIP switch. (See the followings.) (3) Power on. The AK5703 and AK4118A must be reset after the power supplies are applied. The AK5703 and AK4118A should be reset once by bringing SW1 (Toggle SW) “L” upon power-up. Click the Dummy Command button on the control software after releasing the reset by SW1= “H”. ■ Evaluation Mode In case of using the AK4118A when evaluating the AK5703, audio interface format of both devices must be matched. Refer to the datasheet for audio interface format of the AK5703, and Table 3 for audio interface format of the AK4118A. The AK4118A operates on sampling frequency of 32kHz or more. Use other mode, if the sampling frequency is slower than 32kHz. In addition, the AK4118A supports MCLK of 256fs and 512fs. use other mode, when evaluating in a condition except above. Refer to the datasheet for register setting of the AK5703. Applicable Evaluation Mode (1) Setting in PLL Master Mode. (2) Setting in PLL Slave Mode (Reference Clock = MCKI). (3) Setting in PLL Slave Mode (Reference Clock = BICK). (4) Setting in External Slave Mode. <Default> (5) Setting in External Master Mode. <KM112900> 2013/02 -2- [AKD5703-B] (1) PLL Master Mode * Connect PORT4 (DSP) with DSP. In this mode, use the PORT4(DSP). Nothing should be connected to the PORT1 (Opt-In). When an external clock is input to the MCKI pin, MCKO, BICK and LRCK clocks are generated by an internal PLL circuit. SET registers of the AK5703 to PLL Master Mode. Clock frequency should be set to the same as DSP’s specification. Refer to the datasheet of the AK5703 for register definitions of the AK5703. The figure below shows the PORT4 pin assignment. PORT4 MCLK GND BICK LRCK GND NC SDTO NC VCC SDTO, LRCK and BICK of PORT4 should be connected to SDTI, LRCK, BICK of the DSP. In case of supplying MCKO clock P should be connected to MCLK. (1-1) Set up jumper pins of MCKI clock The master clock, 11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 26MHz or 27MHz should be supplied from the MCLK pin of PORT4. JP11 MCKI DIR EXT (1-2) Set up jumper pins of BICK clock JP13 BICK DIR EXT Output frequency (32fs/64fs/128fs) of BICK should be set by “BCKO1-0 bits” of the AK5703. (1-3) Set up jumper pins of LRCK clock JP12 LRCK DIR EXT (1-4) Set up jumper pins of SDTO Select the output data from SDTO. JP14 SDTO JP14 SDTO SDTOA SDTOB In case that signal is output from SDTOA. SDTOA SDTOB In case that signal is output from SDTOB. <KM112900> 2013/02 -3- [AKD5703-B] (2) PLL Slave Mode (PLL Reference Clock: MCKI pin) * Connect PORT4 (DSP) with DSP. In this mode, use the PORT4(DSP). Nothing should be connected to the PORT1 (Opt-In). A reference clock of PLL is selected among the input clocks to the MCKI pin. MCKO clock is generated by an internal PLL circuit. BICK and LRCK are input from DSP dividing by MCKO. SET registers of the AK5703 to PLL Slave Mode (Reference Clock = MCKI). Clock frequency should be set to the same as DSP’s specification. Refer to the datasheet of the AK5703 for register definitions of the AK5703. The Figure below shows the PORT4 pin assignment. PORT4 MCLK GND BICK LRCK GND NC SDTO NC VCC JP9(MCKO) is input to DSP. SDTO, LRCK, BICK of PORT4 should be connected to SDTI, LRCK, BICK of the DSP. (2-1) Set up jumper pins of MCKI clock JP11 MCKI DIR EXT (2-2) Set up jumper pins of BICK clock JP13 BICK DIR EXT (2-3) Set up jumper pins of LRCK clock JP12 LRCK DIR EXT (2-4) Set up jumper pins of SDTO Select the output data from SDTO. JP14 SDTO JP14 SDTO SDTOA SDTOB In case that signal is output from SDTOA. SDTOA SDTOB In case that signal is output from SDTOB. <KM112900> 2013/02 -4- [AKD5703-B] (3) PLL Slave Mode (PLL Reference Clock: BICK pin) * Connect PORT4 (DSP) with DSP. In this mode, use the PORT4(DSP). A reference clock of PLL is selected among the input clocks to the BICK pin. The required clock to operate the AK5703 is generated by an internal PLL circuit. SET registers of the AK5703 to PLL Slave Mode (Reference Clock = BICK). Clock frequency should be set to the same as DSP’s specification. Refer to the datasheet of the AK5703 for register definitions of the AK5703. The figure below shows the PORT4 pin assignment. PORT4 MCLK GND BICK GND LRCK NC SDTO NC VCC SDTO, LRCK, BICK of PORT4 should be connected to SDTI, LRCK, BICK of the DSP. In case of supplying MCKO clock to the DSP, JP9 (MCKO) should be connected to MCLK. (3-1) Set up jumper pins of MCKI clock JP11 MCKI DIR EXT (3-2) Set up jumper pins of BICK clock JP13 BICK DIR EXT (3-3) Set up jumper pins of LRCK clock JP12 LRCK DIR EXT (3-4) Set up jumper pins of SDTO Select the output data from SDTO. JP14 SDTO JP14 SDTO SDTOA SDTOB In case that signal is output from SDTOA. SDTOA SDTOB In case that signal is output from SDTOB. <KM112900> 2013/02 -5- [AKD5703-B] (4) EXT Slave Mode (4-A) In case of using PORT4 * Connect PORT4 (DSP) with the DSP. MCKI, BICK and LRCK should be supplied from PORT4. SET registers of the AK5703 to EXT Slave Mode . Refer to the datasheet for register setting of the AK5703. The figure below shows the PORT4 pin assignment. PORT4 MCLK GND BICK LRCK GND NC SDTO NC VCC SDTO, LRCK, BICK of PORT4 should be connected to SDTI, LRCK, BICK of the DSP. (4-A-1) Set up jumper pins of MCKI clock JP11 MCKI DIR EXT (4-A-2) Set up jumper pins of BICK clock JP13 BICK DIR EXT (4-A-3) Set up jumper pins of LRCK clock JP12 LRCK DIR EXT (4-A-4) Set up jumper pins of SDTO Select the output data from SDTO. JP14 SDTO JP14 SDTO SDTOA SDTOB In case that signal is output from SDTOA. SDTOA SDTOB In case that signal is output from SDTOB. <KM112900> 2013/02 -6- [AKD5703-B] (4-B) In the case of using AK4118A. (Default) *This mode is BICK=64fs, LRCK=1fs only. In this mode, use the PORT1 (Opt-In). Nothing should be connected to the PORT4(DSP). The clock of AK4118A use X’tal of X1. The signal of MCKO, BICK and LRCK outputted from the AK4118A is inputted into AK5703. (4-B-1) Set up jumper pins of MCKI clock JP11 MCKI DIR EXT (4-B-2) Set up jumper pins of BICK clock JP13 BICK DIR EXT (4-B-3) Set up jumper pins of LRCK clock JP12 LRCK DIR EXT (4-B-4) Set up jumper pins of SDTO Select the output data from SDTO. JP14 SDTO JP14 SDTO SDTOA SDTOB In case that signal is output from SDTOA. SDTOA SDTOB In case that signal is output from SDTOB. (5)EXT Master Mode * Connect PORT4 (DSP) with DSP. When an external clock is input the MCKI, BICK and LRCK are generated by the clock divider of the AK5703. SET registers of the AK5703 to EXT Master Mode. Refer to the datasheet of the AK5703 for register definitions of the AK5703. The figure below shows the PORT4 pin assignment. PORT4 MCLK GND BICK LRCK GND NC SDTO NC VCC SDTO, LRCK, BICK of PORT4 should be connected to SDTI, LRCK, BICK of the DSP. <KM112900> 2013/02 -7- [AKD5703-B] (5-1) Set up jumper pins of MCKI clock JP11 MCKI DIR EXT (5-2) Set up jumper pins of BICK clock JP13 BICK DIR EXT (5-3) Set up jumper pins of LRCK clock JP12 LRCK DIR EXT (5-4) Set up jumper pins of SDTO Select the output data from SDTO. JP14 SDTO JP14 SDTO SDTOA SDTOB In case that signal is output from SDTOA. SDTOA SDTOB In case that signal is output from SDTOB. <KM112900> 2013/02 -8- [AKD5703-B] ■ DIP Switch Setting [S1]: Mode setting of the AK4118A. ON is “H”, OFF is “L”. No. 1 2 Mode DIF1 DIF0 1 2 3 4 0 0 1 1 0 1 0 1 Name DIF0 DIF1 ON (“H”) OFF (“L”) AK4118A Audio Format Setting See Table 4. Table 2. Mode Setting of the AK4118A Default H L LRCK BICK I/O I/O 24bit, Left justified 24bit, Left justified H/L O 64fs O 24bit, I2S 24bit, I2S L/H O 64fs O 24bit, Left justified 24bit, Left justified H/L I 64 -128fs I 24bit, I2S 24bit, I2S L/H I 64 -128fs I Table 3. AK4118A Audio Interface Format Setting DAUX SDTO Default ■ Jumper Pin Setting JP17 (CCLK/SCL): CCLK/SCL of the AK5703 SHORT : < Default > ■ Toggle SW Function *Upper-side is “H” and lower-side is “L”. [SW1] (RESET):Power control of the AK5703. Keep “H” during normal operation. The AK5703 must be reset after the power supplies are applied. ■ Serial Control It is possible to control the AKD5703-B via general USB port. Connect a cable with the USB connection (PORT3) on the board and PC. R26 I2C Open Short Short Mode 3-wire CAD0=0 I2C CAD0=1 R23 JP17 JP10 CAD0 CCLK/SCL CSN/CAD0 CDTIO/SDA Open Short CSN CDTIO Short Short CAD0 SDA Open Short CAD0 SDA Table 4. Serial Control Setting Default Set up jumper pins of JP10 JP10 JP10 SCIF SCIF I2C 3WIRE I2C 3WIRE In case that control is 3-wire. <KM112900> In case that control is I2C. 2013/02 -9- [AKD5703-B] ■ Analog Input/Output Circuits (1) Single-ended Input Circuit<Default> 3 J1 MIC-IN1 RIN1 2 1 LIN1 3 J2 MIC-IN2 RIN2 2 1 LIN2 VSS1 Figure 2. LIN1/RIN1, LIN2/RIN2 Input Circuits LIN1 and RIN1 are input to J1. LIN2 and RIN2 are input to J2. JP1 JP2 JP3 JP4 LIN1-single RIN1-single LIN2-single RIN2-single JP5 JP6 JP7 JP8 MP-LIN1 MP-RIN1 MP-LIN2 MP-RIN2 When the Mic Power for MPWRA is not used, JP5 and JP6 should be set to open. When the Mic Power for MPWRB is not used, JP7 and JP8 should be set to open. <KM112900> 2013/02 - 10 - [AKD5703-B] (2) Differential Input Circuit TP3 LINA+ C10 0.1u TP7 LINB+ LINA+ C8 1n LINB+ C16 1n VSS1 TP4 LINA- C18 0.1u VSS1 C11 0.1u TP8 LINB- C19 0.1u LINAC9 1n R6 open LINB- JP1 LIN1-single C17 1n R10 open VSS1 TP5 RINA+ VSS1 C14 0.1u TP9 RINB+ RINA+ C12 1n C22 0.1u RINB+ C20 1n VSS1 TP6 RINA- JP3 LIN2-single VSS1 C15 0.1u TP10 RINB- C23 0.1u RINAC13 1n R8 open RINB- JP2 RIN1-single C21 1n VSS1 R12 open JP4 RIN2-single VSS1 Figure 3. LINA+/RINA-, LINB+/RINB- Input Circuit Input LINA+/- to TP3 and TP4. Input RINA+/- to TP5 and TP6. Input LINB+/- to TP7 and TP8. Input RINB+/- to TP9 and TP10. JP1 LIN1-single JP2 JP3 JP4 RIN1-single LIN2-single RIN2-single JP7 JP8 MP-LIN2 MP-RIN2 JP7 JP8 MP-LIN2 MP-RIN2 (2-1)In the case of using Mic Power. R6, R8, R10 and R12 should be mounted 2.2k ohms. JP5 JP6 MP-LIN1 MP-RIN1 (2-2)In the case of not using Mic Power. R6, R8, R10 and R12 should be set to open. JP5 JP6 MP-LIN1 MP-RIN1 AKM assumes no responsibility for the trouble when using the above circuit examples. <KM112900> 2013/02 - 11 - [AKD5703-B] 2. Control Software Manual ■ Evaluation Board and Control Software Settings 1. Set up the evaluation board as needed, according to the previous terms. 2. Connect the evaluation board and PC with a USB cable. 3. The USB control is recognized as HID (Human Interface Device) on the PC 4. Double-click the icon “akd5703-b.exe” to open the control program.(Note 1) When the screen does not display “AKDUSBIF-B” at bottom left, reconnect the PC and the USB cable, and push the [Port Reset] button. 5. Begin evaluation by following the procedure below. Figure 4. Window of Control Soft <KM112900> 2013/02 - 12 - [AKD5703-B] ■ Operation Overview Function and Register map are controlled by this control software. These controls may be selected by the upper tabs. Frequently used Buttons, such as the register initializing button “Write Default”, are located outside of the switching tab window. Refer to the “■ Dialog Box” section for details of each dialog box setting. 1. [Port Reset]: Resets the connection to PC. Click this button when connecting USB cable after the control software set up. 2. [Write Default]: Register Initialization. When the device is reset by a hardware reset, use this button to initialize the registers. 3. [All Write]: Executes write commands for all registers displayed. 4. [All Read]: Executes read commands for all registers displayed. 5. [Save]: Saves current register settings to a file 6. [Load]: Executes data write from a saved file. 7. [All Reg Write]: “All Reg Write” dialog box pops up. 8. [Data R/W]: “Data R/W” dialog box pops up. 9. [Sequence]: “Sequence” dialog box pops up. 10. [Sequence(File)]:“Sequence(File)” dialog box pops up. 11. [Read]: Reads current register settings and displays to the register area (on the right of the main window). This is different from [All Read] button as it does not reflect to the register map. It only displays register values in hexadecimal numbers. 12. [Dummy Command]: Executes dummy command. (Note 1) Note 1. After power up the evaluation board, put SW1 to “L” to power down the AK5703, and return to “H” to release the power-down state. Then, an initialization must be executed by pressing the Dummy Command button. Since “Dummy Command” is executed in the following operations, clicking the “Dummy Command” button is not necessary when executing these operations. (1) First Read or Write Command after control soft stating. (2) First Read or Write Command after “Port Reset”. (3) “Write Default” (4) “All Write” (5) “All Read” <KM112900> 2013/02 - 13 - [AKD5703-B] ■ Tab Functions (Note 1) 1. [Function] Tab: Function Control When a button in the “Function” frame is clicked, a sequential process is executed. When other button is clicked, the setting dialog opens. Refer to the “■ Dialog Box” section for details of each dialog box setting. Figure 5. [ Function ] Window [Function] button : Executes a sequential process shown on each button. (Refer to 1- 1. [Function] Button) Setting dialog button : Opens a setting dialog. (Refer to 1- 2. Setting Dialog Button) <KM112900> 2013/02 - 14 - [AKD5703-B] 1- 1. [Function] Button Figure 6. [ Function ] Button A function button executes the sequence process shown on the each button and updates several registers. These functions are mainly for path settings. Function Name Single_End_MIC_In Input LIN1(2), RIN1(2) LINA(B)+/-, RINA(B)+/LIN1(2), RIN1(2) Output SDTOA(B) Single_End_MIC_IN and HPF/ALC Description Single-ended Input (MIC) Full-differential Input (MIC) Single-ended Input (MIC) & HPF & ALC Differential_MIC_In and HPF/ALC Full-differential Input (MIC) & HPF & ALC LINA(B)+/-, RINA(B)+/- SDTOA(B) Single_End_Line_In Single-ended Input (Line) Differential_MIC_In SDTOA(B) SDTOA(B) LIN1(2), SDTOA(B) RIN1(2) Table 5. Sequence Process Setting Path LIN1(2),RIN1(2)→MIC-AMP(+30d B)→ADC→VOL→SDTOA(B) LINA(B)+/-,RINA(B)+/-→MIC-AM P(+30dB)→ADC→SDTOA(B) LIN1(2),RIN1(2)→MIC-AMP(+18d B)→ADC→VOL/HPF/ALC→SDTO A(B) LINA(B)+/-,RINA(B)+/-→MIC-AM P(+18dB)→ADC→VOL/HPF/ALC →SDTOA(B) LIN1(2),RIN1(2)→MIC-AMP(+0dB )→ADC→VOL→SDTOA(B) * The setting of Clock mode and I/F mode are hold. The default values are as follows. Clock mode : EXT mode (slave) I/F mode : I2S Sampling Frequency : 44.1 kHz 1- 2. Setting Dialog Button Figure 7. Setting Dialog button [Power Management MIC Input] button : Opens “Power Management & MIC Input” dialog box. [System Clock Audio I/F] button : Opens “System Clock & Audio I/F” dialog box. [Data Output Delay] button : Opens “Programmable Output Data Delay” dialog box. [ALC Setting] button : Opens “ALC Setting” dialog box. [Digital Filter Setting] button : Opens “Filter Setting” dialog box. <KM112900> 2013/02 - 15 - [AKD5703-B] 2. [REG] Tab: Register Map This tab is for register read and write. Each bit on the register map is a push-button switch. Button Down indicates “1” and the bit name is shown in red (when read-only the name is shown in dark red). Button Up indicates “0” and the bit name is shown in blue (when read-only the name is shown in gray) Grayed out registers are Read-Only registers. They cannot be controlled. The registers which are not defined on the datasheet are indicated as “---”. Figure 8. [ REG] Window <KM112900> 2013/02 - 16 - [AKD5703-B] 2-1. [Write]: Data Write Dialog Select the [Write] button located on the right of the each corresponding address when changing two or more bits on the same address simultaneously. Click the [Write] button located on the right of the each corresponded address for a pop-up dialog box. When the checkbox next to the register is checked, the data will become “1”. When the checkbox is not checked, the data will become “0”. Click [OK] to write the set values to the registers, or click [Cancel] to cancel this setting. Figure 9. [ Register Set ] Window 2-2. [Read]: Data Read Click the [Read] button located on the right of the each corresponding address to execute a register read. The current register value will be displayed in the register window as well as in the upper right hand DEBUG window. Button Down indicates “1” and the bit name is shown in red (when read-only the name is shown in dark red). Button Up indicates “0” and the bit name is shown in blue (when read-only the name is shown in gray) <KM112900> 2013/02 - 17 - [AKD5703-B] ■Dialog Box 1. [Save]: [Save Address of Register] Dialog Box Click the [Save] button in the main window for save address setting dialog box. Figure 10. [ Save ] Window [All Address] check box [Start Address] edit box [End Address] edit box [OK] button [Cancel] button : When the [All Address] checkbox is checked, all register settings will be saved. : When the [All Address] check box is not checked, set starts register address to save. : When the [All Address] check box is not checked, set end register address to save. : Selects a file to save and saves register settings. : Cancel and finish this process. <KM112900> 2013/02 - 18 - [AKD5703-B] 2. [All Reg Write]: [All Register Write] Dialog Box Click the [All Reg Write] button in the main window to open register setting file window show below. Register setting files saved by the [SAVE] button may be applied. Figure 11. [ All Reg Write ] Window [Open (left)] button [Write] button [Help] button [Save] button [Open (right)] button [Close] button [All Write] [Start] button [Stop] button [Interval time] [Current No] : Selects a register setting file (*.akr). : Executes register write with selected file setting. : Opens a help window. : Saves a register setting file assignment. File name is “*.mar” : Opens a saved register setting file assignment “*. mar”. : Closes the dialog box and finish the process. : Executes all register write. Selected files are executed in descending order. : Start the register writing. : Stop the register writing. : Set interval time to start next register setting file. (5msec ~ 10,000msec) : The file number which is being processed is displayed. (File number is assigned 1-10 from top to bottom.) <KM112900> 2013/02 - 19 - [AKD5703-B] ~ Operating Suggestions ~ 1. Files saved by the [Save] button and opened by the [Open] button on the right of the dialog “*.mar” should be stored in the same folder. 2. When register settings are changed by the [Save] button in the main window, re-read the file to reflect new register settings. 3. [Data R/W]: [Data Read/Write] Dialog Box Click the [Data R/W] button in the main window for data read/write dialog box. Data is written to the specified address. Figure 12. [ Data R/W ] Window [Address] box : Input data write address in hexadecimal numbers. [Data] box : Input write data in hexadecimal numbers. [Mask] box : Input mask data in hexadecimal numbers. This value “ANDed” with the write data becomes the input data. Data is changed when corresponding mask bit is “1”. The bits which corresponding Mask bit = “0” are not changed. At this time, data read is not executed, and the storage data of this software is used. “Write Default” must be executed after power up the AK5703 or when the AK5703 is reset by the PDN pin since the storage data and register values are different. [Write] button : Writes the data generated from Data and Mask values to the address specified by “Address” box. (Note 2) [Read] button : Reads data from the address specified by “Address” box. (Note 2) The result will be shown in the Read Data Box in hexadecimal numbers. [Close] button : Closes the dialog box and finishes the process. Data write will not be executed unless [Write] is clicked. Note 2. The register map will be updated after executing [Write] or [Read] commands. <KM112900> 2013/02 - 20 - [AKD5703-B] 4. [Sequence]: [Sequence] Dialog Box Click the [Sequence] button in the main window to open register sequence setting dialog box. Register sequence can be set in this dialog box. Figure 13. [ Sequence ] Window ~ Sequence Setting ~ Set register sequence according to the following process. 1. Select a command Use [Select] pull-down box to choose commands. Corresponding boxes will be valid. < Select items > No_use Register Reg(Mask) Interval Stop End : Not using this address : Register write : Register write (Masked) : Takes an interval : Pauses the sequence : Ends the sequence <KM112900> 2013/02 - 21 - [AKD5703-B] 2. Input sequence [Address] : Data address [Data] : Write data [Mask] : Mask This value “ANDed” with the write data becomes the input data. The bits which corresponding Mask bit = “0” are not changed. At this time, data read is not executed, and the storage data of this software is used. “Write Default” must be executed after power up the AK5703 or when the AK5703 is reset by the PDN pin since the storage data and register values are different. This is the actual write data. When Mask = 0x00, current setting is hold. When Mask = 0xFF, the 8bit data which is set in the [Data] box is written. When Mask = 0x0F, lower 4bit data which is set in the [Data] box is written. Upper 4bit is hold to current setting. [Interval] : Interval time Valid boxes for each process command are shown bellow. No_use : None Register : [ Address ], [ Data ], [ Interval ] Reg(Mask) : [ Address ], [ Data ], [ Mask ], [ Interval ] Interval : [ Interval ] Stop : None End : None ~ Control Buttons ~ Functions of Control Button is shown below. [DEL] button : Checked step is deleted. [INS] button : The last deleted step is inserted to checked step. [Start Step] select : Select start step. No.1 Step : Start from No.1 step. Checked Step : Start from checked step. [Start] button : Executes the sequence. [Stop] button : Stops the sequence. [Help] button : Opens a help window. [Save] button : Saves sequence settings as a file. The file name is “*.aks”. [Open] button : Opens a sequence setting file “*.aks”. [Close] button : Closes the dialog box and finishes the process. ~ Stop of the Sequence ~ When “Stop” is selected in the sequence, the process is paused at this step and restart step number is checked. It starts again from the checked step by clicking the [Start] button. When the process at the end of sequence is finished, “Step No.1” of [start step] is selected automatically. <KM112900> 2013/02 - 22 - [AKD5703-B] 5. [Sequence(File)]: [Sequence by *.aks file] Dialog Box Click the [Sequence (File)] button to open sequence setting file dialog box shown below. Files saved in the “Sequence setting dialog” can be applied in this dialog. Figure 14. [ Sequence(File) ] Window [Open (left)] button [Start] button [Start All] button : Opens a sequence setting file (*.aks) : Executes the sequence by the setting of selected file. : Executes all sequence settings. Selected files are executed in descending order. [Stop] button : Stops the sequence process. [Help] button : Opens a help window. [Save] button : Saves a sequence setting file assignment. The file name is “*.mas”. [Open (right)] button : Opens a saved sequence setting file assignment “*. mas”. [Close] button : Closes the dialog box and finishes the process. ~ Operating Suggestions ~ 1. Those files saved by [Save] button and opened by [Open] button on the right of the dialog “*.mas” should be stored in the same folder. 2. When “Stop” is selected in the sequence, the process will be paused and a pop-up message will appear. Click “OK” to continue the process. <KM112900> 2013/02 - 23 - [AKD5703-B] Figure 15. [ Sequence Pause ] Window 6. [Power Management MIC Input]: [Power Management & MIC Input] Dialog Box Click the [Power Management MIC Input] button in the main window to open power management and MIC input setting dialog box. MIC / Line input, ADC, MIC gain and sensitivity setting are available. The settings on this dialog are interlocked with the settings on register map. (Refer to the datasheet for register definitions.) Figure 16. [ Power Management MIC Input ] Window When PMADxL/R (x = A or B) button is set to ON, PMVCM bit is set to “1”automatically. Note that PMVCM bit does not return to “0” when PMADxL/R button is set to OFF. When MIXx checkbox is checked, PMADxL/R and PMVCM bit are set to “1” automatically. Note that PMADxL/R and PMVCM bits will not return to “0” when the MIXx box is unchecked. These bits should be set on the register map. <KM112900> 2013/02 - 24 - [AKD5703-B] ~ Gain Control by Slider ~ The volume can also be changed by slider. When a value is input in the edit box, the slide bar is moved to the value that selected by the edit box. Use the mouse or arrow keys on the keyboard for small adjustments. Slide bar is moved to the selected value. The value which can be set up is chosen automatically. Figure 17. Volume Slider Control <KM112900> 2013/02 - 25 - [AKD5703-B] 7. [System Clock Audio I/F]: [System Clock & Audio I/F] Dialog Box Click the [System Clock Audio I/F] button in the main window to open system clock and Audio I/F setting dialog. The settings on this dialog are interlocked with the settings on register map. (Refer to the datasheet for register definitions.) Figure 18. [ System Clock Audio I/F ] Window <KM112900> 2013/02 - 26 - [AKD5703-B] 8. [Data Output Delay]: [Programmable Output Delay] Dialog Box Click the [Data Output Delay] button in the main window for setting output data delay. The delay amount of output data is controlled in this dialog. The settings on this dialog are interlocked with the settings on register map. (Refer to the datasheet for register definitions.) Figure 19. [Data Output Delay] Window <KM112900> 2013/02 - 27 - [AKD5703-B] 9. [ALC Setting]: [ALC Setting] Dialog Box Click the [ALC Setting] button in the main window for ALC setting. ALC parameters are controlled in this dialog. The settings on this dialog are interlocked with the settings on register map. (Refer to the datasheet for register definitions.) Figure 20. [ALC Setting] Window <KM112900> 2013/02 - 28 - [AKD5703-B] 10. [Digital Filter]: [Filter Setting] Dialog Box Click the [Digital Filter] button in the main window for Digital Filter setting. Coefficient and frequency of digital filter are calculated on this dialog. (Refer to the datasheet for register definitions.) Figure 21. [Digital Filter] Window [Register Setting] button [F Response] button [Coefficient Write] button [Reg Map to Fc/Plot] check box [Close] button : Opens the register setting dialog. Register writes of a filter factor are also executed. : Opens the frequency response plot dialog [Filter Plot]. Register writes of a filter factor are also executed. : Calculation of all the filters and coefficient writing are performed. : When [Reg Map to Fc/Plot] is checked, the coefficient currently written in the register map is reflected to each parameter. Gain of HPF and LPF needs to be set to 1.0. When carrying out coefficient writing by [Coefficient Write] etc. on this dialog, Gain of HPF and LPF is always 1.0. : Closes the dialog box and finishes the process. <KM112900> 2013/02 - 29 - [AKD5703-B] 10-1. Parameter Setting Setting the parameter of each filter Parameter Function Sampling Rate Sampling Frequency(fs) HPF HPF1 Cut Off Frequency HPF2 Cut Off Frequency LPF Cut Off Frequency High Pass Filter 1 Cut Off Frequency High Pass Filter 2 Cut Off Frequency Setting Range 8, 11.025, 12, 16, 22.05, 24, 32, 44.1, or 48kHz 3.4×fs/44.1 ~219.3×fs/44.1 (kHz) fc/fs 0.0001 Low Pass Filter Cut Off Frequency Table 6. Parameter Setting of [Filter Setting] fc/fs 0.05 Set up ON/OFF of a filter with the check button in [Filter ON/OFF Control]." The filter is ON when the check box is checked. Figure 22. Filter ON/OFF Check Box <KM112900> 2013/02 - 30 - [AKD5703-B] 10-2. [Register Setting]: [Register Setting for Filter] Dialog Box Click the [Register Setting] button in the filter setting window to open the register setting dialog box shown below. An error message is displayed when a value which is out of a setting range is written, and a calculation of register setting is carried out. Figure 23. [ Register Setting for Filter ] Window In the following cases, a register set value is updated. 1. When the [Register Setting] button is clicked. 2. When the [F Response] button is clicked. 3. When the [Coefficient Write] button is clicked. 4. When the [UpDate] button on a frequency characteristic display window is clicked. 5. When the Enter key or the Tab key is pressed after setting each parameter. <KM112900> 2013/02 - 31 - [AKD5703-B] 10-3. [F Response]: [Filter Plot] Dialog Box Click the [F Response] button in the filter setting window to open the filter post dialog box show below. Filter frequency response of the AK5703 is displayed according to current value of the filter. Figure 24. [ F Response ] Window [Frequency Range] edit box [Update] button [Gain/Phase] select [Log View] check button [Close] button : The width of the frequency display is specified. : Redraws the filter characteristics. : “Gain/Phase” display switch. : “Linear/Log” display switch. : Closes the dialog box and ends the process. ~ Adjustment of a vertical range ~ 1. [Y-axis Ref] edit box 2. [Vertical slide] 3. [Horizontal slide] : Sets the center value of Y-axis. : Moves center reference of the Y-axis. : Adjusts scale of the Y-axis. (left: shrink, right: expand) <KM112900> 2013/02 - 32 - [AKD5703-B] MEASUREMENT RESULTS [Measurement Conditions] ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Measurement unit MCKI BICK fs Bit Measurement Mode Power Supply Input Frequency Measurement Frequency Temperature : Audio Precision, System two Cascade : 256fs (11.2896MHz) : 64fs : 44.1kHz : 24bit : EXT Slave Mode : AVDD=TVDD= 3.0V, DVDD=1.8V : 1kHz : 20 ~ 20kHz : Room [Measurement Results] Result Lch Rch ADC: LIN1/RIN1 → ADCA → IVOL, IVOL=0dB, ALC=OFF → SDTOA MGAIN = +30dB S/(N+D) fs=44.1kHz, BW=20kHz 80.6 80.4 (-1dBFS) DR (-60dBFS, A-Weighted) 84.4 84.4 S/N (A-weighted) 84.4 84.4 MGAIN = 0dB S/(N+D) fs=44.1kHz, BW=20kHz 86.5 86.7 (-1dBFS) DR (-60dBFS, A-Weighted) 96.3 96.1 S/N (A-weighted) 96.3 96.2 <KM112900> Unit dB dB dB dB dB dB 2013/02 - 33 - [AKD5703-B] 1. ADC (LIN1/RIN1 ADCA) (+30dB) AK5703 FFT (LIN1/RIN1=>ADCA) [-1dBFS] +0 -20 -40 d B F S -60 -80 -100 -120 -140 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz Figure 25. FFT (Input level= -1dBFS) AK5703 FFT (LIN1/RIN1=>ADCA) [-60dBFS] +0 -20 -40 d B F S -60 -80 -100 -120 -140 20 50 100 200 500 1k 2k Hz Figure 26. FFT (Input level= -60dBFS) <KM112900> 2013/02 - 34 - [AKD5703-B] AK5703 FFT (LIN1/RIN1=>ADCA) [No Input] +0 -20 -40 d B F S -60 -80 -100 -120 -140 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 27. FFT (No Signal) AK5703 THD+N vs. Input Level (LIN1/RIN1=>ADCA) [fin=1kHz] -50 -55 -60 d B F S -65 -70 -75 -80 -85 -90 -120 -100 -80 -60 -40 -20 +0 dBr Figure 28. THD+N vs. Input Level <KM112900> 2013/02 - 35 - [AKD5703-B] AK5703 THD+N vs. Input Frequency (LIN1/RIN1=>ADCA) [-1dBFS] -50 -55 -60 -65 d B F S -70 -75 -80 -85 -90 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 29. THD+N vs. Input Frequency (C10 and C14: Ceramic Capacitor) In this case, a ceramic capacitor is used on the LIN1 and RIN1 pins of the AKD5703-B. The performance of the ceramic capacitor is not so good on a low frequency signal. Refer to Figure 30 about the performance of the AK5703. AK5703 THD+N vs. Input Frequency (LIN1/RIN1=>ADCA) [-1dBFS] -50 -55 -60 d B F S -65 -70 -75 -80 -85 -90 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 30. THD+N vs. Input Frequency(C10 and C14 : Electrolytic Capacitor) <KM112900> 2013/02 - 36 - [AKD5703-B] AK5703 Linearity (LIN1/RIN1=>ADCA) [fin=1kHz] +0 T -20 -40 d B F S -60 -80 -100 -120 -120 -100 -80 -60 -40 -20 +0 dBr Figure 31. Linearity AK5703 Frequency Response (LIN1/RIN1=>ADCA) [-1dBFS] +0 -0.5 -1 d B F S -1.5 -2 -2.5 -3 5k 10k 15k 20k Hz Figure 32. Frequency Response <KM112900> 2013/02 - 37 - [AKD5703-B] AK5703 Crosstalk (LIN1/RIN1=>ADCA) [-1dBFS] -50 TTTTTTTTTTT TT TT TTTTTTT TT TTTTTTTTTTTTTTTTTTTT TTT T T -60 -70 -80 d B -90 -100 -110 -120 -130 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz Figure 33. Crosstalk 2.ADC (LIN1/RIN1 ADCA) (+0dB) AK5703 FFT (LIN1/RIN1=>ADCA) [-1dBFS] +0 -20 -40 d B F S -60 -80 -100 -120 -140 20 50 100 200 500 1k 2k Hz Figure 34. FFT (Input level= -1dBFS) <KM112900> 2013/02 - 38 - [AKD5703-B] AK5703 FFT (LIN1/RIN1=>ADCA) [-60dBFS] +0 -20 -40 d B F S -60 -80 -100 -120 -140 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz Figure 35. FFT (Input level= -60dBFS) AK5703 FFT (LIN1/RIN1=>ADCA) [No Input] +0 -20 -40 d B F S -60 -80 -100 -120 -140 20 50 100 200 500 1k 2k Hz Figure 36. FFT (No Signal) <KM112900> 2013/02 - 39 - [AKD5703-B] AK5703 THD+N vs. Input Level (LIN1/RIN1=>ADCA) [fin=1kHz] -60 -65 -70 -75 d B F S -80 -85 -90 -95 -100 -120 -100 -80 -60 -40 -20 +0 dBr Figure 37. THD+N vs. Input Level AK5703 THD+N vs. Input Frequency (LIN1/RIN1=>ADCA) [-1dBFS] -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 38. THD+N vs. Input Frequency (C10 and C14: Ceramic Capacitor) In this case, a ceramic capacitor is used on the LIN1 and RIN1 pins of the AKD5703-B. The performance of a ceramic capacitor is not so good on a low frequency signal. Refer to Figure 39 about the performance of the AK5703. <KM112900> 2013/02 - 40 - [AKD5703-B] AK5703 THD+N vs. Input Frequency (LIN1/RIN1=>ADCA) [-1dBFS] -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 39. THD+N vs. Input Frequency(C10 and C14 : Electrolytic Capacitor) AK5703 Linearity (LIN1/RIN1=>ADCA) [fin=1kHz] +0 T -20 -40 d B F S -60 -80 -100 -120 -120 -100 -80 -60 -40 -20 +0 dBr Figure 40. Linearity <KM112900> 2013/02 - 41 - [AKD5703-B] AK5703 Frequency Response (LIN1/RIN1=>ADCA) [-1dBFS] +0 -0.5 -1 d B F S -1.5 -2 -2.5 -3 5k 10k 15k 20k Hz Figure 41. Frequency Response AK5703 Crosstalk (LIN1/RIN1=>ADCA) [-1dBFS] -70 -80 -90 -100 d B -110 -120 -130 -140 -150 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 42. Crosstalk <KM112900> 2013/02 - 42 - [AKD5703-B] Revision History Date 13/02/12 Manual Revision KM112900 Board Revision 0 Reason Contents First Edition IMPORTANT NOTICE These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the products. Descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. You are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. AKM products are neither intended nor authorized for use as critical components Note1) in any safety, life support, or other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKM. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. <KM112900> 2013/02 - 43 - 5 4 3 2 1 USBGND USB5V T1 TA48018BF REG1 IN +5V TP1 1.8V OUT GND R1 0 DVDD C3+ 0.1u C2 0.1u R4 open C4 47u R3 5.1 D T2 TA48M03F IN + GND1 C1 47u L1 10u TP2 3.0V OUT GND C6+ 0.1u C5 0.1u GND D TVDD VSS2 D3V R2 0 TP12 VSS1 C7 47u VSS1 JP1 LIN1-single C9 1n VSS1 C30 10u C11 0.1u C8 1n C29 0.1u VSS1 C20 1n CCLK/SCL 15 16 CSN/SDA 17 I2C 18 19 VSS1 20 SDTOA LIN2/LINB+ LINB- SDTOB MCKO VSS1 C24 1u C21 1n I2C CDTIO 3WIRE JP10 SCIF C JP17 CCLK/SCL C23 0.1u JP4 RIN2-single C25 C27 0.1u 0.1u + VSS1 VSS1 MCKI LRCK R16 51 11 BICK R15 51 10 SDTOA 9 SDTOB 8 JP9 MCKO VSS2 R13 51 PDN C26 10u C28 10u TP11 VSS2 TVDD VSS2 A B R14 51 + C22 0.1u R12 open R19 51 TP15 CCLK/SCL R17 51 12 TVDD 28 BICK MPWRB 1 JP8 MP-RIN2 R11 2.2k TP14 CDTIO/CAD0 R18 51 13 7 C19 0.1u JP3 LIN2-single C17 1n VSS1 TP9 RINB+ TP10 RINB- 27 AK5703EN MRF VSS2 VSS1 26 C18 0.1u R10 open R20 51 CSN VSS2 LRCK U1 6 VSS1 25 MPWRA DVDD 24 C31 1u 5 C16 1n TP13 CSN/SDA 14 MCKI PDN VSS1 RIN1/RINA+ 4 VSS1 TP7 LINB+ TP8 LINB- R9 2.2k R21 51 R23 open CDTIO/CAD0 VCOM C14 0.1u JP7 MP-LIN2 2 1 23 3 C12 1n R7 2.2k 3 J2 MIC-IN2 VSS2 C15 0.1u JP6 MP-RIN1 B RINA- LINA- 21 22 RINB- 2 1 VSS1 2 3 J1 MIC-IN1 C13 1n LIN1/LINA+ JP2 RIN1-single TP6 RINATP5 RINA+ R22 4.7k CCLK JP5 MP-LIN1 R8 open R24 4.7k R27 4.7k AVDD R5 2.2k C10 0.1u RIN2/RINB+ C R6 open R25 4.7k + TP4 LINATP3 LINA+ TVDD R26 open VSS2 A DVDD Title AKD5703-B Size - 44 5 4 3 A3 Date: 2 Document Number Rev 0 AK5703 Thursday, November 29, 2012Sheet 1 1 of 3 5 4 3 2 1 PORT2 DIR 1 D3V C33 0.1u JP11 MCKI MCKI VCC IN EXT C37 10u 26 DIR JP13 BICK 27 EXT 28 C38 5p C40 0.1u 13 14 NC/GP1 15 TX0/GP2 16 TX1/GP3 TVDD 11 10 9 DIF1/RX6 CM1/CDTI/SDA TEST2 OCKS1/CCLK/SCL DIF0/RX5 OCKS0/CSN/CAD0 NC 4 3 7 S1 6 H (ON) SW DIP-2 L(OFF) 1 2 5 4 3 R32 47k 2 R33 47k B RX3 1 48 VSS4 47 RX2 46 TEST1 45 44 VSS3 41 RX1 IPS0/RX4 VCOM INT0 8 C43 0.47u C41 0.1u + 2 SW1 RESET 17 CM0/CDTO/CAD1 37 A VSS1 R31 10k 1 3 H DIF2/RX7 PDN INT1 K 36 IPS1/IIC U2 AK4118A XTI 40 35 L 12 DIF0 DIF1 XTO R 34 R30 10k BOUT/GP4 P/SN 39 33 D1 HSU119 18 DAUX AVDD 32 B 19 XTL0 38 1 31 PDN COUT/GP5 DVDD MCKO2 NC 29 30 X1 11.2896MHz USB-PDN UOUT/GP6 20 21 22 VSS2 XTL1 C39 5p R29 2.2k VIN/GP0 C 2 JP14 SDTO C C34 0.1u BICK 43 SDTOB SDTO RX0 SDTOA SDTOB C36 0.1u 42 SDTOA MCKO1 25 DSP BICK 23 PORT4 2 GND 4 GND 6 8 10 24 1 3 5 7 9 LRCK EXT MCLK BICK LRCK SDTO + LRCK + DIR JP12 LRCK D OPT-OUT C35 10u VOUT/GP7 D GND 2 3 C42 10u R28 470 C32 0.1u PORT1 1 2 3 OUT GND VCC OPT-IN A A Title AKD5703-B - 45 - Size A3 Date: 5 4 3 2 Document Number Rev 0 DIR/DIT Thursday, November 22, 2012Sheet 1 2 of 3 5 4 3 2 1 GND ID D+ DVBUS PORT3 USB Connector 5 4 3 2 1 T3 TA48M03F JP15 USB5V USB5V D IN C45 0.1u OUT GND C46 10u D + C44 1u USBGND RC7/RX/DT/SDO C 2 RD4/SPP4 3 4 5 7 34 NC/ICPORTS 35 RD6/SPP6/P1C OSC1/CLKI VSS1 U3 PIC18F4550 VDD1 VDD0 RE1/AN6/CK2SPP RB1/AN10/INT1/SCK/SCL RE0/AN5/CK1SPP C53 22p 31 XTO 30 XTI X2 20MHz C52 22p 29 C50 0.1u 28 C51 10u 27 26 B 25 24 RA3/AN3/Vref+ 23 22 RA1/AN1 20 19 RA4/T0CKI/C1OUT/RCV 32 R35 100k C49 0.1u VDD 1 MCLR 2 PGD 3 PGC 4 GND 5 JP16 PIC A RA0/AN0 MCLR_N/Vpp/RE3 18 RB7/KBI3/PGD 17 RB6/KBI2/PGC RB5/KBI1/PGM R34 4.7k 16 14 12 NC/ICCK/ICPGC RB3/AN9/CPP2/VPO 15 11 RA5/AN4/SS_N/HLVDIN/C2OUT RB4/AN11/KBI0/CSSPP RB2/AN8/INT2/VMO RA2/AN2/Vref-/CVref 10 RB0/AN12/INT0/FLT0/SDI/SDA 21 9 RE2/AN7/OESPP NC/ICDT/ICPGD + 8 B OSC2/CLKO/RA6 VSS0 33 C RC0/T1OSO/T13CKI RD5/SPP5/P1B 13 C47 0.1u NC/ICRST_N/ICVpp RD7/SPP7/P1D 6 C48 10u RC1/T1OSI/CCP2/UOE_N 36 RC2/CCP1/P1A VUSB 37 38 RD0/SPP0 39 RD1/SPP1 40 RD2/SPP2 41 RD3/SPP3 42 RC4/D-/VM RC5/D+/VP 43 44 RC6/TX/CK 1 C54 0.47u R36 0 + R37 0 A CCLK CDTIO Title AKD5703-B CSN USB-PDN Size - 46 5 4 3 A3 Date: 2 Document Number Rev 0 Control I/F (USB) Tuesday, November 20, 2012 Sheet 1 3 of 3 AK5703-B Silk Layer1 - 47 - AK5703-B Silk Layer2 - 48 - AK5703-B Pattern Layer1 - 49 - AK5703-B Pattern Layer2 - 50 -