Datasheet

DATASHEET
5A Automotive Synchronous Buck Regulator
ISL78235
Features
The ISL78235 is a highly efficient, monolithic, synchronous
step-down DC/DC converter that can deliver 5A of continuous
output current from a 2.7V to 5.5V input supply. The device uses
peak current mode control architecture to achieve very low duty
cycle operation at high frequency with fast transient response and
excellent loop stability.
• 2.7V to 5.5V input voltage range
The ISL78235 integrates a low ON-resistance P-channel
(35mΩ, typical) high-side FET and N-channel (11mΩ, typical)
low-side FET to maximize efficiency and minimize external
component count. The 100% duty cycle operation allows less
than 250mV dropout voltage at 5A output current. The
operating frequency of the Pulse Width Modulator (PWM) is
adjustable from 500kHz to 4MHz. The default switching
frequency of 2MHz is set by connecting the FS pin high.
• External synchronization from 1MHz to 4MHz
The ISL78235 can be configured for discontinuous (PFM) or
forced continuous (PWM) operation at light load. Forced
continuous operation reduces noise and RF interference, while
discontinuous mode provides higher efficiency by reducing
switching losses at light loads.
• 1% reference accuracy over-temperature
Fault protection is provided by internal hiccup mode current
limiting during short-circuit and overcurrent conditions. The
device also integrates output overvoltage and
over-temperature protections. A power-good monitor indicates
when the output is in regulation. The ISL78235 offers a 1ms
Power-Good (PG) timer at power-up.
When in shutdown, the ISL78235 discharges the output
capacitor through an internal 100Ω soft-stop switch. Other
features include internal fixed or adjustable soft-start and
internal/external compensation.
The ISL78235 is available in a 3mmx3mm 16 Ld Thin Quad Flat
No-lead (TQFN) Pb-free package and in a 5mmx5mm 16 Ld
Wettable Flank Quad Flat No-Lead (WFQFN) package with an
exposed pad for improved thermal performance. The
ISL78235 is rated to operate across the temperature range of
-40°C to +105°C in the 3mmx3mm package and -40°C to
+125°C in the 5mmx5mm package.
VIN
15
PHASE
14
11
*ISL78235
10
SYNC 4
9
8
COMP
7
SS
6
FS
EN
5
• Optional PFM mode for light-load efficiency improvement
• Very low ON-resistance HS/LS switches: 35mΩ/11mΩ
• Internal 1ms or adjustable external soft-start
• Soft-stop output discharge during disable
• OTP, OCP, output OVP, input UVLO protections
• Up to 95% efficiency
• AEC-Q100 qualified
• Common pinout family allows migration from 3A to 5A
without PCB change:
- ISL78233 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3A
- ISL78234 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4A
- ISL78235 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5A
Applications
• DC/DC POL modules
• μC/µP, FPGA and DSP power
• Video processor/SOC power
• Automotive infotainment power
Related Literature
• UG015, “ISL7823xEVAL1Z Evaluation Board User Guide”
• ISL78233, ISL78234 Datasheet
• UG062, “ISL7823xEVAL2Z Evaluation Board User Guide”
100
5A LOAD
DSP, FPGA
90
13
12
PG 3
• Adjustable switching frequency from 500kHz to 4MHz
COUT
1
VDD 2
VOUT
• 100ns guaranteed phase minimum on time for wide output
regulation
EFFICIENCY (%)
16
PHASE
VIN
CIN
PHASE
L
2.7V TO 5.5V
• 2MHz default switching frequency
PGND
PGND
SGND
2.5VOUT
80
3.3VOUT
1.8VOUT 1.5VOUT
70
1.2VOUT
60
FB
50
*Pin Compatible
ISL78233 - 3A BUCK
ISL78234 - 4A BUCK
40
TA = +25°C
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
OUTPUT LOAD (A)
FIGURE 1. TYPICAL APPLICATION: 5A BUCK REGULATOR
April 1, 2016
FN8713.5
1
FIGURE 2. EFFICIENCY vs LOAD (VIN = 5V; fsw = 2MHz; SYNC = GND)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2015, 2016. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL78235
Table of Contents
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Typical Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Operating Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SKIP Mode (PFM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frequency Adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Negative Current Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Soft Start-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Discharge Mode (Soft-Stop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100% Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
16
16
17
17
17
17
17
17
18
18
18
18
18
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Inductor and Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loop Compensation Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
18
18
19
19
PCB Layout Recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
L16.3x3D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
L16.5x5D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Submit Document Feedback
2
FN8713.5
April 1, 2016
ISL78235
Functional Block Diagram
COMP
SS
SHUTDOWN
SYNC
55pF
SOFTSoft
START
SHUTDOWN
VDD
100kΩ
+
BANDGAP VREF
+
EN
FS
+
COMP
-
EAMP
-
VIN
OSCILLATOR
PWM/PFM
LOGIC
CONTROLLER
PROTECTION
HS DRIVER
3pF
+
P
PHASE
LS
DRIVER
N
PGND
FB
6kΩ
SLOPE
Slope
COMP
0.8V
+
CSA
-
+
OV
0.85*VREF
PG
+
UV
+
OCP
-
+
SKIP
-
ISET
THRESHOLD
1ms
DELAY
NEG CURRENT
SENSING
SGND
ZERO-CROSS
SENSING
0.5V
SCP
+
100Ω
SHUTDOWN
FIGURE 3. FUNCTIONAL BLOCK DIAGRAM
Submit Document Feedback
3
FN8713.5
April 1, 2016
ISL78235
Pin Configuration
16
15
14
PHASE
PHASE
PHASE
VIN
ISL78235
(16 LD TQFN, WFQFN)
TOP VIEW
13
12 PGND
VIN 1
11 PGND
VDD 2
EPAD
10 SGND
PG 3
9
5
6
7
8
EN
FS
SS
COMP
SYNC 4
FB
Pin Descriptions
PIN NUMBER
PIN NAME
DESCRIPTION
1, 16
VIN
Input supply voltage. Place a minimum of two 22µF low ESR ceramic capacitors from VIN to PGND as close
as possible to the IC for decoupling.
2
VDD
Input supply voltage for the logic circuitry. A 0.1µF high frequency decoupling ceramic capacitor should also
be placed close to the VDD and SGND pin. Connect to VIN pin.
3
PG
PG is an open-drain output for power-good indication. Use a 10kΩ to 100kΩ pull-up resistor connected from
PG to VIN. At power-up or EN high, PG rising edge is delayed by 1ms upon output voltage within regulation.
4
SYNC
Mode selection pin. Connect to logic high or input voltage VIN for forced PWM mode. Connect to logic low or
ground for PFM mode. Connect to an external function generator for synchronization with a positive edge
trigger. In external synchronization the ISL78235 operates in forced PWM mode. The transition to and from
internal oscillator to external synchronization is seamless and does not require disabling of the ISL78235.
There is an internal 1MΩ pull-down resistor to SGND to prevent an undefined logic state if SYNC pin is
floating.
5
EN
Regulator enable pin. Regulator is enabled when driven logic high. Regulator is shutdown and PHASE pin
discharge output capacitor when enable pin is driven low.
6
FS
This pin sets the internal oscillator switching frequency using a resistor, RFS, from the FS pin to GND. The
frequency of operation may be programmed between 500kHz to 4MHz. The switching frequency is 2MHz if
FS is connected to VIN.
7
SS
SS is used to adjust the soft-start time. Connect SS pin to SGND for internal 1ms soft-start time. Connect a
capacitor from SS to SGND to adjust the soft-start time. Do not use more than 33nF on the SS pin.
8
COMP
COMP is the output of the error amplifier if COMP is not connected to VDD. An external compensation
network must be used if COMP is not tied to VDD. If COMP is tied to VDD, the error amplifier output is
internally compensated. External compensation network across COMP and SGND may be required to
improve the loop compensation of the amplifier.
9
FB
10
SGND
Signal ground, Connect to PGND.
The feedback network of the regulator, FB, is the negative input to the transconductance error amplifier. The
output voltage is set by an external resistor divider connected to FB. With a properly selected divider, the
output voltage can be set to any voltage between the power rail (reduced by converter losses) and the 0.6V
reference. In addition, the regulator power-good and undervoltage protection circuitry use FB to monitor the
regulator output voltage.
11, 12
PGND
Power ground
13, 14, 15
PHASE
Switching node connections. Connect to one terminal of the inductor. This pin is discharged by a 100Ω
resistor when the device is disabled. See “Functional Block Diagram” on page 3 for more detail.
Exposed Pad
EPAD
The exposed pad must be connected to the SGND pin for proper electrical performance. Place as many vias
as possible under the pad connecting to SGND plane for optimal thermal performance.
Submit Document Feedback
4
FN8713.5
April 1, 2016
ISL78235
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
OUTPUT VOLTAGE
(V)
TEMP. RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
ISL78235ARZ
8235
Adjustable
-40°C to +105°C 16 Ld 3x3mm TQFN
L16.3x3D
ISL78235AARZ
78235A ARZ
Adjustable
-40°C to +125°C 16 Ld 5x5mm WFQFN
L16.5x5D
ISL78235EVAL1Z
3x3mm TQFN Evaluation Board
ISL78235EVAL2Z
5x5mm WFQFN Evaluation Board
NOTES:
1. Add “-T” suffix for 6k unit or “-T7A” suffix for 250 unit tape and reel options. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials and 100% matte tin
plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL78235. For more information on MSL, please see tech brief TB363.
TABLE 1. KEY DIFFERENCE BETWEEN FAMILY OF PARTS
PART NUMBER
IOUT MAX
(A)
ISL78233
3
ISL78234
4
ISL78235
5
Submit Document Feedback
5
FN8713.5
April 1, 2016
ISL78235
Typical Application Diagram
L1
0.68μH
POWER GOOD
INDICATOR
2
3
EXTERNAL
SYNCHRONIZATION
INPUT
VOUT
PHASE
C2
2x22μF
CERAMIC
PGND
ISL78235
VDD
PGND
PG
SGND
R2
200k
C3*
FB
SYNC
FS
EN
4
+1.8V/5A
COMP
R1
100k
VIN
SS
1
PHASE
VIN
C1
2x22μF
CERAMIC
PHASE
2.7V TO 5.5V
VIN
R3
100k
ENABLE INPUT
RFS
RCOMP
CSS
CCOMP
*C3 IS OPTIONAL. IT IS
RECOMMENDED TO PUT A
PLACEHOLDER FOR IT AND CHECK
LOOP ANALYSIS BEFORE USE.
FIGURE 4. TYPICAL APPLICATION DIAGRAM
TABLE 2. COMPONENT SELECTION TABLE WITH INTERNAL COMPENSATION
VOUT
1.2V
1.5V
1.8V
2.5V
3.3V
C1
2 x 22µF
2 x 22µF
2 x 22µF
2x22µF
2 x 22µF
C2 (Note 4)
3 x 22µF
3 x 22µF
2 x 22µF
2 x 22µF
2 x 22µF
C3
22pF
10pF
10pF
10pF
10pF
L1
0.33µH-0.68µH
0.33µH-0.68µH
0.33µH-0.68µH
0.47µH-0.78µH
0.47µH-0.78µH
R2
100kΩ
150kΩ
200kΩ
316kΩ
450kΩ
R3
100kΩ
100kΩ
100kΩ
100kΩ
100kΩ
NOTE:
4. C2 values are minimum recommended values for ceramic capacitors. Higher capacitance may be needed based on system requirements.
Submit Document Feedback
6
FN8713.5
April 1, 2016
ISL78235
Absolute Maximum Ratings (Reference to GND)
Thermal Information
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.8V (DC) or 7V (20ms)
EN, FS, PG, SYNC, VFB . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN + 0.3V
PHASE . . . . . . . . . . . . -1.5V (100ns)/-0.3V (DC) to 6.5V (DC) or 7V (20ms)
COMP, SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V
ESD Rating
Human Body Model (Tested per AEC-Q100-002) . . . . . . . . . . . . . . . . 5kV
Machine Model (Tested per AEC-Q100-003) . . . . . . . . . . . . . . . . . . 300V
Charge Device Model (Tested per AEC-Q100-011) . . . . . . . . . . . . . . . 2kV
Latch-Up (Tested per AEC-Q100-004, Class II, Level A) . . . . . . . . . . 100mA
Thermal Resistance
JA (°C/W) JC (°C/W)
16 Ld TQFN Package (Notes 5, 6) . . . . . . .
43
3.5
16 Ld WFQFN Package (Notes 5, 6) . . . . .
33
3.5
Operating Junction Temperature Range . . . . . . . . . . . . . .-55°C to +125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
VIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 5A
Ambient Temperature Range
3x3mm TQFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C
5x5mm WFQFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
6. JC, “case temperature” location is at the center of the exposed metal pad on the package underside.
Electrical Specifications
Specification limits are established at the following conditions: TA = -40°C to +105°C or TA = -40°C to +125°C
depending on package, VIN = 3.6V, EN = VIN, unless otherwise noted. Typical values are at TA = +25°C. Boldface limits apply across the operating
temperature range specified in the Recommended Operating Conditions table for the specified package.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 7)
TYP
MAX
(Note 7)
2.5
2.7
2.20
2.45
UNIT
INPUT SUPPLY
VIN Undervoltage Lockout Threshold
VUVLO
Rising, no load
Falling, no load
Quiescent Supply Current
IVIN
Shutdown Supply Current
ISD
V
V
SYNC = GND, no load at the output
47
SYNC = GND, no load at the output and no
switches switching
47
60
µA
µA
SYNC = VIN, fSW = 2MHz, no load at the output
19
25
mA
SYNC = GND, VIN = 5.5V, EN = low
4
10
µA
0.600
0.606
V
OUTPUT REGULATION
Reference Voltage
VREF
VFB Bias Current
IVFB
0.594
VFB = 0.75V
0.1
µA
Line Regulation
VIN = VO + 0.5V to 5.5V (minimal 2.7V)
0.2
%/V
Soft-Start Ramp Time Cycle
SS = SGND
1
ms
Soft-Start Charging Current
ISS
VSS = 0.1V
1.7
2.1
2.5
µA
OVERCURRENT PROTECTION
Current Limit Blanking Time
tOCON
17
Clock
pulses
Overcurrent and Auto Restart Period
tOCOFF
8
SS cycle
Positive Peak Current Limit
IPLIMIT
TA = +25°C
6.2
TA = -40°C to +105°C
6.1
7.8
5x5 mm WFQFN package
TA = +105°C to +125°C
Peak Skip Limit
ISKIP
TA = +25°C
0.85
TA = -40°C to +105°C
0.83
5x5 mm WFQFN package
TA = +105°C to +125°C
Submit Document Feedback
7
1.10
9.4
A
11.0
A
12.5
A
1.40
A
1.60
A
1.65
A
FN8713.5
April 1, 2016
ISL78235
Electrical Specifications
Specification limits are established at the following conditions: TA = -40°C to +105°C or TA = -40°C to +125°C
depending on package, VIN = 3.6V, EN = VIN, unless otherwise noted. Typical values are at TA = +25°C. Boldface limits apply across the operating
temperature range specified in the Recommended Operating Conditions table for the specified package. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
Zero Cross Threshold
MIN
(Note 7)
TYP
-275
Negative Current Limit
INLIMIT
TA = +25°C
-5.1
-2.8
-6.0
MAX
(Note 7)
UNIT
375
mA
-1.3
A
-0.6
A
COMPENSATION
Error Amplifier Transconductance
Transresistance
RT
COMP = VDD, internal compensation
125
µA/V
External compensation
130
µA/V
TA = -40°C to +105°C
0.11
5x5 mm WFQFN package
TA = +105°C to +125°C
0.1
0.17
0.22
Ω
Ω
MOSFET
P-Channel ON-Resistance
N-Channel ON-Resistance
VIN = 5V, IO = 200mA
26
35
50
mΩ
VIN = 2.7V, IO = 200mA
38
52
78
mΩ
VIN = 5V, IO = 200mA
5
11
20
mΩ
VIN = 2.7V, IO = 200mA
8
15
31
mΩ
100
ns
PHASE
PHASE Maximum Duty Cycle
100
PHASE Minimum On-Time
SYNC = High
%
OSCILLATOR
Nominal Switching Frequency
fSW
FS = VIN
1730
FS with RS = 402kΩ
2000
2350
420
FS with RS = 42.2kΩ
kHz
kHz
4200
kHz
SYNC Logic LOW to HIGH Threshold
0.67
0.75
0.84
V
SYNC Logic Hysteresis
0.10
0.17
0.20
V
3.7
5.0
µA
SYNC Logic Input Leakage Current
SYNC = 3.6V
POWER-GOOD (PG)
Output Low Voltage
IPG = 1mA
PG Delay Time (Rising Edge)
Time from VOUT reached regulation
0.5
PG Delay Time (Falling Edge)
1.0
0.3
V
2.0
ms
6.5
PG Pin Leakage Current
PG = VIN
0.01
OVP PG Rising Threshold
µs
0.10
0.80
UVP PG Rising Threshold
80
UVP PG Hysteresis
85
µA
V
90
5.5
%
%
EN
Logic Input Low
Logic Input High
0.4
V
1.0
µA
0.9
EN Logic Input Leakage Current
V
EN = 3.6V
0.1
Thermal Shutdown
Temperature rising
150
°C
Thermal Shutdown Hysteresis
Temperature falling
25
°C
OVER-TEMPERATURE PROTECTION
NOTE:
7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
Submit Document Feedback
8
FN8713.5
April 1, 2016
ISL78235
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25°C, VIN = VDD = 5V,
VOUT = 1.8V, EN = VDD, SYNC = VDD, L = 0.68µH, fSW = 2MHz, CIN = 2 x 22µF, COUT = 2 x 22µF, IOUT = 0A to 5A.
100
100
90
90
2.5VOUT
1.8VOUT
80
1.5VOUT
70
1.2VOUT
1.0VOUT
60
1.5VOUT
70
0.9VOUT
60
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
40
5.0
0
0.5
1.0
1.5
OUTPUT LOAD (A)
90
90
2.5VOUT
3.3VOUT
1.5VOUT
70
EFFICIENCY (%)
EFFICIENCY (%)
100
1.8VOUT
2.5
3.0
3.5
1.2VOUT
60
50
80
1.8VOUT
1.5VOUT
70
5.0
1.2VOUT
60
50
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
40
0
5.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
OUTPUT LOAD (A)
OUTPUT LOAD (A)
FIGURE 8. EFFICIENCY vs LOAD (5VIN; SYNC = GND)
2.5
2.5
2.5VOUT
2.0
1.8VOUT
POWER DISSIPATION (W)
POWER DISSIPATION (W)
4.5
2.5VOUT
3.3VOUT
FIGURE 7. EFFICIENCY vs LOAD (5VIN; SYNC = VDD)
1.2VOUT
1.5
1.0VOUT
1.0
0.5
0
4.0
OUTPUT LOAD (A)
100
80
2.0
FIGURE 6. EFFICIENCY vs LOAD (3.3VIN; SYNC = GND)
FIGURE 5. EFFICIENCY vs LOAD (3.3VIN; SYNC = VDD)
40
1.2VOUT
50
50
40
1.8VOUT
80
EFFICIENCY (%)
EFFICIENCY (%)
2.5VOUT
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
OUTPUT LOAD (A)
FIGURE 9. POWER DISSIPATION vs LOAD (3.3VIN; SYNC = VDD)
Submit Document Feedback
9
3.3VOUT
2.0
2.5VOUT
1.8VOUT
1.5
1.2VOUT
1.0
0.5
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
OUTPUT LOAD (A)
FIGURE 10. POWER DISSIPATION vs LOAD (5VIN; SYNC = VDD)
FN8713.5
April 1, 2016
ISL78235
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25°C, VIN = VDD = 5V,
1.219
1.810
1.214
1.805
1.209
1.800
1.204
5V PFM
3.3V PFM
1.199
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
VOUT = 1.8V, EN = VDD, SYNC = VDD, L = 0.68µH, fSW = 2MHz, CIN = 2 x 22µF, COUT = 2 x 22µF, IOUT = 0A to 5A. (Continued)
3.3V PWM
5V PWM
1.194
1.189
3.3V PWM
1.790
1.785
1.780
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
1.770
5.0
0
0.5
1.0
2.5
3.0
3.5
4.0
4.5
5.0
75
1.020
PHASE MINIMUM ON-TIME (ns)
3.3V PFM
1.010
3.3V PWM
1.005
1.000
0.995
0.990
0.985
0.980
0
2.0
FIGURE 12. VOUT REGULATION vs LOAD (VOUT = 1.8V)
FIGURE 11. VOUT REGULATION vs LOAD (VOUT = 1.2V)
1.015
1.5
OUTPUT LOAD (A)
OUTPUT LOAD (A)
OUTPUT VOLTAGE (V)
3.3V PFM
5V PWM
1.775
1.184
1.179
5V PFM
1.795
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
T = +125°C
70
65
60
T = +25°C
55
T = -40°C
50
3.0
3.5
OUTPUT LOAD (A)
4.5
5.0
5.5
VIN (V)
FIGURE 13. VOUT REGULATION vs LOAD (VOUT = 1.0V)
FIGURE 14. PHASE MINIMUM ON-TIME vs VIN
PHASE 5V/DIV
PHASE 5V/DIV
SS = GND
COUT = 4 x 22µF
VOUT 1V/DIV
VOUT 1V/DIV
EN 2V/DIV
EN 2V/DIV
PG 5V/DIV
PG 5V/DIV
500µs/DIV
FIGURE 15. EN START-UP AT NO LOAD (SYNC = GND)
Submit Document Feedback
4.0
10
SS = GND
COUT = 4 x 22µF
500µs/DIV
FIGURE 16. EN START-UP AT NO LOAD (SYNC = VDD)
FN8713.5
April 1, 2016
ISL78235
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25°C, VIN = VDD = 5V,
VOUT = 1.8V, EN = VDD, SYNC = VDD, L = 0.68µH, fSW = 2MHz, CIN = 2 x 22µF, COUT = 2 x 22µF, IOUT = 0A to 5A. (Continued)
PHASE 5V/DIV
PHASE 5V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
SS = GND
COUT = 4 x 22µF
VIN 2V/DIV
SS = GND
COUT = 4 x 22µF
VIN 2V/DIV
PG 5V/DIV
PG 5V/DIV
500µs/DIV
500µs/DIV
FIGURE 17. VIN START-UP AT NO LOAD (SYNC = GND)
FIGURE 18. VIN START-UP AT NO LOAD (SYNC = VDD)
PHASE 5V/DIV
PHASE 5V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
SS = GND
COUT = 4 x 22µF
SS = GND
COUT = 4 x 22µF
EN 2V/DIV
EN 2V/DIV
PG 5V/DIV
PG 5V/DIV
1ms/DIV
1ms/DIV
FIGURE 19. EN SHUTDOWN AT NO LOAD (SYNC = GND)
FIGURE 20. EN SHUTDOWN AT NO LOAD (SYNC = VDD)
PHASE 5V/DIV
PHASE 5V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
SS = GND
COUT = 4 x 22µF
SS = GND
COUT = 4 x 22µF
VIN 2V/DIV
VIN 2V/DIV
PG 2V/DIV
PG 2V/DIV
2ms/DIV
2ms/DIV
FIGURE 21. VIN SHUTDOWN AT NO LOAD (SYNC = GND)
FIGURE 22. VIN SHUTDOWN AT NO LOAD (SYNC = VDD)
Submit Document Feedback
11
FN8713.5
April 1, 2016
ISL78235
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25°C, VIN = VDD = 5V,
VOUT = 1.8V, EN = VDD, SYNC = VDD, L = 0.68µH, fSW = 2MHz, CIN = 2 x 22µF, COUT = 2 x 22µF, IOUT = 0A to 5A. (Continued)
IOUT 5A/DIV
IOUT 5A/DIV
SS = GND
COUT = 4 x 22µF
VOUT 1V/DIV
SS = GND
COUT = 4 x 22µF
VOUT 1V/DIV
EN 2V/DIV
EN 2V/DIV
PG 5V/DIV
PG 5V/DIV
500µs/DIV
500µs/DIV
FIGURE 23. EN START-UP AT 5A LOAD (SYNC = GND)
FIGURE 24. EN START-UP AT 5A LOAD (SYNC = VDD)
IOUT 5A/DIV
IOUT 5A/DIV
SS = GND
COUT = 4 x 22µF
VOUT 1V/DIV
SS = GND
COUT = 4 x 22µF
VOUT 1V/DIV
VIN 5V/DIV
VIN 5V/DIV
PG 5V/DIV
PG 5V/DIV
500µs/DIV
500µs/DIV
FIGURE 25. VIN START-UP AT 5A LOAD (SYNC = GND)
FIGURE 26. VIN START-UP AT 5A LOAD (SYNC = VDD)
IOUT 5A/DIV
IOUT 5A/DIV
VOUT 1V/DIV
VOUT 1V/DIV
SS = GND
COUT = 4 x 22µF
SS = GND
COUT = 4 x 22µF
EN 2V/DIV
EN 2V/DIV
PG 5V/DIV
PG 5V/DIV
100µs/DIV
FIGURE 27. EN SHUT-DOWN AT 5A LOAD (SYNC = GND)
Submit Document Feedback
12
100µs/DIV
FIGURE 28. EN SHUT-DOWN AT 5A LOAD (SYNC = VDD)
FN8713.5
April 1, 2016
ISL78235
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25°C, VIN = VDD = 5V,
VOUT = 1.8V, EN = VDD, SYNC = VDD, L = 0.68µH, fSW = 2MHz, CIN = 2 x 22µF, COUT = 2 x 22µF, IOUT = 0A to 5A. (Continued)
PHASE 1V/DIV
PHASE 1V/DIV
5ns/DIV
5ns/DIV
FIGURE 29. JITTER AT NO LOAD (SYNC = VDD)
FIGURE 30. JITTER AT 5A LOAD (SYNC = VDD)
COUT = 4 x 22µF
COUT = 4 x 22µF
PHASE 5V/DIV
PHASE 5V/DIV
VOUT 20mV/DIV AC
VOUT 20mV/DIV AC
I_PHASE 1A/DIV AC
I_PHASE 1A/DIV AC
200ns/DIV
20ms/DIV
FIGURE 32. STEADY STATE AT NO LOAD (SYNC = VDD)
FIGURE 31. STEADY STATE AT NO LOAD (SYNC = GND)
COUT = 4 x 22µF
PHASE 5V/DIV
VOUT 20mV/DIV AC
I_PHASE 1A/DIV AC
200ns/DIV
FIGURE 33. STEADY STATE AT 5A (SYNC = VDD)
Submit Document Feedback
13
FN8713.5
April 1, 2016
ISL78235
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25°C, VIN = VDD = 5V,
VOUT = 1.8V, EN = VDD, SYNC = VDD, L = 0.68µH, fSW = 2MHz, CIN = 2 x 22µF, COUT = 2 x 22µF, IOUT = 0A to 5A. (Continued)
COUT = 4 x 22µF
VOUT 100mV/DIV AC
RCOMP = 154kΩ
CCOMP = 220pF
I_LOAD 2A/DIV
COUT = 4 x 22µF
VOUT 100mV/DIV AC
RCOMP = 154kΩ
CCOMP = 220pF
I_LOAD 2A/DIV
500µs/DIV
500µs/DIV
FIGURE 34. LOAD TRANSIENT 0A TO 5A; 0.5A/µs (SYNC = GND)
PHASE
FIGURE 35. LOAD TRANSIENT 0A TO 5A; 0.5A/µs (SYNC = VDD)
PHASE
VOUT
PG
PG
VOUT
I_PHASE
I_PHASE
FIGURE 36. OUTPUT SHORT-CIRCUIT
CSS = 33nF
SS
PHASE
LOAD = 4A TO 8A STEP
I_PHASE
I_PHASE
VOUT
VOUT
I_LOAD
PG
FIGURE 38. SHORT-CIRCUIT HICCUP WAVEFORM
Submit Document Feedback
FIGURE 37. OUTPUT SHORT-CIRCUIT RECOVERY TO 1A LOAD
14
FIGURE 39. OVERCURRENT PROTECTION
FN8713.5
April 1, 2016
ISL78235
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25°C, VIN = VDD = 5V,
VOUT = 1.8V, EN = VDD, SYNC = VDD, L = 0.68µH, fSW = 2MHz, CIN = 2 x 22µF, COUT = 2 x 22µF, IOUT = 0A to 5A. (Continued)
VOUT INTO 3V SUPPLY
PHASE
VOUT FROM 3V SUPPLY
PHASE
VOUT
VOUT
I_PHASE
I_PHASE
PG
PG
FIGURE 41. OVERVOLTAGE RECOVERY
FIGURE 40. OVERVOLTAGE PROTECTION
V_TEMP
V_TEMP
TEMP = (V_TEMP-1.1092)/4.1mV
+125°C TO +170°C TRANSIENT
LOAD = 4A
PG
PG
VOUT
TEMP = (V_TEMP-1.1092)/4.1mV
+125°C TO +170°C TRANSIENT
LOAD = 4A
FIGURE 42. OVER-TEMPERATURE PROTECTION
Submit Document Feedback
15
VOUT
FIGURE 43. OVER-TEMPERATURE RECOVERY
FN8713.5
April 1, 2016
ISL78235
Theory of Operation
The ISL78235 is a step-down switching regulator optimized for
automotive point-of-load powered applications. The regulator
operates at a 2MHz default switching frequency for high
efficiency and smaller form factor while staying out of the AM
frequency band. By connecting a resistor from FS to SGND, the
operational frequency is adjustable in the range of 500kHz to
4MHz. At light load, the regulator reduces the switching
frequency by operating in Pulse Frequency Modulation (PFM)
mode, unless forced to operate in fixed frequency PWM mode, to
minimize the switching loss and to maximize the battery life. The
quiescent current when the output is not loaded is typically only
45µA. The supply current is typically only 3.8µA when the
regulator is shut down.
PWM Control Scheme
Pulling the SYNC pin HI (>0.8V) forces the converter into PWM
mode, regardless of output current, bypassing the PFM operation
at light load. The ISL78235 employs the current-mode Pulse
Width Modulation (PWM) control scheme for fast transient
response and pulse-by-pulse current limiting (see Figure 3 on
page 3). The current loop consists of the oscillator, the PWM
comparator, current-sensing circuit and the slope compensation
for the current loop stability. The slope compensation is
440mV/Ts (Ts is the switching period), which changes
proportionally with frequency. The gain for the
current-sensing circuit is typically 170mV/A. The control
reference for the current loops comes from the Error Amplifier's
(EAMP) output.
The PWM operation is initialized by the clock from the oscillator.
The P-channel MOSFET is turned on at the beginning of a PWM
cycle and the current in the MOSFET starts to ramp up. When the
sum of the current amplifier CSA and the slope compensation
reaches the control reference of the current loop, the PWM
comparator COMP sends a signal to the PWM logic to turn off the
PFET and turn on the N-channel MOSFET. The NFET stays on until
the end of the PWM cycle. Figure 44 shows the typical operating
waveforms during the PWM operation. The dotted lines on VCSA
illustrate the sum of the slope compensation ramp and the
current-sense amplifier’s CSA output.
The output voltage is regulated by controlling the VEAMP voltage
to the current loop. The bandgap circuit outputs a 0.6V reference
voltage to the voltage loop. The feedback signal comes from the
VFB pin. The soft-start block only affects the operation during the
start-up and is discussed separately. The error amplifier is a
transconductance amplifier that converts the voltage error signal
to a current output. The voltage loop is internally compensated
with the 55pF and 100kΩ RC network. The maximum EAMP
voltage output is precisely clamped to 2.5V.
Submit Document Feedback
16
VEAMP
VCSA
DUTY
CYCLE
IL
VOUT
FIGURE 44. PWM OPERATION WAVEFORMS
SKIP Mode (PFM)
Pulling the SYNC pin low (<0.4V), forces the converter into PFM
mode. The ISL78235 enters a pulse-skipping mode at light load
to minimize the switching loss by reducing the switching
frequency. Figure 45 on page 17 illustrates the Skip mode
operation. A zero-cross sensing circuit shown in Figure 3 on
page 3 monitors the NFET current for zero crossing. When 16
consecutive cycles are detected, the regulator enters the skip
mode. During the sixteen detecting cycles, the current in the
inductor is allowed to become negative. The counter is reset to
zero when the current in any cycle does not cross zero.
Once the Skip mode is entered, the pulse modulation starts
being controlled by the Skip comparator shown in Figure 3 on
page 3. Each pulse cycle is still synchronized by the PWM clock.
The PFET is turned on at the clock's rising edge and turned off
when the output is higher than 1.2% of the nominal regulation or
when its current reaches the peak skip current limit value. Then,
the inductor current is discharging to 0A and stays at zero (the
internal clock is disabled), and the output voltage reduces
gradually due to the load current discharging the output
capacitor. When the output voltage drops to the nominal voltage,
the PFET will be turned on again at the rising edge of the internal
clock as it repeats the previous operations.
The regulator resumes normal PWM mode operation when the
output voltage drops 1.2% below the nominal voltage.
FN8713.5
April 1, 2016
ISL78235
PWM
PFM
PWM
CLOCK
16 CYCLES
PFM CURRENT LIMIT
IL
LOAD CURRENT
0
NOMINAL +1.2%
VOUT
NOMINAL -1.2%
NOMINAL
FIGURE 45. SKIP MODE OPERATION WAVEFORMS
Frequency Adjust
Negative Current Protection
The frequency of operation is fixed at 2MHz when FS is tied to VIN.
The switching frequency is adjustable in the range from 500kHz to
4MHz with a resistor from FS to SGND according to Equation 1:
Similar to overcurrent, the negative current protection is realized
by monitoring the current across the low-side NFET, as shown in
Figure 3 on page 3. When the valley point of the inductor current
reaches -3A for 4 consecutive cycles, both PFET and NFET are off.
A 100Ω discharge circuit in parallel to the NFET activates to
discharge the output into regulation. The regulator resumes
switching operation when output is within regulation. The regulator
will be in PFM for 20µs before switching to PWM if necessary.
220  10 3
R FS  k  = ------------------------------ – 14
f OSC  kHz 
(EQ. 1)
The ISL78235 also has frequency synchronization capability by
connecting the SYNC pin to an external square pulse waveform.
The frequency synchronization feature will synchronize the
positive edge trigger and its switching frequency up to 4MHz. The
synchronization positive pulse width should be 100ns or greater
for proper operation. The minimum external SYNC frequency is
half of the free running oscillator frequency (either the default
2MHz when FS tied to VIN or determined by the resistor from FS
to SGND).
Overcurrent Protection
The overcurrent protection is realized by monitoring the CSA
output with the OCP comparator, as shown in Figure 3 on page 3.
The current-sensing circuit has a gain of 170mV/A typical, from
the PFET current to the CSA output. When the CSA output reaches
the threshold, the OCP comparator is tripped to turn off the PFET
immediately. The overcurrent function protects the switching
converter from a shorted output by monitoring the current flowing
through the upper MOSFET.
Upon detection of an overcurrent condition, the upper MOSFET is
immediately turned off and is not turned on again until the next
switching cycle. Upon detection of the initial overcurrent
condition, the overcurrent fault counter is set to 1. If on the
subsequent cycle another overcurrent condition is detected, the
OC fault counter is incremented. If there are 17 sequential OC
fault detections, the regulator is shut down under an overcurrent
fault condition. An overcurrent fault condition results in the
regulator attempting to restart in a hiccup mode within the delay
of eight soft-start periods. At the end of the 8th soft-start wait
period, the fault counters are reset and soft-start is attempted
again. If the overcurrent condition goes away during the delay of
8 soft-start periods, the output will resume back into regulation
point after hiccup mode expires.
Submit Document Feedback
17
PG
PG is an open-drain output of a window comparator that
continuously monitors the buck regulator output voltage. PG is
actively held low when EN is low and during the buck regulator
soft-start period. A 1ms delay after the soft-start period, PG
becomes high impedance as long as the output voltage is within
nominal regulation voltage set by VFB. When the voltage at FB pin
drops 15% below 0.6V or rises above 0.8V, the ISL78235 pulls PG
low. Any fault condition forces PG low until the fault condition is
cleared and after soft-start completes. For logic level output
voltages, connect an external pull-up resistor between PG and VIN. A
100kΩ resistor works well in most applications.
UVLO
When the input voltage is below the Undervoltage Lockout
(UVLO) threshold (2.5V typical), the regulator is disabled.
Soft Start-Up
The soft start-up circuit reduces the inrush current during
power- up. The soft-start block outputs a ramp reference to the
input of the error amplifier. This voltage ramp limits the slew rate
of inductor current as well as the output voltage, so that the
output voltage rises in a controlled fashion. When VFB is less
than 0.1V at the beginning of the soft-start, the switching
frequency is reduced to 200kHz, so that the output can start-up
smoothly at light load condition. During soft-start, the IC operates
in the skip mode to support prebiased output condition.
FN8713.5
April 1, 2016
ISL78235
When a transition to shutdown mode occurs, (EN low or fault
condition) or the VIN UVLO is set, the output is discharged to GND
through an internal 100Ω switch on the PHASE pin.
Power MOSFETs
The power MOSFETs are optimized for highest efficiency. The
ON-resistance for the PFET is typically 35mΩ and the
ON-resistance for the NFET is typically 11mΩ.
100% Duty Cycle
The ISL78235 features a 100% duty cycle operation to maximize
the battery operation life and provide very low dropout down to
the minimum operating voltage. When the battery voltage drops
to a level that the ISL78235 can no longer maintain the
regulation at the output, the regulator completely turns on the
PFET. The maximum dropout voltage under the 100% duty cycle
operation is the product of the load current and the
ON-resistance of the PFET.
Table 2, shows the minimum output capacitor value is given for
the different output voltages to make sure that the whole
converter system is stable. Additional output capacitance should
be added for better performance in applications where high load
transient or low output ripple is required. It is recommended to
check the system level performance along with the simulation
model.
Output Voltage Selection
The output voltage of the regulator is programmed with an external
resistor divider that is used to scale the output voltage relative to the
internal reference voltage (0.6V) and fed back to the inverting input
of the error amplifier FB pin (see Figure 46).
VOUT
VIN
16
VIN
Thermal Shutdown
VDD
PG
SYNC
13
12
2
11
ISL78235
10
3
9
4
5
Applications Information
14
1
EN
The ISL78235 has built-in over-temperature thermal protection.
When the internal temperature reaches +150°C, the regulator
completely shuts down. As the temperature drops to +125°C, the
ISL78235 resumes operation after a soft-start cycle.
15
PHASE
Discharge Mode (Soft-Stop)
The ISL78235 uses an internal compensation network for
regulator stability and the output capacitor value is dependent on
the output voltage. The recommended ceramic capacitors are
low ESR X7R rated or better. The recommended minimum output
capacitor values are shown in Table 2 on page 6.
6
7
8
PGND
PGND
SGND
R2
FB
R3
COMP
The Enable (EN) input allows the user to control the turning on or
off of the regulator for purposes such as power-up sequencing or
minimizing power dissipation when the output is not needed.
When the regulator is enabled, there is typically a 600µs delay
for waking up the bandgap reference and then the soft start-up
begins.
PHASE
Enable
The inductor’s saturation current rating needs to be larger than
the positive peak current limit specified in the electrical
specification table. The ISL78235 has a typical peak current limit
of 7.5A. The inductor saturation current needs to be over 7.5A for
proper operation.
SS
CSS must be less than 33nF to insure proper soft-start reset after
fault condition.
(EQ. 3)
PHASE
(EQ. 2)
V OUT

V OUT   1 – ----------------
V IN 

I = ----------------------------------------------------L  f SW
FS
C SS  F  = 3.1  t SS  s 
performance. The inductor ripple current can be expressed as
shown in Equation 3:
VIN
Tie SS to SGND for internal soft-start (1ms typical). Connect a
capacitor from SS to SGND to adjust the soft-start time. This
capacitor, along with an internal 2.1µA current source, sets the
soft-start interval of the converter, tSS as shown by Equation 2.
Output Inductor and Capacitor Selection
To consider steady state and transient operation, the ISL78235
typically uses a 0.33µH to 0.78µH output inductor. Higher or
lower inductor values can be used to optimize the total converter
system performance. For example, for a higher output voltage
3.3V application, in order to decrease the inductor current ripple
and output voltage ripple, the output inductor value can be
increased. It is recommended to set the ripple inductor current to
approximately 30% of the maximum output current for optimized
Submit Document Feedback
18
FIGURE 46. PROGRAMMING OUTPUT VOLTAGE WITH R2 AND R3
The output voltage programming resistor R2 (from VOUT to FB)
will depend on the value chosen for the feedback resistor and the
desired output voltage of the regulator. The value for the
feedback resistor, R3 (from FB to GND), is typically between
10kΩ and 100kΩ. R2 is chosen as shown in Equation 4. Where
VFB = 0.6V and VOUT is the output voltage.
V OUT
R 2 = R 3  ---------------- – 1
 VFB

(EQ. 4)
FN8713.5
April 1, 2016
ISL78235
There is a leakage current from VIN to PHASE. It is recommended
to preload the output with 10µA minimum for accurate output
voltage. For improved loop stability performance, add 10pF to
22pF in parallel with R2. Check loop analysis before use in
application. See “Loop Compensation Design” for more
information.
Input Capacitor Selection
Vo
R2
VFB
R3
The main functions for the input capacitor are to provide
decoupling of the parasitic inductance and to provide a filtering
function to prevent the switching current flowing back to the
input rail. Two 22µF low ESR X7R rated ceramic capacitors in
parallel with a 0.1µF high frequency decoupling capacitor placed
very close to the VIN/VDD and SGND/PGND pins is a good
starting point for the input capacitor selection.
Loop Compensation Design
When COMP is not connected to VDD, the COMP pin is active for
external loop compensation. The ISL78235 uses constant
frequency peak current mode control architecture to achieve a
fast loop transient response. An accurate current-sensing circuit
in parallel with the upper MOSFET is used for peak current
control signal and overcurrent protection. The inductor is not
considered as a state variable since its peak current is constant
and the system becomes a single order system. It is much easier
to design a type II compensator to stabilize the loop than to
implement voltage mode control. Peak current mode control has
an inherent input voltage feed-forward function to achieve good
line regulation. Figure 47 shows the small signal model of the
synchronous buck regulator.
^
Vin
+
^
i in
ILd^
1:D
^
iL
LP
^
vo
RT
VCOMP
GM
+
R6
C7
C6
FIGURE 48. TYPE II COMPENSATOR
Figure 48 shows the type II compensator and its transfer function
is expressed as Equation 5:
S 
S
 1 + ------------ 1 + -------------

GM  R 3
 cz1 
 cz2
v̂ comp
A v  S  = ----------------- = -------------------------------------------------------- --------------------------------------------------------------- (EQ. 5)
 C6 + C7    R2 + R3  
S
S
v̂ FB
S 1 + -------------  1 + -------------





cp1
cp2
Where,
R2 + R3
C6 + C7
1
1
 cz1 = --------------- ,  cz2 = ---------------  cp1 = -----------------------  cp2 = ----------------------R
C
R6 C6
R2 C3
6 C6 C7
3 R2 R3
Compensator design goal:
High DC gain
Choose Loop bandwidth fc ~100kHz or less
Gain margin: >10dB
Phase margin: >40°
The loop gain at crossover frequency of fc has a unity gain.
Therefore, the compensator resistance R6 is determined by
Equation 6.
Rc
Ro
Co
2f c V o C o R t
3
R 6 = ---------------------------------- = 13.7 10  f c V o C o
GM  V FB
T i(S)
d^
(EQ. 6)
K
Fm
+
VREF
-
The compensator design procedure is as follows:
Vin d^
+
GAIN (VLOOP (S(fi))
RLP
C3
Tv (S)
He(S)
v^comp
-Av(S)
FIGURE 47. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK
REGULATOR
Where GM is the transconductance, gm, of the voltage error
amplifier and Rt is the gain of the current sense amplifier.
Compensator capacitors C6 and C7 are given by Equation 7.
Ro Co Vo Co
Rc Co 1
C 6 = --------------- = --------------- ,C 7 = max (--------------,----------------)
R6
Io R6
R 6 f s R 6
(EQ. 7)
Put one compensator pole at zero frequency to achieve high DC
gain, and put another compensator pole at either ESR zero
frequency or half switching frequency, whichever is lower in
Equation 7. An optional zero can boost the phase margin. CZ2 is
a zero due to R2 and C3
Put compensator zero 2 to 5 times fc :
1
C 3 = ---------------f c R 2
Submit Document Feedback
19
(EQ. 8)
FN8713.5
April 1, 2016
ISL78235
Example: VIN = 5V, VO = 1.8V, IO = 5A, fSW = 2MHz, R2 = 200kΩ,
R3 = 100kΩ, Co = 2 x22µF/10mΩ, L = 0.68µH, fc = 100kHz, then
compensator resistance R6:
3
(EQ. 9)
R 6 = 13.7 10  100kHz  1.8V  44F = 108k
It is acceptable to use 107kΩas theclosest standard value for
R6.
1.8V  44 F
C 6 = -------------------------------- = 148pF
5A  107k
(EQ. 10)
10m  44F
1
C 7 = max (------------------------------------,------------------------------------------------) = (4.1pF,1.5pF) (EQ. 11)
107k
  2MHz  107k 
It is also acceptable to use the closest standard values for C6 and
C7. There is approximately 3pF parasitic capacitance from VCOMP to
GND. Therefore, C7 is optional. Use C6 = 150pF and C7 = OPEN.
1
C 3 = ------------------------------------------------ = 16pF
100kHz  200k
(EQ. 12)
PCB Layout Recommendation
The PCB layout is a very important converter design step to make
sure the designed converter works well. For the ISL78235 the
power loop is composed of the output inductor L0, the output
capacitor CO, the PHASE pins and the PGND pin. It is necessary
to make the power loop as small as possible and the connecting
traces among them should be direct, short and wide. The
switching node of the converter, the PHASE pins and the traces
connected to the node are very noisy, so keep the voltage
feedback trace away from these noisy traces. The input capacitor
should be placed as close as possible to the VIN pin. The ground
of the input and output capacitors should be connected as close
as possible. The heat of the IC is mainly dissipated through the
thermal pad. Maximizing the copper area connected to the
thermal pad is preferable. In addition, a solid ground plane is
helpful for better EMI performance. Refer to TB389 for via
placement on the copper area of the PCB underneath the
thermal pad for optimum thermal performance.
Use C3 = 10pF. Note that C3 may increase the loop bandwidth
from previous estimated value. Figure 49 shows the simulated
voltage loop gain. It is shown that it has a 120kHz loop
bandwidth with a 58° phase margin and 8dB gain margin. It may
be more desirable to achieve an increased phase and gain
margin. This can be accomplished by lowering R6 by 10% to
20%.
60
CLOSED LOOP GAIN (dB)
40
20
0
-20
-40
-60
100
1k
10k
100k
1M
100k
1M
FREQUENCY (Hz)
200
CLOSED LOOP PHAE (°)
150
100
50
0
-50
-100
-150
100
1k
10k
FREQUENCY (Hz)
FIGURE 49. SIMULATED LOOP GAIN AND PHASE
Submit Document Feedback
20
FN8713.5
April 1, 2016
ISL78235
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
April 1, 2016
FN8713.5
Updated Figure 10 title on page 9.
CHANGE
December 11, 2015
FN8713.4
Added a new User Guide to Related Literature section on page 1.
Added ISL78235EVAL2Z to the ordering information table on page 5.
Added table1 on page 5.
November 10, 2015
FN8713.3
Added 5x5mmWFQFN information throughout datasheet.
Removed “Li-Ion Battery Powered devices” application bullet from page 1.
Updated Note 1 on page 5 from “Add “-T*” suffix for tape and reel.” to “Add “-T” suffix for 6k unit or “-T7A” suffix
for 250 unit tape and reel options.”
On page 8, removed the test condition “TA = -40°C to +105°C” for the INLIMIT specifications.
On page 8, added “TA = -40°C to +105°C to the test conditions of the Transresistance specification.”
In “PWM Control Scheme” on page 16 (last sentence) corrected a typo by changing “1.6V to “2.5V”.
Updated the “PCB Layout Recommendation” section.
July 1, 2015
FN8713.2
Figures 15 through 28 changed “CSS = 33nF” to “SS = GND”.
February 20, 2015
FN8713.1
Electrical Spec table, Oscillator section on page 8:
Changed nominal switching frequency minimum from 1700kHz to 1730kHz.
February 3, 2015
FN8713.0
Initial Release
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
For additional products, see www.intersil.com/en/products.html
Intersil Automotive Qualified products are manufactured, assembled and tested utilizing TS16949 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
Submit Document Feedback
21
FN8713.5
April 1, 2016
ISL78235
Package Outline Drawing
L16.3x3D
16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 3/10
4X 1.50
3.00
A
12X 0.50
B
13
6
PIN 1
INDEX AREA
16
6
PIN #1
INDEX AREA
12
3.00
1
1.60 SQ
4
9
(4X)
0.15
8
0.10 M C A B
5
16X 0.40±0.10
TOP VIEW
4 16X 0.23 ±0.05
BOTTOM VIEW
SEE DETAIL “X”
0.10 C
0.75 ±0.05
C
0.08 C
SIDE VIEW
(12X 0.50)
(2.80 TYP) (
1.60)
(16X 0.23)
C
0 . 2 REF
5
0 . 02 NOM.
0 . 05 MAX.
(16X 0.60)
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance: Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.25mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
7.
JEDEC reference drawing: MO-220 WEED.
either a mold or mark feature.
Submit Document Feedback
22
FN8713.5
April 1, 2016
ISL78235
Package Outline Drawing
L16.5x5D
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (PUNCH QFN WITH WETTABLE FLANK)
Rev 2, 5/14
A
0.10 C A (2X)
5.00
4.75
16
0.10 C B (2X)
0.10 M C A B
2.8
0.60 MAX. (4X)
PIN 1 ID
R0.20
16
0.60 MAX. (4X)
0.45
0.10 M C B A
1
5
0.50 DIA
1
5.00
2
2
2.8
4.75
3
3
(0.70)
CC
(2X)
0.10 C B
(2X)
0.40±0.10
0.15±0.10
0.10 C A
B
TOP VIEW
0.08 C
// 0.10 C
0.85 ± 0.05
TERMINAL TIP 4
0.30±0.05
0.10 M C A B
0.05 M C
(0.70)
0.80
5
BOTTOM VIEW
+ 0.04
0.01 - 0.01
0.65 ± 0.05
(0.20)
0.20
0.10
4
SEE DETAIL “A”
(0.01)
SECTION “C-C”
SCALE: NONE
12° MAX
4
DETAIL “A” (DIMPLE DEPTH)
SCALE: NONE
SEATING PLANE
C
SIDE VIEW
NOTES:
12X (0.80)
1. Dimensions are in millimeters.
Dimensions in ( ) are for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
(2.80) SQ
3. Unless otherwise specified, tolerance: Decimal ± 0.05
(4.80) SQ
4. Dimension applies to the plated terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
16X (0.30)
16X (0.60)
TYPICAL RECOMMENDED LAND PATTERN
Submit Document Feedback
23
5. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
6.
Reference document: JEDEC M0220.
FN8713.5
April 1, 2016