DATASHEET 3A and 4A Compact Synchronous Buck Regulators ISL78233, ISL78234 Features The ISL78233, ISL78234 are highly efficient, monolithic, synchronous step-down DC/DC converters that can deliver 3A (ISL78233), or 4A (ISL78234) of continuous output current from a 2.7V to 5.5V input supply. The devices use current mode control architecture to deliver a very low duty cycle operation at high frequency with fast transient response and excellent loop stability. • 2.7V to 5.5V input voltage range • Very low ON-resistance FETs - P-channel 35mΩ and N-Channel 11mΩ typical values • High efficiency synchronous buck regulator with up to 95% efficiency • -1.2%/1% reference accuracy over temperature/load/line The ISL78233, ISL78234 integrate a very low ON-resistance P-channel (35mΩ) high-side FET and N-channel (11mΩ) low-side FET to maximize efficiency and minimize external component count. The 100% duty-cycle operation allows less than 200mV dropout voltage at 4A output current. The operation frequency of the Pulse Width Modulator (PWM) is adjustable from 500kHz to 4MHz. The default switching frequency of 2MHz is set by connecting the FS pin high. • Complete BOM with as few as 3 external parts • Internal soft-start - 1ms or adjustable • Soft-stop output discharge during disable • Adjustable frequency from 500kHz to 4MHz - default at 2MHz • External synchronization up to 4MHz The ISL78233, ISL78234 can be configured for discontinuous or forced continuous operation at light load. Forced continuous operation reduces noise and RF interference, while discontinuous mode provides higher efficiency by reducing switching losses at light loads. Fault protection is provided by internal hiccup mode current limiting during short-circuit and overcurrent conditions. Other protection, such as overvoltage and over-temperature are also integrated into the device. A power-good output voltage monitor indicates when the output is in regulation. • Over-temperature, overcurrent, overvoltage and negative overcurrent protection • Shared common device pinout allows simplified output power upgrades over time • Tiny 3mmx3mm TQFN package • AEC-Q100 qualified Applications • DC/DC POL modules The ISL78233, ISL78234 offers a 1ms Power-Good (PG) timer at power-up. When in shutdown, the ISL78233, ISL78234 discharges the output capacitor through an internal soft-stop switch. Other features include internal fixed or adjustable soft-start and internal/external compensation. • μC/µP, FPGA and DSP power The ISL78233, ISL78234 is available in a 3mmx3mm 16 Ld Thin Quad Flat Pb-free (TQFN) package and in a 5mmx5mm 16 Ld Wettable Flank Quad Flat No-Lead (WFQFN) package with an exposed pad for improved thermal performance. The ISL78233, ISL78234 are rated to operate across the temperature range of -40°C to +125°C. Related Literature • Video processor/SOC power • Li-ion battery powered devices • Automotive infotainment power • UG015, “ISL7823xEVAL1Z Evaluation Board User Guide” • ISL78235 datasheet. • UG062, “ISL7823xEVAL2Z Evaluation Board User Guide” 100 3.3VOUT EFFICIENCY (%) 90 80 1.2VOUT 1.5VOUT 1.8VOUT 70 2.5VOUT 60 50 40 0.0 0.5 1.0 1.5 2.0 2.5 OUTPUT LOAD (A) 3.0 3.5 4.0 FIGURE 1. EFFICIENCY vs LOAD (2MHz 5VIN PFM, TA = +25°C) December 4, 2015 FN8359.7 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2013-2015. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL78233, ISL78234 Pin Configuration 16 15 14 PHASE PHASE PHASE VIN ISL78233, ISL78234 (16 LD TQFN) TOP VIEW 13 11 PGND PG 3 10 SGND SYNC 4 9 FB 5 6 7 8 COMP VDD 2 SS PGND FS 12 EN VIN 1 Pin Descriptions PIN NUMBER SYMBOL DESCRIPTION 1, 16 VIN Input supply voltage. Place a minimum of two 22µF ceramic capacitors from VIN to PGND as close as possible to the IC for decoupling. 2 VDD 3 PG Power-good is an open-drain output. Use a 10kΩ to 100kΩ pull-up resistor connected between VIN and PG. At power-up or EN HI, PG rising edge is delayed by 1ms upon output reached within regulation. 4 SYNC Mode Selection pin. Connect to logic high or input voltage VIN for PWM mode. Connect to logic low or ground for PFM mode. Connect to an external function generator for synchronization with the positive edge trigger. There is an internal 1MΩ pull-down resistor to prevent an undefined logic state in case of SYNC pin float. 5 EN Regulator enable pin. Enable the output when driven to high. Shutdown the chip and discharge output capacitor when driven to low. 6 FS This pin sets the oscillator switching frequency, using a resistor, RFS, from the FS pin to GND. The frequency of operation may be programmed between 500kHz to 4MHz. The default frequency is 2MHz if FS is connected to VIN. 7 SS SS is used to adjust the soft-start time. Set to SGND for internal 1ms rise time. Connect a capacitor from SS to SGND to adjust the soft-start time. Do not use more than 33nF per IC. 8, 9 COMP, FB The feedback network of the regulator, FB, is the negative input to the transconductance error amplifier. COMP is the output of the amplifier if COMP not tied to VDD. Otherwise, COMP is disconnected through a MOSFET for internal compensation. Must connect COMP to VDD in internal compensation mode. The output voltage is set by an external resistor divider connected to FB. With a properly selected divider, the output voltage can be set to any voltage between the power rail (reduced by converter losses) and the 0.6V reference. There is an internal compensation to meet a typical application. Additional external networks across COMP and SGND might be required to improve the loop compensation of the amplifier operation. In addition, the regulator power-good and undervoltage protection circuitry use FB to monitor the regulator output voltage. Input supply voltage for logic. Connect to VIN pin. 10 SGND Signal ground 11, 12 PGND Power ground 13, 14, 15 PHASE Switching node connections. Connect to one terminal of the inductor. This pin is discharged by a 100Ω resistor when the device is disabled. See “Functional Block Diagram” on page 5 for more detail. Exposed Pad - Submit Document Feedback 2 The exposed pad must be connected to the SGND pin for proper electrical performance. Place as many vias as possible under the pad connecting to SGND plane for optimal thermal performance. FN8359.7 December 4, 2015 ISL78233, ISL78234 Ordering Information PART NUMBER (Notes 1, 2, 3) PART MARKING OUTPUT VOLTAGE (V) TEMP. RANGE (°C) PACKAGE (RoHS Compliant) PKG. DWG. # ISL78233ARZ 8233 Adjustable -40 to +125 16 Ld 3x3 TQFN L16.3x3D ISL78233AARZ 78233A ARZ Adjustable -40 to +125 16 Ld 5x5mm WFQFN L16.5x5D ISL78234ARZ 8234 Adjustable -40 to +125 16 Ld 3x3 TQFN L16.3x3D ISL78234AARZ 78234A ARZ Adjustable -40 to +125 16 Ld 5x5mm WFQFN L16.5x5D ISL78233EVAL1Z 3x3mm TQFN Evaluation Board ISL78234EVAL1Z 3x3mm TQFN Evaluation Board ISL78233EVAL2Z 5x5mm WFQFN Evaluation Board ISL78234EVAL2Z 5x5mm WFQFN Evaluation Board NOTES: 1. Add “-T” suffix for 6k unit or “-T7A” suffix for 250 unit tape and reel options. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL78233, ISL78234 For more information on MSL please see techbrief TB363. TABLE 1. KEY DIFFERENCE BETWEEN FAMILY OF PARTS PART NUMBER IOUT MAX (A) ISL78233 3 ISL78234 4 ISL78235 5 Submit Document Feedback 3 FN8359.7 December 4, 2015 ISL78233, ISL78234 Typical Application Diagram 1 C1 2 x 22µF R1 100k 2 3 PG +1.8V/4A 1.0µH C2 2 x 22µF 13 14 ISL78233, ISL78234 VOUT GND PGND 12 VDD PGND PG SGND R2 200k C3* 22pF 11 10 R3 9 +0.6V 100k PAD 17 8 SS 7 *C3 IS OPTIONAL. IT IS RECOMMENDED TO PUT A PLACEHOLDER FOR IT AND CHECK LOOP ANALYSIS BEFORE USE. EN 5 FB COMP SYNC EN 4 FS GND VIN PHASE +2.7V …+5.5V 6 VIN PHASE 15 VIN PHASE 16 L1 FIGURE 2. TYPICAL APPLICATION DIAGRAM TABLE 2. COMPONENT SELECTION TABLE VOUT 1.2V 1.5V 1.8V 2.5V 3.3V 3.6V C1 2 x 22µF 2 x 22µF 2 x 22µF 2 x 22µF 2 x 22µF 2 x 22µF C2 2 x 22µF 2 x 22µF 2 x 22µF 2 x 22µF 2 x 22µF 2 x 22µF C3 22pF 22pF 22pF 22pF 22pF 22pF L1 0.33-0.68µH 0.33-0.68µH 0.33-0.68µH 0.47-0.78µH 0.47-0.78µH 0.47-0.78µH R2 100kΩ 150kΩ 200kΩ 316kΩ 450kΩ 500kΩ R3 100kΩ 100kΩ 100kΩ 100kΩ 100kΩ 100kΩ Submit Document Feedback 4 FN8359.7 December 4, 2015 ISL78233, ISL78234 COMP SS SHUTDOWN SYNC 55pF Soft SOFTSTART SHUTDOWN VDD 100kΩ + BANDGAP VREF + EN FS + COMP - EAMP - VIN OSCILLATOR PWM/PFM LOGIC CONTROLLER PROTECTION HS DRIVER 3pF + P PHASE LS DRIVER N PGND FB 6kΩ SLOPE Slope COMP 0.8V + CSA - + OV 0.85*VREF PG + UV + OCP - + SKIP - ISET THRESHOLD 1ms DELAY NEG CURRENT SENSING SGND ZERO-CROSS SENSING 0.5V SCP + 100Ω SHUTDOWN FIGURE 3. FUNCTIONAL BLOCK DIAGRAM Submit Document Feedback 5 FN8359.7 December 4, 2015 ISL78233, ISL78234 Absolute Maximum Ratings (Reference to GND) Thermal Information VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.8V (DC) or 7V (20ms) EN, FS, PG, SYNC, VFB . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN + 0.3V PHASE . . . . . . . . . . . . -1.5V (100ns)/-0.3V (DC) to 6.5V (DC) or 7V (20ms) COMP, SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V ESD Rating Human Body Model (Tested per AEC-Q100-002) . . . . . . . . . . . . . . . . 5kV Machine Model (Tested per AEC-Q100-003) . . . . . . . . . . . . . . . . . . 300V Charge Device Model (Tested per AEC-Q100-011) . . . . . . . . . . . . . . . 2kV Latch-Up (Tested per AEC-Q100-004, Class II, Level A) . . . . . . . . . . 100mA Thermal Resistance JA (°C/W) JC (°C/W) 16 Ld TQFN Package (Notes 4, 5) . . . . . . . 43 3.5 16 Ld WFQFN Package (Notes 4, 5) . . . . . 33 3.5 Operating Junction Temperature Range . . . . . . . . . . . . . .-55°C to +125°C Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 Recommended Operating Conditions VIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Load Current Range (ISL78233) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 3A (ISL78234) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 4A Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 5. JC, “case temperature” location is at the center of the exposed metal pad on the package underside. Electrical Specifications Unless otherwise noted, all parameter limits are established over the recommended operating conditions and the specification limits are measured at the following conditions: TA = -40°C to +125°C, VIN = 3.6V, EN = VIN, unless otherwise noted. Typical values are at TA = +25°C. Boldface limits apply across the operating temperature range, -40°C to +125°C. PARAMETER MIN (Note 6) TYP MAX (Note 6) 2.5 2.7 2.2 2.45 V SYNC = GND, no load at the output 45 µA SYNC = GND, no load at the output and no switches switching 45 60 µA SYNC = VIN, FS = 2MHz, no load at the output 19 25 mA SYNC = GND, VIN = 5.5V, EN = low 3.8 10 µA 0.600 0.606 V SYMBOL TEST CONDITIONS UNIT INPUT SUPPLY VIN Undervoltage Lockout Threshold VUVLO Rising, no load Falling, no load Quiescent Supply Current IVIN Shutdown Supply Current ISD V OUTPUT REGULATION Reference Voltage VREF VFB Bias Current IVFB 0.593 VFB = 0.75V 0.1 µA Line Regulation VIN = VO + 0.5V to 5.5V (minimal 2.7V) 0.2 %/V Soft-Start Ramp Time Cycle SS = SGND 1 ms Soft-Start Charging Current ISS VSS = 0.1V 1.7 2.1 2.5 µA OVERCURRENT PROTECTION Current Limit Blanking Time tOCON 17 Clock pulses Overcurrent and Auto Restart Period tOCOFF 8 SS cycle Positive Peak Current Limit IPLIMIT Submit Document Feedback 6 ISL78234, TA = +25°C 5.4 ISL78234, TA = -40°C to +125°C 5.2 ISL78233, TA = +25°C 3.9 ISL78233, TA = -40°C to +125°C 3.7 6.7 8.1 A 9 A 4.9 6 A 6.6 A FN8359.7 December 4, 2015 ISL78233, ISL78234 Electrical Specifications Unless otherwise noted, all parameter limits are established over the recommended operating conditions and the specification limits are measured at the following conditions: TA = -40°C to +125°C, VIN = 3.6V, EN = VIN, unless otherwise noted. Typical values are at TA = +25°C. Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued) PARAMETER SYMBOL Peak Skip Limit ISKIP TEST CONDITIONS ISL78234, TA = +25°C ISL78234, TA = -40°C to +125°C ISL78233, TA = +25°C ISL78233, TA = -40°C to +125°C Zero Cross Threshold Negative Current Limit INLIMIT MIN (Note 6) TYP MAX (Note 6) UNIT 0.9 1.1 1.35 A 1.5 A 1.2 A 0.84 0.7 0.9 0.6 1.3 A -275 375 mA -1.3 A -0.6 A TA = +25°C -5.1 TA = -40°C to +125°C -6.0 -2.8 COMPENSATION Error Amplifier Transconductance COMP = VDD, Internal compensation 125 External compensation Transresistance RT 4A application µA/V 130 0.145 0.2 µA/V 0.25 Ω PHASE P-Channel MOSFET ON-Resistance N-Channel MOSFET ON-Resistance VIN = 5V, IO = 200mA 26 35 50 mΩ VIN = 2.7V, IO = 200mA 38 52 78 mΩ VIN = 5V, IO = 200mA 5 11 20 mΩ VIN = 2.7V, IO = 200mA 8 15 31 mΩ 100 ns 2350 kHz PHASE Maximum Duty Cycle 100 PHASE Minimum On-Time SYNC = High % OSCILLATOR Nominal Switching Frequency fSW FS = VIN 1700 2000 FS with RS = 402kΩ 420 kHz FS with RS = 42.2kΩ 4200 kHz SYNC Logic LOW to HIGH Transition Range 0.67 SYNC Hysteresis 0.75 0.84 0.17 SYNC Logic Input Leakage Current VIN = 3.6V 3.7 V V 5 µA 0.3 V 1 2 ms 0.01 0.1 µA PG Output Low Voltage IPG = 1mA Delay Time (Rising Edge) Time from VOUT reached regulation PG Pin Leakage Current PG = VIN 0.5 OVP PG Rising Threshold 0.80 UVP PG Rising Threshold 80 86 V 90 % UVP PG Hysteresis 5.5 % PGOOD Delay Time (Falling Edge) 6.5 µs EN Logic Input Low Logic Input High 0.4 V 1 µA 0.9 V EN Logic Input Leakage Current Pulled up to 3.6V 0.1 Thermal Shutdown Temperature Rising 150 °C Thermal Shutdown Hysteresis Temperature Falling 25 °C NOTE: 6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. Submit Document Feedback 7 FN8359.7 December 4, 2015 ISL78233, ISL78234 Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 5V, EN = VIN, SYNC = VIN, L = 1.0µH, C1 = 22µF, C2 = 2 x 22µF, IOUT = 0A to 4A. 100 100 2.5VOUT 2.5VOUT 90 80 1.5VOUT 1.2VOUT EFFICIENCY (%) EFFICIENCY (%) 90 1.8VOUT 70 60 50 80 1.5VOUT 1.2VOUT 1.8VOUT 70 60 50 40 0.0 0.5 1.0 1.5 2.0 2.5 OUTPUT LOAD (A) 3.0 3.5 40 4.0 0.0 FIGURE 4. EFFICIENCY vs LOAD (2MHz, 3.3VIN PWM) 0.5 1.0 1.5 2.0 2.5 OUTPUT LOAD (A) 3.0 3.5 4.0 FIGURE 5. EFFICIENCY vs LOAD (2MHz, 3.3VIN PFM) 100 100 2.5VOUT 3.3VOUT 3.3VOUT 90 90 1.5VOUT 80 1.2VOUT EFFICIENCY (%) EFFICIENCY (%) 2.5VOUT 1.8VOUT 70 60 1.2VOUT 60 0.0 0.5 1.0 1.5 2.0 2.5 OUTPUT LOAD (A) 3.0 3.5 40 0.0 4.0 FIGURE 6. EFFICIENCY vs LOAD (2MHz, 5VIN PWM) 1.219 1.515 1.214 1.510 1.209 3.3VIN PFM 1.204 5VIN PFM 1.199 5VIN PWM 1.194 1.189 3.3VIN PWM 1.184 1.179 0.5 1.0 1.5 2.0 2.5 OUTPUT LOAD (A) 3.0 3.5 4.0 FIGURE 7. EFFICIENCY vs LOAD (2MHz, 5VIN PFM) OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 1.8VOUT 70 50 50 40 1.5VOUT 80 3.3VIN PFM 1.505 1.500 5VIN PFM 1.495 5VIN PWM 1.490 1.485 3.3VIN PWM 1.480 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 OUTPUT LOAD (A) FIGURE 8. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.2V) Submit Document Feedback 8 4.0 1.475 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 OUTPUT LOAD (A) FIGURE 9. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.5V) FN8359.7 December 4, 2015 ISL78233, ISL78234 Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 5V, EN = VIN, 1.815 2.505 1.810 2.500 1.805 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) SYNC = VIN, L = 1.0µH, C1 = 22µF, C2 = 2 x 22µF, IOUT = 0A to 4A. (Continued) 3.3VIN PFM 1.800 5VIN PFM 1.795 5VIN PWM 1.790 1.785 3.3VIN PWM 1.780 1.775 0.0 0.5 1.0 2.495 3.3VIN PFM 2.490 5VIN PFM 2.485 2.475 3.3VIN PWM 2.470 1.5 2.0 2.5 3.0 3.5 4.0 5VIN PWM 2.480 2.465 0.0 0.5 1.0 1.5 2.5 3.0 3.5 4.0 FIGURE 11. VOUT REGULATION vs LOAD (1MHz, VOUT = 2.5V) FIGURE 10. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.8V) 3.309 75 PHASE MINIMUM ON-TIME (ns) 3.301 OUTPUT VOLTAGE (V) 2.0 OUTPUT LOAD (A) OUTPUT LOAD (A) 5VIN PWM 3.293 3.285 5VIN PFM 3.277 3.269 3.261 3.253 3.245 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 T = +125°C 70 65 60 T = +25°C 55 T = -40°C 50 3.0 3.5 4.0 OUTPUT LOAD (A) FIGURE 12. VOUT REGULATION vs LOAD (1MHz, VOUT = 3.3V) PHASE 5V/DIV 4.5 VIN (V) 5.5 6.0 FIGURE 13. PHASE MINIMUM ON-TIME vs VIN (2MHz) PHASE 5V/DIV VOUT 1V/DIV VOUT 1V/DIV VEN 5V/DIV VEN 5V/DIV PG 5V/DIV PG 5V/DIV 400µs/DIV FIGURE 14. START-UP AT NO LOAD (PFM) Submit Document Feedback 5.0 9 400µs/DIV FIGURE 15. START-UP AT NO LOAD (PWM) FN8359.7 December 4, 2015 ISL78233, ISL78234 Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 5V, EN = VIN, SYNC = VIN, L = 1.0µH, C1 = 22µF, C2 = 2 x 22µF, IOUT = 0A to 4A. (Continued) PHASE 5V/DIV VOUT 1V/DIV PHASE 5V/DIV VOUT 1V/DIV VEN 5V/DIV VEN 5V/DIV PG 5V/DIV PG 5V/DIV 400µs/DIV 400µs/DIV FIGURE 16. SHUTDOWN AT NO LOAD (PFM) PHASE 5V/DIV FIGURE 17. SHUTDOWN AT NO LOAD (PWM) PHASE 5V/DIV VOUT 1V/DIV VOUT 1V/DIV VEN 5V/DIV VEN 5V/DIV PG 5V/DIV PG 5V/DIV 500µs/DIV FIGURE 18. START-UP AT 4A LOAD (PWM) 500µs/DIV FIGURE 19. SHUTDOWN AT 4A LOAD (PWM) IOUT 2A/DIV IOUT 2A/DIV VOUT 1V/DIV VOUT 1V/DIV VEN 5V/DIV VEN 5V/DIV PG 5V/DIV PG 5V/DIV 500µs/DIV 500µs/DIV FIGURE 20. START-UP AT 4A LOAD (PFM) FIGURE 21. SHUTDOWN AT 4A LOAD (PFM) Submit Document Feedback 10 FN8359.7 December 4, 2015 ISL78233, ISL78234 Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 5V, EN = VIN, SYNC = VIN, L = 1.0µH, C1 = 22µF, C2 = 2 x 22µF, IOUT = 0A to 4A. (Continued) PHASE 1V/DIV PHASE 1V/DIV 10ns/DIV 10ns/DIV FIGURE 22. JITTER AT NO LOAD PWM (1MHz) FIGURE 23. JITTER AT FULL LOAD PWM (1MHz) PHASE 5V/DIV PHASE 5V/DIV VOUT RIPPLE 20mV/DIV VOUT RIPPLE 20mV/DIV IL 1A/DIV IL 1A/DIV 500ns/DIV 20ms/DIV FIGURE 24. STEADY STATE AT NO LOAD PWM FIGURE 25. STEADY STATE AT NO LOAD PFM PHASE 5V/DIV VOUT RIPPLE 20mV/DIV IL 2A/DIV 500ns/DIV FIGURE 26. STEADY STATE AT 4A PWM Submit Document Feedback 11 FN8359.7 December 4, 2015 ISL78233, ISL78234 Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 5V, EN = VIN, SYNC = VIN, L = 1.0µH, C1 = 22µF, C2 = 2 x 22µF, IOUT = 0A to 4A. (Continued) VOUT RIPPLE 100mV/DIV VOUT RIPPLE 100mV/DIV ILOAD 2A/DIV ILOAD 2A/DIV 200µs/DIV 200µs/DIV FIGURE 27. LOAD TRANSIENTS (PWM) FIGURE 28. LOAD TRANSIENTS (PFM) PHASE 5V/DIV VOUT 1V/DIV IL 2A/DIV IL 5A/DIV VOUT 1V/DIV PG 5V/DIV PG 5V/DIV 4µs/DIV 40µs/DIV FIGURE 29. OUTPUT SHORT-CIRCUIT FIGURE 30. OVERCURRENT PROTECTION PHASE 5V/DIV VOUT 1V/DIV VOUT 2V/DIV IL 5A/DIV PG 2V/DIV PG 5V/DIV 20µs/DIV FIGURE 31. OVERVOLTAGE PROTECTION Submit Document Feedback 12 20ms/DIV FIGURE 32. OVER-TEMPERATURE PROTECTION FN8359.7 December 4, 2015 ISL78233, ISL78234 Theory of Operation with the 55pF and 100kΩ RC network. The maximum EAMP voltage output is precisely clamped to 2.5V. The ISL78233, ISL78234 are step-down switching regulators optimized for automotive battery powered applications. The regulator operates at a 2MHz default switching frequency for high efficiency and allow smaller form factor, when FS is connected to VIN. By connecting a resistor from FS to SGND, the operational frequency adjustable range is 500kHz to 4MHz. At light load, the regulator reduces the switching frequency, unless forced to the fixed frequency, to minimize the switching loss and to maximize the battery life. The quiescent current when the output is not loaded is typically only 45µA. The supply current is typically only 3.8µA when the regulator is shut down. VEAMP VCSA DUTY CYCLE IL PWM Control Scheme VOUT Pulling the SYNC pin HI (>0.8V) forces the converter into PWM mode, regardless of output current. The ISL78233, ISL78234 employs the current-mode Pulse Width Modulation (PWM) control scheme for fast transient response and pulse-by-pulse current limiting. Figure 3 on page 5 shows the Functional Block Diagram. The current loop consists of the oscillator, the PWM comparator, current-sensing circuit and the slope compensation for the current loop stability. The slope compensation is 440mV/Ts, which changes proportionally with frequency. The gain for the current-sensing circuit is typically 200mV/A. The control reference for the current loops comes from the Error Amplifier's (EAMP) output. FIGURE 33. PWM OPERATION WAVEFORMS Skip Mode The PWM operation is initialized by the clock from the oscillator. The P-channel MOSFET is turned on at the beginning of a PWM cycle and the current in the MOSFET starts to ramp up. When the sum of the current amplifier CSA and the slope compensation reaches the control reference of the current loop, the PWM comparator COMP sends a signal to the PWM logic to turn off the PFET and turn on the N-channel MOSFET. The NFET stays on until the end of the PWM cycle. Figure 33 shows the typical operating waveforms during the PWM operation. The dotted lines illustrate the sum of the slope compensation ramp and the current-sense amplifier’s CSA output. The output voltage is regulated by controlling the VEAMP voltage to the current loop. The bandgap circuit outputs a 0.6V reference voltage to the voltage loop. The feedback signal comes from the VFB pin. The soft-start block only affects the operation during the start-up and will be discussed separately. The error amplifier is a transconductance amplifier that converts the voltage error signal to a current output. The voltage loop is internally compensated PWM Pulling the SYNC pin LO (<0.4V) forces the converter into PFM mode. The ISL78233, ISL78234 enters a pulse-skipping mode at light load to minimize the switching loss by reducing the switching frequency. Figure 34 on page 13 illustrates the Skip mode operation. A zero-cross sensing circuit shown in Figure 3 on page 5 monitors the NFET current for zero crossing. When 16 consecutive cycles are detected, the regulator enters the Skip mode. During the sixteen detecting cycles, the current in the inductor is allowed to become negative. The counter is reset to zero when the current in any cycle does not cross zero. Once the Skip mode is entered, the pulse modulation starts being controlled by the Skip comparator shown in Figure 3 on page 5. Each pulse cycle is still synchronized by the PWM clock. The PFET is turned on at the clock's rising edge and turned off when the output is higher than 1.2% of the nominal regulation or when its current reaches the peak Skip current limit value. Then, the inductor current is discharging to 0A and stays at zero (the internal clock is disabled), and the output voltage reduces gradually due to the load current discharging the output capacitor. When the output voltage drops to the nominal voltage, the PFET will be turned on again at the rising edge of the internal clock as it repeats the previous operations. The regulator resumes normal PWM mode operation when the output voltage drops 1.2% below the nominal voltage. PFM PWM CLOCK 16 CYCLES PFM CURRENT LIMIT IL LOAD CURRENT 0 NOMINAL +1% VOUT NOMINAL NOMINAL -1.5% FIGURE 34. SKIP MODE OPERATION WAVEFORMS Submit Document Feedback 13 FN8359.7 December 4, 2015 ISL78233, ISL78234 Frequency Adjust The frequency of operation is fixed at 2MHz when FS is tied to VIN. Adjustable frequency ranges from 500kHz to 4MHz via a simple resistor connecting FS to SGND according to Equation 1: 220 10 3 R FS k = ------------------------------ – 14 f OSC kHz (EQ. 1) The ISL78233, ISL78234 also has frequency synchronization capability by simply connecting the SYNC pin to an external square pulse waveform. The frequency synchronization feature will synchronize the positive edge trigger and its switching frequency up to 4MHz. The minimum external SYNC frequency is half of the free running frequency (either the default frequency or determined by the FS resistor). Overcurrent Protection The overcurrent protection is realized by monitoring the CSA output with the OCP comparator, as shown in Figure 3 on page 5. The current sensing circuit has a gain of 200mV/A, from the P-FET current to the CSA output. When the CSA output reaches the threshold, the OCP comparator is tripled to turn off the PFET immediately. The overcurrent function protects the switching converter from a shorted output by monitoring the current flowing through the upper MOSFET. Upon detection of an overcurrent condition, the upper MOSFET will be immediately turned off and will not be turned on again until the next switching cycle. Upon detection of the initial overcurrent condition, the overcurrent fault counter is set to 1. If, on the subsequent cycle, another overcurrent condition is detected, the OC fault counter will be incremented. If there are 17 sequential OC fault detections, the regulator will be shut down under an overcurrent fault condition. An overcurrent fault condition will result in the regulator attempting to restart in a hiccup mode within the delay of eight soft-start periods. At the end of the 8th soft-start wait period, the fault counters are reset and soft-start is attempted again. If the overcurrent condition goes away during the delay of 8 soft-start periods, the output will resume back into regulation point after hiccup mode expires. Negative Current Protection Similar to overcurrent, the negative current protection is realized by monitoring the current across the low-side NFET, as shown in Figure 3 on page 5. When the valley point of the inductor current reaches -3A for 4 consecutive cycles, both PFET and NFET are off. The 100Ω in parallel to the NFET will activate discharging the output into regulation. The control will begin to switch when output is within regulation. The regulator will be in PFM for 20µs before switching to PWM if necessary. PG PG is an open-drain output of a window comparator that continuously monitors the buck regulator output voltage. PG is actively held low when EN is low and during the buck regulator soft-start period. After 1ms delay of the soft-start period, PG becomes high impedance as long as the output voltage is within nominal regulation voltage set by VFB. When VFB drops 15% below or raises 0.8V above the nominal regulation voltage, the ISL78233, ISL78234 pulls PG low. Any fault condition forces PG low until the Submit Document Feedback 14 fault condition is cleared by attempts to soft-start. For logic level output voltages, connect an external pull-up resistor, R1, between PG and VIN. A 100kΩ resistor works well in most applications. UVLO When the input voltage is below the Undervoltage Lockout (UVLO) threshold, the regulator is disabled. Soft Start-Up The soft start-up reduces the inrush current during the start-up. The soft-start block outputs a ramp reference to the input of the error amplifier. This voltage ramp limits the inductor current as well as the output voltage speed, so that the output voltage rises in a controlled fashion. When VFB is less than 0.1V at the beginning of the soft-start, the switching frequency is reduced to 200kHz so that the output can start-up smoothly at light load condition. During soft-start, the IC operates in the Skip mode to support prebiased output condition. Tie SS to SGND for internal soft-start is approximately 1ms. Connect a capacitor from SS to SGND to adjust the soft-start time. This capacitor, along with an internal 2.1µA current source sets the soft-start interval of the converter, tSS as shown by Equation 2. C SS F = 3.1 t SS s (EQ. 2) CSS must be less than 33nF to insure proper soft-start reset after fault condition. Enable The Enable (EN) input allows the user to control the turning on or off of the regulator for purposes such as power-up sequencing. When the regulator is enabled, there is typically a 600µs delay for waking up the bandgap reference and then the soft start-up begins. Discharge Mode (Soft-Stop) When a transition to shutdown mode occurs or the VIN UVLO is set, the outputs discharge to GND through an internal 100Ω switch. Power MOSFETs The power MOSFETs are optimized for best efficiency. The ON-resistance for the PFET is typically 35mΩ and the ON-resistance for the NFET is typically 11mΩ. 100% Duty Cycle The ISL78233, ISL78234 features 100% duty cycle operation to maximize the battery life. When the battery voltage drops to a level that the ISL78233, ISL78234 can no longer maintain the regulation at the output, the regulator completely turns on the P-FET. The maximum dropout voltage under the 100% duty-cycle operation is the product of the load current and the ON-resistance of the PFET. FN8359.7 December 4, 2015 ISL78233, ISL78234 Thermal Shutdown Input Capacitor Selection The ISL78233, ISL78234 has built-in thermal protection. When the internal temperature reaches +150°C, the regulator is completely shut down. As the temperature drops to +125°C, the ISL78233, ISL78234 resumes operation by stepping through the soft-start. The main functions for the input capacitor are to provide decoupling of the parasitic inductance and to provide a filtering function to prevent the switching current flowing back to the battery rail. At least two 22µF X5R or X7R ceramic capacitors are a good starting point for the input capacitor selection. Applications Information Loop Compensation Design Output Inductor and Capacitor Selection To consider steady state and transient operations, the ISL78233, ISL78234 typically uses a 1.0µH output inductor. The higher or lower inductor value can be used to optimize the total converter system performance. For example, for higher output voltage 3.3V application, in order to decrease the inductor current ripple and output voltage ripple, the output inductor value can be increased. It is recommended to set the ripple inductor current to approximately 30% of the maximum output current for optimized performance. The inductor ripple current can be expressed as shown in Equation 3: VO V O 1 – --------- V IN I = --------------------------------------L fS (EQ. 3) In Table 2, the minimum output capacitor value is given for the different output voltages to make sure that the whole converter system is stable. Additional output capacitance should be added for better performance in applications where high load transient or low output ripple is required. It is recommended to check the system level performance along with the simulation model. Output Voltage Selection The output voltage of the regulator can be programmed via an external resistor divider that is used to scale the output voltage relative to the internal reference voltage, and feed it back to the inverting input of the error amplifier (see Figure 2 on page 4). The output voltage programming resistor, R2, will depend on the value chosen for the feedback resistor and the desired output voltage of the regulator. The value for the feedback resistor, R3, is typically between 10kΩ and 100kΩ, as shown in Equation 4. VO R 2 = R 3 ------------ – 1 VFB (EQ. 4) If the output voltage desired is 0.6V, then R3 is left unpopulated and R2 is shorted. There is a leakage current from VIN to PHASE. It is recommended to preload the output with 10µA minimum. For better performance, add 15pF in parallel with R2 (200kΩ). Check loop analysis before use in application. 15 ^ Vin ILd^ ^ iL LP RLP ^ vo Vin d^ 1:D + Rc RT GAIN (VLOOP (S(fi)) The ISL78233, ISL78234 uses an internal compensation network and the output capacitor value is dependent on the output voltage. The recommended ceramic capacitor is X5R or X7R. The recommended X5R or X7R minimum output capacitor values are shown in Table 2 on page 4. + ^ i in The inductor’s saturation current rating needs to be at least larger than the peak current. The ISL78233, ISL78234 protects the typical peak current 4.9A/6.7A. The saturation current needs to be over 7A for maximum output current application. Submit Document Feedback When COMP is not connected to VDD, the COMP pin is active for external loop compensation. The ISL78233, ISL78234 uses constant frequency peak current mode control architecture to achieve a fast loop transient response. An accurate current-sensing pilot device in parallel with the upper MOSFET is used for peak current control signal and overcurrent protection. The inductor is not considered as a state variable since its peak current is constant, and the system becomes a single order system. It is much easier to design a type II compensator to stabilize the loop than to implement voltage mode control. Peak current mode control has an inherent input voltage feed-forward function to achieve good line regulation. Figure 35 shows the small signal model of the synchronous buck regulator. Ro Co T i(S) d^ K Fm + Tv (S) He(S) v^comp -Av(S) FIGURE 35. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK REGULATOR Vo R2 C3 VFB R3 VREF GM VCOMP + R6 C7 C6 FIGURE 36. TYPE II COMPENSATOR FN8359.7 December 4, 2015 ISL78233, ISL78234 Figure 36 shows the type II compensator and its transfer function is expressed as Equation 5: S S 1 + ------------ 1 + ------------- GM R 3 cz2 cz1 v̂ comp A v S = ----------------- = -------------------------------------------------------- -------------------------------------------------------------- C6 + C7 R2 + R3 S S v̂ FB S 1 + ------------- 1 + ------------- cp1 cp2 (EQ. 5) Where, R2 + R3 C6 + C7 1 1 cz1 = --------------- , cz2 = --------------- cp1 = ----------------------- cp2 = ----------------------R6 C6 C7 C3 R2 R3 R6 C6 R2 C3 It is also acceptable to use the closest standard values for C6 and C7. There is approximately 3pF parasitic capacitance from VCOMP to GND; Therefore, C7 is optional. Use C6 = 150pF and C7 = OPEN. 1 C 3 = ------------------------------------------------ = 16pF 100kHz 200k (EQ. 12) Use C3 = 15pF. Note that C3 may increase the loop bandwidth from previous estimated value. Figure 37 shows the simulated voltage loop gain. It is shown that it has a 150kHz loop bandwidth with a 42° phase margin and 10dB gain margin. It may be more desirable to achieve an increased phase margin. This can be accomplished by lowering R6 by 20% to 30%. 60 Compensator design goal: The compensator design procedure is as follows: The loop gain at crossover frequency of fc has a unity gain. Therefore, the compensator resistance R6 is determined by Equation 6. Ro Co Vo Co Rc Co 1 C 6 = --------------- = --------------- ,C 7 = max (--------------,----------------) R6 Io R6 R 6 f s R 6 (EQ. 7) Put one compensator pole at zero frequency to achieve high DC gain, and put another compensator pole at either ESR zero frequency or half switching frequency, whichever is lower in Equation 7. An optional zero can boost the phase margin. CZ2 is a zero due to R2 and C3 Put compensator zero 2 to 5 times fc : 1 C 3 = ---------------f c R 2 15 0 -30 100 (EQ. 6) Where GM is the sum of the transconductance, gm, of the voltage error amplifier in each phase. Compensator capacitor C6 is then given by Equation 7. 30 -15 1k 10k f (fi) 1k 10k f (fi) 100k 1M 180 150 PHASE (VLOOP (S(fi)) 2f c V o C o R t 3 R 6 = ---------------------------------- = 17.45 10 f c V o C o GM V FB GAIN (VLOOP (S(fi)) 45 High DC gain Choose Loop bandwidth fc less than 100kHz Gain margin: >10dB Phase margin: >40° 120 90 60 30 0 100 100k 1M FIGURE 37. SIMULATED LOOP GAIN (EQ. 8) Example: VIN = 5V, VO = 1.8V, IO = 4A, FS = 1MHz, R2 = 200kΩ, R3 = 100kΩ, Co = 2x22µF/3mΩ, L = 1µH, fc = 100kHz, then compensator resistance R6: 3 R 6 = 17.45 10 100kHz 1.8V 44F = 138k (EQ. 9) It is acceptable to use 137kΩas theclosest standard value for R6. 1.8V 44 F C 6 = -------------------------------- = 144pF 4A 137k (EQ. 10) 3m 44F 1 C 7 = max (---------------------------------,------------------------------------------------) = (1pF,2.3pF) 137k 1MHz 137k (EQ. 11) Submit Document Feedback 16 FN8359.7 December 4, 2015 ISL78233, ISL78234 PCB Layout Recommendation The PCB layout is a very important converter design step to make sure the designed converter works well. For the ISL78233, ISL78234 the power loop is composed of the output inductor L’s, the output capacitor CO, the PHASE pins and the PGND pin. It is necessary to make the power loop as small as possible and the connecting traces among them should be direct, short and wide. The switching node of the converter, the PHASE pins and the traces connected to the node are very noisy, so keep the voltage feedback trace away from these noisy traces. The input capacitor should be placed as close as possible to the VIN pin. The ground of the input and output capacitors should be connected as close as possible. The heat of the IC is mainly dissipated through the thermal pad. Maximizing the copper area connected to the thermal pad is preferable. In addition, a solid ground plane is helpful for better EMI performance. Refer to TB389 for via placement on the copper area of the PCB underneath the thermal pad for optimum thermal performance. Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE REVISION December 4, 2015 FN8359.7 Added a new User Guide to Related Literature section on page 1. Added EVAL2 part numbers to the ordering information table on page 3. Added Table 1 on page 3. CHANGE November 10, 2015 FN8359.6 Added 5x5mmWFQFN information throughout datasheet. Updated Note 1 on page 3 from “Add “-T*” suffix for tape and reel.” to “Add “-T” suffix for 6k unit or “-T7A” suffix for 250 unit tape and reel options.” In “PWM Control Scheme” on page 13 (last sentence) corrected a typo by changing “1.6V to “2.5V”. Table 2 on page 4: Updated L1 row. Updated the “PCB Layout Recommendation” section on page 17. Added POD L16.5x5D. April 23, 2015 FN8359.5 Updated the 4th Features bullet page 1 by changing value from “0.8%” to “-1.2%/1%”. April 23, 2014 FN8359.4 Updated electrical table, changed Phase minimum on-time MAX from 133ns to 100ns on page 7 Updated electrical table, modified test conditions for Error Amplifier trans-conductance and Power-good Output Low Voltage on page 7 Removed references to VOUT = 0.8V, and 0.9V Added typical curve for Phase minimum on-time vs VIN on page 9 Added description on synchronized control on page 14 February 24, 2014 FN8359.3 Updated ESD rating qual references from Jedec standard references to AEC-Q100 standard references on page 6 December 13, 2013 FN8359.2 Last Features bullet on page 1: changed from "Qualified for automotive application" to "AEC-Q100 qualified" October 16, 2013 FN8359.1 Initial Release. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support For additional products, see www.intersil.com/en/products.html Intersil Automotive Qualified products are manufactured, assembled and tested utilizing TS16949 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com Submit Document Feedback 17 FN8359.7 December 4, 2015 ISL78233, ISL78234 Package Outline Drawing L16.3x3D 16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 3/10 4X 1.50 3.00 A 12X 0.50 B 13 6 PIN 1 INDEX AREA 16 6 PIN #1 INDEX AREA 12 3.00 1 1.60 SQ 4 9 (4X) 0.15 8 0.10 M C A B 5 16X 0.40±0.10 TOP VIEW 4 16X 0.23 ±0.05 BOTTOM VIEW SEE DETAIL “X” 0.10 C C 0.75 ±0.05 0.08 C SIDE VIEW (12X 0.50) (2.80 TYP) ( 1.60) (16X 0.23) C 0 . 2 REF 5 0 . 02 NOM. 0 . 05 MAX. (16X 0.60) TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to ASME Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension applies to the metallized terminal and is measured between 0.15mm and 0.25mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be 7. JEDEC reference drawing: MO-220 WEED. either a mold or mark feature. Submit Document Feedback 18 FN8359.7 December 4, 2015 ISL78233, ISL78234 Package Outline Drawing L16.5x5D 16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (PUNCH QFN WITH WETTABLE FLANK) Rev 2, 5/14 A 0.10 C A (2X) 5.00 4.75 16 0.10 C B (2X) 0.10 M C A B 2.8 0.60 MAX. (4X) PIN 1 ID R0.20 16 0.60 MAX. (4X) 0.45 0.10 M C B A 1 5 0.50 DIA 1 5.00 2 2 2.8 4.75 3 3 (0.70) CC (2X) 0.10 C B (2X) 0.40±0.10 0.15±0.10 0.10 C A B TOP VIEW 0.08 C // 0.10 C 0.85 ± 0.05 TERMINAL TIP 4 0.30±0.05 0.10 M C A B 0.05 M C (0.70) 0.80 5 BOTTOM VIEW + 0.04 0.01 - 0.01 0.65 ± 0.05 (0.20) 0.20 0.10 4 SEE DETAIL “A” (0.01) SECTION “C-C” SCALE: NONE 12° MAX 4 DETAIL “A” (DIMPLE DEPTH) SCALE: NONE SEATING PLANE C SIDE VIEW NOTES: 12X (0.80) 1. Dimensions are in millimeters. Dimensions in ( ) are for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. (2.80) SQ 3. Unless otherwise specified, tolerance: Decimal ± 0.05 (4.80) SQ 4. Dimension applies to the plated terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 16X (0.30) 16X (0.60) TYPICAL RECOMMENDED LAND PATTERN Submit Document Feedback 19 5. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 6. Reference document: JEDEC M0220. FN8359.7 December 4, 2015