AN11106 Pin FMEA for AHC/AHCT family Rev. 1 — 4 November 2011 Application note Document information Info Content Keywords FMEA, AHC, AHCT, CMOS Abstract This application note provides a Failure Modes and Effects Analysis (FMEA) for NXP Semiconductors AHC/AHCT family during typical failure situations. AN11106 NXP Semiconductors Pin FMEA for AHC/AHCT family Revision history Rev Date Description v.1 20111104 initial version Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] AN11106 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 4 November 2011 © NXP B.V. 2011. All rights reserved. 2 of 7 AN11106 NXP Semiconductors Pin FMEA for AHC/AHCT family 1. Introduction The Advanced High-Speed CMOS (AHC and AHCT) family of logic devices from NXP Semiconductors, offers many of the same functions found in the High-Speed CMOS (HC and HCT) family. However, it has higher performance and lower power consumption than the HC/HCT while maintaining competitive prices. In addition, NXP Semiconductors guarantees AHC/AHCT products to operate over an extended temperature range of 40 C to +125 C. The increase in product specification is at no extra cost to the customer. The AHC/AHCT family of products is ideally suited for notebooks, telecom infrastructure, and portable applications. The capability to operate at both 5 V and 3.3 V, further extends its integration into new designs. The dual voltage facilitates the migration of existing designs to low-voltage systems and establishes it as a truly mixed-voltage product. The AHC/AHCT family includes gates, octals, MSI, and 16 bit-wide devices. It is both functionally and pin-for-pin compatible with the HC/HCT family of products. 2. Pin FMEA This chapter provides an FMEA (Failure Mode and Effect Analysis) for typical failure situations. The failure situations are when the pins of a type in the AHC/AHCT family are shorted to supply voltages VCC, GND or neighboring pins, or simply left open. The individual failures are classified in accordance with their corresponding effects on the AHC/AHCT device and its functionality (see Table 1). Table 1. Classification of failure effects Class Failure effect A damage to device affects application functionality B no damage to device can affect application functionality C no damage to device no affect to application functionality Table 2. AN11106 Application note FMEA matrix for pin short-circuit to VCC Pin Class Remarks Input B normal operating condition, no damage, no leakage, can affect functionality Output C if output defined HIGH, no damage, no leakage, no output level change Output A if output defined LOW, short-circuits and high currents can damage device, output level changes GND B short-circuits and high currents can damage device, affects functionality All information provided in this document is subject to legal disclaimers. Rev. 1 — 4 November 2011 © NXP B.V. 2011. All rights reserved. 3 of 7 AN11106 NXP Semiconductors Pin FMEA for AHC/AHCT family Table 3. FMEA matrix for pin short-circuit to GND Pin Class Remarks Input B normal operating condition, no damage, no leakage; can affect functionality Output C if output defined LOW, no damage, no leakage no output level change Output A if output defined HIGH, short-circuits and high currents can damage device, output level changes VCC B no damage, affects functionality Table 4. FMEA matrix for pin left open Pin Class Remarks Input B undefined operating condition, no damage, increases leakage, can affect functionality Output C normal operating condition, no damage, no leakage GND B undefined operating condition, no damage, increases leakage, affects functionality VCC B undefined operating condition, no damage, increases leakage (only for I/O types), affects functionality Table 5. FMEA matrix for pin short-circuits between neighboring pins Pin Class Remarks Input to input C if inputs have same voltage levels: no damage, no leakage B if inputs have different voltage levels: leakage increases, affects functionality A if input and output have different voltage levels, can cause high current and can damage device, affects functionality C if input and output have same voltage levels, no damage, no leakage Input to GND - see Table 3 Input to VCC - see Table 2 Output to output C if outputs have same voltage levels, no damage, no leakage A if outputs have different voltage levels, can cause high current and can damage device, affects functionality Input to output AN11106 Application note Output to input - same effect as ‘input to output’ condition Output to GND - see Table 3 Output to VCC - see Table 2 GND to VCC - not applicable, these pins are not neighbors All information provided in this document is subject to legal disclaimers. Rev. 1 — 4 November 2011 © NXP B.V. 2011. All rights reserved. 4 of 7 AN11106 NXP Semiconductors Pin FMEA for AHC/AHCT family 3. Abbreviations Table 6. AN11106 Application note Abbreviations Acronym Description AHCT Advanced High-Speed CMOS TTL CMOS Complementary Metal-Oxide Semiconductor FMEA Failure Modes and Effects Analysis LSTTL Low-power Schottky TTL TTL Transistor-Transistor Logic All information provided in this document is subject to legal disclaimers. Rev. 1 — 4 November 2011 © NXP B.V. 2011. All rights reserved. 5 of 7 AN11106 NXP Semiconductors Pin FMEA for AHC/AHCT family 4. Legal information 4.1 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 4.2 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product AN11106 Application note design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 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Notwithstanding any damages that customer might incur for any reason whatsoever (including without limitation, all damages referenced above and all direct or general damages), the entire liability of NXP Semiconductors, its affiliates and their suppliers and customer’s exclusive remedy for all of the foregoing shall be limited to actual damages incurred by customer based on reasonable reliance up to the greater of the amount actually paid by customer for the product or five dollars (US$5.00). The foregoing limitations, exclusions and disclaimers shall apply to the maximum extent permitted by applicable law, even if any remedy fails of its essential purpose. 4.3 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 1 — 4 November 2011 © NXP B.V. 2011. All rights reserved. 6 of 7 AN11106 NXP Semiconductors Pin FMEA for AHC/AHCT family 5. Contents 1 2 3 4 4.1 4.2 4.3 5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin FMEA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . Legal information. . . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 5 6 6 6 6 7 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 4 November 2011 Document identifier: AN11106