INTERSIL HFA1113ML/883

HFA1113/883
TM
Output Limiting, Ultra High Speed
Programmable Gain, Buffer Amplifier
July 1994
Features
Description
• This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
The HFA1113/883 is a closed loop buffer featuring a high
degree of gain accuracy, wide bandwidth, low distortion, and
programmable output limiting. This buffer is the ideal choice
for high frequency applications requiring output limiting,
especially those needing ultra fast overdrive recovery times.
The output limiting function allows the designer to set the
maximum positive and negative output levels, thereby protecting later stages from damage or input saturation. The
sub-nanosecond overdrive recovery time quickly returns the
amplifier to linear operation following an overdrive condition.
• User Programmable Output Voltage Limiting
• User Programmable For Closed-Loop Gains of +1, -1
or +2 Without Use of External Resistors
• Low Differential Gain and Phase . . . . .0.02%/0.04 Deg.
• Low Distortion (HD3, 30MHz) . . . . . . . . . . -73dBc (Typ)
• Wide -3dB Bandwidth . . . . . . . . . . . . . . . 850MHz (Typ)
• Very High Slew Rate . . . . . . . . . . . . . . . 2400V/µs (Typ)
• Fast Settling (0.1%) . . . . . . . . . . . . . . . . . . . . 13ns (Typ)
• Excellent Gain Flatness (to 100MHz) . . . . 0.07dB (Typ)
• Excellent Gain Accuracy . . . . . . . . . . . . . . 0.99V/V (Typ)
• High Output Current . . . . . . . . . . . . . . . . . . 60mA (Typ)
• Fast Overdrive Recovery . . . . . . . . . . . . . . . <1ns (Typ)
Applications
Component and composite video systems will also benefit
from this buffer’s performance, as indicated by the excellent
gain flatness, and 0.02%/0.04 Deg. Differential Gain/Phase
specifications (R L = 150Ω).
A unique feature of the pinout allows the user to select a
voltage gain of +1, -1, or +2, without the use of any external
components, as described in the “Design Information” section. Compatibility with existing op amp pinouts provides
flexibility to upgrade low gain amplifiers, while decreasing
component count. Unlike most buffers, the standard pinout
provides an upgrade path should a higher closed loop gain
be needed at a future date.
This amplifier is available without output limiting as the
HFA1112/883. For applications requiring a standard buffer
pinout, please refer to the HFA1110/883 datasheet.
• Video Switching and Routing
• Pulse and Video Amplifiers
• Wideband Amplifiers
Ordering Information
• RF/IF Signal Processing
• Flash A/D Driver
PART NUMBER
• Medical Imaging Systems
HFA1113MJ/883
HFA1113ML/883
TEMPERATURE
RANGE
-55
oC
-55
oC
PACKAGE
to
+125oC
8 Lead CerDIP
to
+125oC
20 Lead Ceramic LCC
Pinouts
8
VH
7
V+
NC 4
6
OUT
-IN 5
5
VL
300
-IN
2
+IN
3
V-
4
-
+
NC
NC
NC
300
1
NC
NC
NC
HFA1113/883
(CLCC)
TOP VIEW
HFA1113/883
(CERDIP)
TOP VIEW
3
2
1 20 19
18 VH
300
300
17 V+
-
NC 6
16 NC
15 OUT
+
+IN 7
14 NC
NC 8
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
189
NC
NC
VL
V-
NC
9 10 11 12 13
Spec Number
511106-883
FN3618.1
Specifications HFA1113/883
Absolute Maximum Ratings
Thermal Information
Voltage Between V+ and V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V
Voltage at Either Input Terminal . . . . . . . . . . . . . . . . . . . . . . V+ to VVoltage at VH or VL Terminal . . . . . . . . . . . . . (V+) + 2V to (V-) - 2V
Output Current (50% Duty Cycle) . . . . . . . . . . . . . . . . . . . . . . . . ±55mA
Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
ESD Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . < 2000V
Storage Temperature Range . . . . . . . . . . . . . . -65oC ≤ TA ≤ +150oC
Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300oC
θJC
Thermal Resistance
θJA
CerDIP Package . . . . . . . . . . . . . . . . . 115oC/W
30oC/W
Ceramic LCC Package . . . . . . . . . . . . 75oC/W
23oC/W
Maximum Package Power Dissipation at +75oC
CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.87W
Ceramic LCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.33W
Package Power Dissipation Derating Factor above +75oC
CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.7mW/oC
Ceramic LCC Package . . . . . . . . . . . . . . . . . . . . . . . . 13.3mW/oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Supply Voltage (±VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5V
Operating Temperature Range. . . . . . . . . . . . .-55oC ≤ TA ≤ +125oC
RL Š≥ 50Ω
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Tested at: V SUPPLY = ±5V, RSOURCE = 0Ω, RL = 100Ω, VOUT = 0V, Unless Otherwise Specified.
PARAMETERS
Output Offset Voltage
Power Supply
Rejection Ratio
SYMBOL
VOS
PSRRP
PSRRN
Non-Inverting Input (+IN)
Current
IBSP
+IN Common
Mode Rejection
CMSIBP
+IN Resistance
+RIN
CONDITIONS
GROUP A
SUBGROUPS
VCM = 0V
∆VSUPPLY = ±1.25V,
V+ = 6.25V, V- = -5V,
V+ = 3.75V, V- = -5V
∆VSUPPLY = ±1.25V,
V+ = 5V, V- = -6.25V,
V+ = 5V, V- = -3.75V
∆VCM = ±2V,
V+ = 3V, V- = -7V,
V+ = 7V, V- = -3V
Note 1
Gain (VOUT = 2VP-P)
Gain (VOUT = 4VP-P)
Output Voltage
Swing
AVP1
AVM1
AVP2
VOP100
VON100
Output Voltage
Swing
VOP50
VON50
AV = +1,
VIN = -1V to +1V
AV = -1,
VIN = -1V to +1V
AV = +2,
VIN = -1V to +1V
AV = -1
RL = 100Ω
+25 C
-25
25
mV
-40
40
mV
1
+25oC
39
-
dB
2, 3
+125oC, -55oC
35
-
dB
1
+25oC
39
-
dB
35
-
dB
AV = -1
RL = 100Ω
AV = -1
RL = 50Ω
AV = -1
RL = 50Ω
+125
oC,
-55oC
1
+25oC
-40
40
µA
2, 3
+125oC, -55oC
-65
65
µA
1
+25oC
-
40
µA/V
2, 3
+125oC, -55oC
-
50
µA/V
1
+25oC
25
-
kΩ
oC,
-55oC
20
-
kΩ
1
+25oC
0.980
1.020
V/V
2, 3
+125oC, -55oC
0.975
1.025
V/V
1
+25oC
0.980
1.020
V/V
+125
o
o
2, 3
+125 C, -55 C
0.975
1.025
V/V
1
+25oC
1.960
2.040
V/V
1.950
2.050
V/V
3
-
V
2.5
-
V
1
VIN = 2.7V
UNITS
+125oC, -55oC
2, 3
VIN = -3.2V
MAX
1
2, 3
Gain (VOUT = 2VP-P)
o
MIN
2, 3
2, 3
VCM = 0V
LIMITS
TEMPERATURE
2, 3
+125
oC,
-55oC
+25oC
+125oC,
-55oC
VIN = +3.2V
1
+25oC
-
-3
V
VIN = +2.7V
2, 3
+125oC, -55oC
-
-2.5
V
VIN = -2.7V
1, 2
+25oC, +125oC
2.5
-
V
3
-55oC
1.5
-
V
1, 2
+25oC, +125oC
-
-2.5
V
3
-55oC
-
-1.5
V
VIN = 2.25V
VIN = +2.7V
VIN =+2.25V
Spec Number
190
511106-883
Specifications HFA1113/883
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
Device Tested at: V SUPPLY = ±5V, RSOURCE = 0Ω, RL = 100Ω, VOUT = 0V, Unless Otherwise Specified.
PARAMETERS
Output Current
SYMBOL
+IOUT
MAX
UNITS
50
-
mA
RL = 100Ω
VHCLMP
VLCLMP
VH or VL Input Current
MIN
+25oC, +125oC
RL = 100Ω
ICC
IEE
Limiting Accuracy
TEMPERATURE
1, 2
Note 2
Note 2
-IOUT
Quiescent Power
Supply Current
CONDITIONS
VHBIAS
VLBIAS
LIMITS
GROUP A
SUBGROUPS
AV = -1, VIN = -1.6V,
VH = 1V
AV = -1, VIN = +1.6V,
VL = -1V
VH = 1V
VL = -1V
o
3
-55 C
30
-
mA
1, 2
+25oC, +125oC
-
-50
mA
3
-55oC
-
-30
mA
1
+25oC
14
26
mA
2, 3
+125oC, -55oC
-
33
mA
1
+25oC
-26
-14
mA
2, 3
+125oC, -55oC
-33
-
mA
1
+25oC
-150
150
mV
2, 3
+125oC, -55oC
-200
200
mV
1
+25oC
-150
150
mV
o
o
2, 3
+125 C, -55 C
-200
200
mV
1
+25oC
-
200
µA
2, 3
+125 C, -55 C
-
300
µA
1
+25oC
-200
-
µA
-300
-
µA
o
2, 3
+125
oC,
o
-55oC
NOTES:
1. Guaranteed from +IN Common Mode Rejection Test, by: +R IN = 1/CMSIBP .
2. Guaranteed from VOUT Test with RL = 50Ω, by: IOUT = VOUT /50Ω.
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
Table 2 Intentionally Left Blank.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Characterized at: VSUPPLY = ±5V, RL = 100Ω, Unless Otherwise Specified.
LIMITS
PARAMETERS
-3dB Bandwidth
Gain Flatness
Slew Rate
SYMBOL
CONDITIONS
BW(-1)
AV = -1, VOUT = 200mV P-P
BW(+1)
AV = +1, VOUT = 200mVP-P
BW(+2)
AV = +2, VOUT = 200mVP-P
NOTES
TEMPERATURE
MIN
MAX
UNITS
1
+25oC
450
-
MHz
o
500
-
MHz
o
1
+25 C
1
+25 C
350
-
MHz
-
±0.04
dB
GF30
AV = +2, f ≤ 30MHz,
VOUT = 200mV P-P
1
+25oC
GF50
AV = +2, f ≤ 50MHz,
VOUT = 200mV P-P
1
+25oC
-
±0.08
dB
GF100
AV = +2, f ≤ 100MHz,
VOUT = 200mV P-P
1
+25oC
-
±0.22
dB
+SR(-1)
AV = -1, VOUT = 5V P-P
1, 2
+25oC
1500
-
V/µs
-SR(-1)
AV = -1, VOUT = 5VP-P
1, 2
+25oC
1800
-
V/µs
+SR(+1)
AV = +1, VOUT = 5VP-P
900
-
V/µs
1, 2
o
+25 C
-SR(+1)
AV = +1, VOUT = 5VP-P
1, 2
+25 C
800
-
V/µs
+SR(+2)
AV = +2, VOUT = 5VP-P
1, 2
+25oC
1200
-
V/µs
-SR(+2)
AV = +2, VOUT = 5VP-P
1, 2
+25oC
1100
-
V/µs
o
Spec Number
191
511106-883
Specifications HFA1113/883
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
Device Characterized at: VSUPPLY = ±5V, RL = 100Ω, Unless Otherwise Specified.
LIMITS
PARAMETERS
SYMBOL
Rise and Fall Time
Overshoot
Settling Time
2nd Harmonic Distortion
3rd Harmonic Distortion
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
UNITS
TR(-1)
AV = -1, VOUT = 0.5VP-P
1, 2
+25 C
-
750
ps
TF(-1)
AV = -1, VOUT = 0.5VP-P
1, 2
+25oC
-
800
ps
TR(+1)
AV = +1, VOUT = 0.5VP-P
o
-
750
ps
TF (+1)
AV = +1, VOUT = 0.5VP-P
o
-
750
ps
TR(+2)
AV = +2, VOUT = 0.5VP-P
1, 2
o
+25 C
-
1000
ps
TF (+2)
AV = +2, VOUT = 0.5VP-P
1, 2
+25oC
-
1000
ps
+OS(-1)
AV = -1, VOUT = 0.5VP-P
o
-
30
%
-OS(-1)
AV = -1, VOUT = 0.5VP-P
o
-
25
%
+OS(+1)
AV = +1, VOUT = 0.5VP-P
1, 3
o
+25 C
-
65
%
-OS(+1)
AV = +1, VOUT = 0.5VP-P
1, 3
+25oC
-
60
%
+OS(+2)
AV = +2, VOUT = 0.5VP-P
-OS(+2)
AV = +2, VOUT = 0.5VP-P
TS(0.1)
AV = +2, to 0.1%, VOUT = 2V to
0V
1
TS(0.05)
AV = +2, to 0.05%,
VOUT = 2V to 0V
HD2(30)
1, 2
1, 2
1, 3
1, 3
o
+25 C
+25 C
+25 C
+25 C
o
1, 3
+25 C
-
20
%
1, 3
+25oC
-
20
%
+25 C
-
20
ns
1
+25oC
-
33
ns
AV = +2, f = 30MHz,
VOUT = 2VP-P
1
+25oC
-
-45
dBc
HD2(50)
AV = +2, f = 50MHz,
VOUT = 2VP-P
1
+25oC
-
-40
dBc
HD2(100)
AV = +2, f = 100MHz,
VOUT = 2VP-P
1
+25oC
-
-35
dBc
HD3(30)
AV = +2, f = 30MHz,
VOUT = 2VP-P
1
+25oC
-
-65
dBc
HD3(50)
AV = +2, f = 50MHz,
VOUT = 2VP-P
1
+25oC
-
-55
dBc
HD3(100)
AV = +2, f = 100MHz,
VOUT = 2VP-P
1
+25oC
-
-45
dBc
o
NOTES:
1. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These parameters are lab characterized upon initial design release, or upon design changes. These parameters are guaranteed by characterization
based upon data from multiple production runs which reflect lot-to-lot and within lot variation.
2. Measured between 10% and 90% points.
3. For 200ps input transition times. Overshoot decreases as input transition times increase, especially for A V = +1. Please refer to
Performance Curves.
TABLE 4. ELECTRICAL TEST REQUIREMENTS
MIL-STD-883 TEST REQUIREMENTS
SUBGROUPS (SEE TABLE 1)
Interim Electrical Parameters (Pre Burn-In)
1
Final Electrical Test Parameters
1 (Note 1), 2, 3
Group A Test Requirements
1, 2, 3
Groups C and D Endpoints
1
NOTE:
1. PDA applies to Subgroup 1 only.
Spec Number
192
511106-883
HFA1113/883
Die Characteristics
DIE DIMENSIONS:
63 x 44 x 19 mils ± 1 mils
1600 x 1130 x 483µm ± 25.4µm
METALLIZATION:
Type: Metal 1: AICu(2%)/TiW
Thickness: Metal 1: 8kÅ ± 0.4kÅ
Type: Metal 2: AICu(2%)
Thickness: Metal 2: 16kÅ ± 0.8kÅ
GLASSIVATION:
Type: Nitride
Thickness: 4kÅ ± 0.5kÅ
WORST CASE CURRENT DENSITY:
2.0 x 105 A/cm2 at 47.5mA
TRANSISTOR COUNT: 52
SUBSTRATE POTENTIAL (Powered Up): Floating (Recommend Connection to V-)
Metallization Mask Layout
HFA1113/883
NC
+IN
V-
VL
-IN
VH
NC
V+
OUT
Spec Number
193
511106-883
HFA1113/883
Test Circuit
(Applies to Table 1)
NC
K3
VL
0.1
V+
50
0.1
+
ICC
10
Vos =
0.1
0.1
NC
-VIN
2
2
1
+VIN
0.1
K1
510
5
-
2
1K
6
0.1
3
VY
x100
7
1
K2
+
-
470pF
510
VY
100
VOUT
DUT
+
8
100
100
4
50
100K (0.01%)
VZ
+IBIAS =
100K
K3
0.1
+
VZ
10
+
0.1
0.1
NC
HA-5177
NOTE:
K4
IEE
V-
0.1
VH
Terminal Numbers Refer to CerDIP Package
All Resistors = ±1% (Ω)
All Capacitors = ±10% (µF)
Unless Otherwise Noted
Chip Components Recommended
For AV = +1, K1 = Position 1, K2 = Position 1
For AV = +2, K1 = Position 1, K2 = Position 2, -VIN = 0V
For AV = -1, K1 = Position 1, K2 = Position 2, +VIN = 0V
Test Waveforms
SIMPLIFIED TEST CIRCUIT FOR LARGE AND SMALL SIGNAL PULSE RESPONSE (Applies to Table 3)
AV = +1 or +2 TEST CIRCUIT
AV = -1 TEST CIRCUIT
V+
3
+
2
-
VIN
RS
50Ω
V+
7
VOUT
6
4
50Ω
VIN
2
RS
50Ω
50Ω
RG
2
3 +
V-
7
VOUT
6
4
50Ω
V-
NOTE:
NOTE:
VS = ±5V, RG = 0Ω for AV = +2, R G = ∞ for AV = +1
RF = Internal, RS = 50Ω
RL = 100Ω For Small and Large Signals
Terminal Numbers Refer to CerDIP Package
VS = ±5V, AV = -1
RF = Internal
RS = 50Ω, RL = 100Ω For Small and Large Signals
Terminal Numbers Refer to CerDIP Package
LARGE SIGNAL WAVEFORM
SMALL SIGNAL WAVEFORM
VOUT
+2.5V
VOUT
90%
90%
+SR
-2.5V
2
50Ω
+2.5V
+250mV
-SR
10%
10%
90%
90%
TF , -OS
TR , +OS
-2.5V
-250mV
10%
10%
Spec Number
194
+250mV
-250mV
511106-883
HFA1113/883
Burn-In Circuits
HFA1113MJ/883 CERAMIC DIP
1
300
8
-
7
D3
300
NC 2
+
3
D4
4
VD2
V+
C1
6
5
D1
R1
C2
NOTES:
R1 = 100Ω, ±5% (Per Socket)
C1 = C2 = 0.01µF (Per Socket) or 0.1µF (Per Row) Minimum
D1 = D2 = 1N4002 or Equivalent (Per Board)
D3 = D4 = 1N4002 or Equivalent (Per Socket)
V+ = +5.5V ±0.5V
V- = -5.5V ±0.5V
HFA1113ML/883 CERAMIC LCC
3
2
4
NC 5
300
300
18
D3
17
-
6
R1
1 20 19
V+
16
+
7
15
8
14
C1
D1
R2
9 10 11 12 13
D4
VD2
C2
NOTES:
R1 = 1kΩ, ±5% (Per Socket)
R2 = 100Ω, ±5% (Per Socket)
C1 = C2 = 0.01µF (Per Socket) or 0.1µF (Per Row) Minimum
D1 = D2 = 1N4002 or Equivalent (Per Board)
D3 = D4 = 1N4002 or Equivalent (Per Socket)
V+ = +5.5V ±0.5V
V- = -5.5V ±0.5V
Spec Number
195
511106-883
HFA1113/883
Ceramic Dual-In-Line Frit Seal Packages (CerDIP)
F8.3A
MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A)
8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
LEAD FINISH
c1
-D-
-A-
BASE
METAL
E
b1
M
M
(b)
-Bbbb S
C A-B S
SECTION A-A
D S
D
BASE
PLANE
Q
-C-
SEATING
PLANE
A
α
L
S1
eA
A A
b2
b
ccc M
C A-B S
e
D S
eA/2
INCHES
(c)
c
aaa M C A - B S D S
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.200
-
5.08
-
b
0.014
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
-
0.405
-
10.29
5
E
0.220
0.310
5.59
7.87
5
e
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
-
3.81 BSC
-
eA/2
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
MILLIMETERS
L
0.150 BSC
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
6
S1
0.005
-
0.13
-
7
α
90o
105o
90o
105o
-
aaa
-
0.015
-
0.38
-
bbb
-
0.030
-
0.76
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
ccc
-
0.010
-
0.25
-
M
-
0.0015
-
0.038
2, 3
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
8
8
8
Rev. 0 4/94
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
11. Materials: Compliant to MIL-I-38535.
Spec Number
196
511106-883
HFA1113/883
Ceramic Leadless Chip Carrier Packages (CLCC)
J20.A
MIL-STD-1835 CQCC1-N20 (C-2)
20 PAD LEADLESS CERAMIC CHIP CARRIER
0.010 S E H S
D
INCHES
D3
j x 45o
E3
B
E
0.010 S E F S
A
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.060
0.100
1.52
2.54
6, 7
A1
0.050
0.088
1.27
2.23
-
B
-
-
-
-
-
B1
0.022
0.028
0.56
0.71
2, 4
B2
h x 45 o
A1
PLANE 2
-E-
0.022
0.15
0.56
-
0.342
0.358
8.69
9.09
-
D1
0.200 BSC
5.08 BSC
-
D2
0.100 BSC
2.54 BSC
-
D3
-
0.358
-
9.09
2
E
0.342
0.358
8.69
9.09
-
E1
0.200 BSC
5.08 BSC
-
E2
0.100 BSC
2.54 BSC
-
h
j
e
L
-H-
L3
B3
E1
E2
0.358
0.050 BSC
0.015
-
-
9.09
2
1.27 BSC
0.38
0.040 REF
0.020 REF
-
2
1.02 REF
5
0.51 REF
5
0.045
0.055
1.14
1.40
-
L1
0.045
0.055
1.14
1.40
-
L2
0.075
0.095
1.91
2.41
-
L3
0.003
0.015
0.08
5
0.38
-
5
3
NE
5
5
3
N
20
20
3
Rev. 0 4/94
NOTES:
1. Metallized castellations shall be connected to plane 1 terminals
and extend toward plane 2 across at least two layers of ceramic
or completely across all of the ceramic layers to make electrical
connection with the optional plane 2 terminals.
L2
B2
2. Unless otherwise specified, a minimum clearance of 0.015 inch
(0.38mm) shall be maintained between all metallized features
(e.g., lid, castellations, terminals, thermal pads, etc.)
L1
D2
e1
-
L
ND
-F-
-
0.006
e1
B1
1.83 REF
D
e
0.007 M E F S H S
0.072 REF
B3
E3
PLANE 1
MILLIMETERS
3. Symbol “N” is the maximum number of terminals. Symbols “ND”
and “NE” are the number of terminals along the sides of length
“D” and “E”, respectively.
D1
4. The required plane 1 terminals and optional plane 2 terminals (if
used) shall be electrically connected.
5. The corner shape (square, notch, radius, etc.) may vary at the
manufacturer’s option, from that shown on the drawing.
6. Chip carriers shall be constructed of a minimum of two ceramic
layers.
7. Dimension “A” controls the overall package thickness. The maximum “A” dimension is package height before being solder dipped.
8. Dimensioning and tolerancing per ANSI Y14.5M-1982.
9. Controlling dimension: INCH.
10. Materials: Compliant to MIL-I-38535.
Spec Number
197
511106-883
HFA1113
TM
DESIGN INFORMATION
Output Limiting, Ultra High Speed
Programmable Gain Buffer Amplifier
February 2002
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as
application and design information only. No guarantee is implied.
Typical Performance Curves
VSUPPLY = ±5V, RL = 100Ω, TA = +25oC, Unless Otherwise Specified
SMALL SIGNAL PULSE RESPONSE
LARGE SIGNAL PULSE RESPONSE
200
2.0
AV = +2
1.5
100
1.0
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (mV)
AV = +2
150
50
0
-50
-100
-150
0.5
0
-0.5
-1.0
-1.5
-200
-2.0
5ns/DIV
5ns/DIV
SMALL SIGNAL PULSE RESPONSE
LARGE SIGNAL PULSE RESPONSE
2.0
200
AV = +1
1.5
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (mV)
150
100
50
0
-50
-100
AV = +1
1.0
0.5
0
-0.5
-1.0
-1.5
-150
-2.0
-200
5ns/DIV
5ns/DIV
SMALL SIGNAL PULSE RESPONSE
LARGE SIGNAL PULSE RESPONSE
2.0
200
AV = -1
1.5
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (mV)
150
100
50
0
-50
-100
AV = -1
1.0
0.5
0
-0.5
-1.0
-1.5
-150
-2.0
-200
5ns/DIV
5ns/DIV
Spec Number
198
511106-883
HFA1113
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as
application and design information only. No guarantee is implied.
Typical Performance Curves
VSUPPLY = ±5V, RL = 100Ω, TA = +25oC, Unless Otherwise Specified (Continued)
UNCLAMPED PERFORMANCE
(AV = +2, VH = 2V, VL = -2V)
CLAMPED PERFORMANCE
(AV = +2, VH = 1V, VL = -1V, 2X Overdrive)
AV = +2
IN
0V TO
1V
IN
0V TO
0.5V
AV = +2
OUT
0V TO
1V
OUT
0V TO
1V
20ns/DIV
20ns/DIV
FREQUENCY RESPONSE
FREQUENCY RESPONSE FOR VARIOUS LOAD RESISTORS
6
VOUT = 200mVP-P
AV = +1
A V = +2, VOUT = 200mVP-P
9
6
AV = +2
-6
0
PHASE
-9
-90
AV = +2
AV = -1
AV = +1
-180
-270
GAIN
3
RL = 50Ω
RL = 100Ω
0
RL = 1kΩ
0
PHASE
-90
RL = 100Ω
-360
-180
RL = 50Ω
RL = 1kΩ
0.3
1
10
FREQUENCY (MHz)
100
0.3
1000
FREQUENCY RESPONSE FOR VARIOUS LOAD RESISTORS
6
RL = 1kΩ
RL = 100Ω
RL = 50Ω
RL = 1kΩ
-9
0
PHASE
RL = 100Ω
RL = 50Ω
RL = 1kΩ
1
10
100
FREQUENCY (MHz)
-90
GAIN
-3
GAIN (dB)
GAIN
PHASE (DEGREES)
GAIN (dB)
-360
1000
0
-6
0.3
100
AV = -1, VOUT = 200mVP-P
3
0
-3
10
FREQUENCY (MHz)
FREQUENCY RESPONSE FOR VARIOUS LOAD RESISTORS
6
AV = +1, VOUT = 200mVP-P
3
1
-270
RL = 100Ω
RL = 50Ω
-6
-9
RL = 100Ω
180
PHASE
90
-180
PHASE (DEGREES)
-3
AV = -1
GAIN (dB)
GAIN
PHASE (DEGREES)
0
PHASE (DEGREES)
GAIN (dB) NORMALIZED
3
0
RL = 50Ω
-270
-90
RL = 1kΩ
-360
1000
0.3
1
10
100
FREQUENCY (MHz)
Spec Number
199
-180
1000
511106-883
HFA1113
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as
application and design information only. No guarantee is implied.
Typical Performance Curves
VSUPPLY = ±5V, RL = 100Ω, TA = +25oC, Unless Otherwise Specified (Continued)
FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES
12
6
1VP-P
AV = +2
9
FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES
GAIN
2.5VP-P
0
PHASE
-90
-180
4.0VP-P
2.5VP-P
1
VOUT = 2.5VP-P
-6
VOUT = 1VP-P
0
PHASE
-90
VOUT = 1VP-P
0.3
1000
1
10
100
FREQUENCY (MHz)
FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES
AV = -1
1000
FULL POWER BANDWIDTH
VOUT = 2.5VP-P
VOUT = 4VP-P
3
GAIN
VOUT = 5VP-P
12
0
PHASE
180
90
VOUT = 4VP-P
0
VOUT = 2.5VP-P
PHASE (DEGREES)
-6
GAIN (dB) NORMALIZED
9
VOUT = 1VP-P
-3
-90
VOUT = 1VP-P
1
10
100
FREQUENCY (MHz)
3
0
-3
AV = -1
AV = +2
-6
AV = +1
-12
-180
0.3
6
-9
-15
0.3
1000
-3dB BANDWIDTH vs TEMPERATURE
1
10
FREQUENCY (MHz)
100
1000
GAIN FLATNESS
900
0.35
0.30
A V = +1
850
800
GAIN (dB) NORMALIZED
GAIN (dB)
-360
15
6
BANDWIDTH (MHz)
-270
VOUT = 2.5VP-P
-360
10
100
FREQUENCY (MHz)
-180
VOUT = 4VP-P
-270
1VP-P
0.3
VOUT = 4VP-P
-3
GAIN (dB)
4.0VP-P
0
PHASE (DEGREES)
GAIN
3
PHASE (DEGREES)
0
6
GAIN (dB)
AV = +1
3
AV = -1
750
700
650
600
AV = +2
0.25
0.20
AV = +1
0.10
0.05
0
-0.05
550
AV = -1
0.15
AV = +2
-0.10
500
-0.15
-50
-25
0
+25
+50
+75
+100
+125
TEMPERATURE (oC)
1
10
100
FREQUENCY (MHz)
Spec Number
200
511106-883
HFA1113
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as
application and design information only. No guarantee is implied.
Typical Performance Curves
VSUPPLY = ±5V, RL = 100Ω, TA = +25oC, Unless Otherwise Specified (Continued)
DEVIATION FROM LINEAR PHASE
SETTLING RESPONSE
4
AV = +2, VOUT = 2V
0.6
2
1
SETTLING ERROR (%)
DEVIATION (DEGREES)
3
AV = -1
0
-1
AV = +2
-2
AV = +1
-3
-4
0.4
0.2
0.1
0
-0.1
-0.2
-0.4
-0.6
-5
-6
0
15
30
45
60
75
90
105
120
-2
135 150
3
8
13
18
23
28
33
38
43
48
TIME (ns)
FREQUENCY (MHz)
LOW FREQUENCY REVERSE ISOLATION (S12)
HIGH FREQUENCY REVERSE ISOLATION (S12)
180
-24
135
-30
PHASE
AV = +1
AV = +1
-48
GAIN (dB)
GAIN (dB)
-42
-54
AV = +2
-60
AV = -1
AV = -1
-66
0
GAIN
-30
AV = +2
AV = +1
-36
AV = -1
-48
-78
-54
-84
20
0
40
60
80
100
120 140
160
180
-60
100 190
200
FREQUENCY (MHz)
1dB GAIN COMPRESSION vs FREQUENCY
280 370
460 550 640 730
FREQUENCY (MHz)
820
910 1000
3rd ORDER INTERMODULATION INTERCEPT vs FREQUENCY
20
30
2 - TONE
18
16
INTERCEPT POINT (dBm)
OUTPUT POWER AT 1dB COMPRESSION (dBm)
45
AV = +2
-24
-42
AV = +2
-72
90
AV = -1
PHASE (DEGREES)
-36
AV = -1
14
AV = +2
12
10
AV = +1
8
6
AV = -1
20
AV = +2
AV = +1
10
4
2
0
100
200
300
FREQUENCY (MHz)
400
0
100
500
200
300
400
FREQUENCY (MHz)
Spec Number
201
511106-883
HFA1113
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as
application and design information only. No guarantee is implied.
Typical Performance Curves
VSUPPLY = ±5V, RL = 100Ω, TA = +25oC, Unless Otherwise Specified (Continued)
2nd HARMONIC DISTORTION vs POUT
-20
AV = +2
-30
-30
-40
-40
DISTORTION (dBc)
DISTORTION (dBc)
-20
3rd HARMONIC DISTORTION vs POUT
-50
-60
100MHz
30MHz
50MHz
-70
AV = +2
-50
-60
-70
-80
-80
-90
-90
30MHz
50MHz
100MHz
-100
-100
-6
-3
0
3
6
9
12
-6
15
-3
0
3
2nd HARMONIC DISTORTION vs POUT
12
15
18
3rd HARMONIC DISTORTION vs POUT
AV = +1
-30
AV = +1
-30
-40
-40
DISTORTION (dBc)
DISTORTION (dBc)
9
-20
-20
-50
-60
-70
100MHz
50MHz
30MHz
-50
-60
-70
100MHz
-80
-80
-90
-90
-6
-3
0
3
6
9
12
50MHz
-100
-6
-100
15
-3
OUTPUT POWER (dBm)
0
30MHz
3
6
9
12
15
12
15
OUTPUT POWER (dBm)
2nd HARMONIC DISTORTION vs POUT
3rd HARMONIC DISTORTION vs POUT
-20
-20
AV = -1
A V = -1
-30
-30
-40
-40
DISTORTION (dBc)
DISTORTION (dBc)
6
OUTPUT POWER (dBm)
OUTPUT POWER (dBm)
-50
-60
100MHz
-70
50MHz
30MHz
-50
-60
-70
-80
-80
30MHz
50MHz
100MHz
-90
-90
-100
-100
-6
-3
0
3
6
9
OUTPUT POWER (dBm)
12
-6
15
-3
0
3
6
9
OUTPUT POWER (dBm)
Spec Number
202
511106-883
HFA1113
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as
application and design information only. No guarantee is implied.
Typical Performance Curves
VSUPPLY = ±5V, RL = 100Ω, TA = +25oC, Unless Otherwise Specified (Continued)
INTEGRAL LINEARITY ERROR
OVERSHOOT vs INPUT RISE TIME
60
+0.04
VOUT = 0.5V
OVERSHOOT (%)
PERCENT ERROR (%)
50
+0.02
0
AV = +1
40
30
20
-0.02
AV = -1
10
AV = +2
0
100
-0.04
-3.0
-2.0
-1.0
0
+1.0
INPUT VOLTAGE (V)
+2.0
+3.0
300
700
900
1100
1300
INPUT RISE TIME (ps)
OVERSHOOT vs INPUT RISE TIME
OVERSHOOT vs INPUT RISE TIME
60
60
VOUT = 1V
VOUT = 2V
50
40
OVERSHOOT (%)
50
OVERSHOOT (%)
500
AV = +1
30
20
40
AV = +1
30
20
AV = +2
AV = -1
10
10
AV = -1
AV = +2
0
100
300
500
700
900
1100
0
100
1300
300
INPUT RISE TIME (ps)
700
900
1100
1300
INPUT RISE TIME (ps)
SUPPLY CURRENT vs SUPPLY VOLTAGE
SUPPLY CURRENT vs TEMPERATURE
25
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
24
23
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
500
22
21
20
19
18
17
16
15
5
6
7
8
9
-50
10
-25
0
+25
+50
+75
+100
+125
TEMPERATURE (oC)
TOTAL SUPPLY VOLTAGE (V+ - V-, V)
Spec Number
203
511106-883
HFA1113
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as
application and design information only. No guarantee is implied.
Typical Performance Curves
VSUPPLY = ±5V, RL = 100Ω, TA = +25oC, Unless Otherwise Specified (Continued)
OUTPUT VOLTAGE vs TEMPERATURE
INPUT NOISE CHARACTERISTICS
3.6
AV = -1
50
130
40
110
30
90
20
70
OUTPUT VOLTAGE (V)
+VOUT (R L = 100Ω)
3.3
3.2
NOISE VOLTAGE (nV/√Hz)
+VOUT (RL = 50Ω)
3.4
|-VOUT| (RL = 100Ω)
3.1
3.0
2.9
2.8
|-VOUT| (RL = 50Ω)
eni
50
10
ini
2.7
2.6
30
100
0
-50
-25
0
+25
+50
+75
TEMPERATURE (oC)
+100
+125
0.1
1
10
FREQUENCY (kHz)
VH CLAMP ACCURACY vs OVERDRIVE
NON-LINEARITY NEAR CLAMP VOLTAGE
(AV = -1)
20
350
15
VL = -3V
VL = -2V VL = -1V
10
5
0
-5
VH = 1V
-10
AV = ±1
300
CLAMP ACCURACY (mV)
VOUT - (AV * VIN) (mV)
NOISE CURRENT (pA/√Hz)
3.5
VH = 2V
VH = 3V
-15
VH = 500mV
250
VH = 1V
200
150
VH = 2V
100
VH = 100mV
50
-20
-3
-2
-1
0
1
2
3
0
AV * VIN (V)
0
VL CLAMP ACCURACY vs OVERDRIVE
250
100
200
300
OVERDRIVE (% OF VH)
400
500
VH CLAMP ACCURACY vs OVERDRIVE
400
AV = ±1
AV = +2
VL = 500mV
VH = 1V
CLAMP ACCURACY (mV)
CLAMP ACCURACY (mV)
200
VL = 1V
150
100
VL = 2V
50
300
VH = 2V
200
VH = 500mV
100
VH = 100mV
VL = 100mV
0
0
100
200
300
400
0
500
OVERDRIVE (% OF VL)
0
100
200
300
OVERDRIVE (% OF VH)
Spec Number
204
400
500
511106-883
HFA1113
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as
application and design information only. No guarantee is implied.
Typical Performance Curves
VSUPPLY = ±5V, RL = 100Ω, TA = +25oC, Unless Otherwise Specified (Continued)
VL CLAMP ACCURACY vs OVERDRIVE
OVERDRIVE RECOVERY vs OVERDRIVE
250
3500
VL = 1V
OVERDRIVE RECOVERY TIME (ps)
CLAMP ACCURACY (mV)
AV = +2
200
VL = 500mV
150
VL = 2V
100
50
VL = 100mV
0
0
100
200
300
OVERDRIVE (% OF VL)
400
500
3000
2500
VH = 2V
2000
1500
VH = 1V
1000
VH = 0.5V
500
VH = 0.1V
0
100
200
300
400
500
OVERDRIVE LEVEL (% OF CLAMP LEVEL)
CLAMP ACCURACY vs TEMPERATURE
CLAMP ACCURACY (mV)
130
CLAMP BIAS CURRENT vs TEMPERATURE
130
AV = -1, VIN = ±1.6V
VH = 1V, VL = -1V
120
110
VH
100
90
VL
80
70
60
-75
VH = 1V, VL = -1V
120
CLAMP BIAS CURRENT (µA)
140
110
100
90
VL
80
70
60
VH
50
40
30
-50
-25
0
+25 +50 +75
TEMPERATURE (°C)
20
-75
+100 +125 +150
VH CLAMP INPUT BANDWIDTH
-25
+25 +50 +75
0
TEMPERATURE (°C)
+100 +125 +150
VL CLAMP INPUT BANDWIDTH
6
6
VH = 300mVP-P
3
0
0
-3
-3
-6
VH = 600mVP-P
VH = 1.2VP-P
-9
VL = 300mVP-P
3
GAIN (dB)
GAIN (dB)
-50
-12
-6
VL = 600mVP-P
-9
VL = 1.2VP-P
-12
1
10
100
FREQUENCY (MHz)
1
1000
10
100
FREQUENCY (MHz)
Spec Number
205
1000
511106-883
HFA1113
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as
application and design information only. No guarantee is implied.
Application Information
Closed Loop Gain Selection
The HFA1113 features a novel design which allows the user
to select from three closed loop gains, without any external
components. The result is a more flexible product, fewer part
types in inventory, and more efficient use of board space.
This “buffer” operates in closed loop gains of -1, +1, or +2, and
gain selection is accomplished via connections to the ±Inputs.
Applying the input signal to +IN and floating -IN selects a gain
of +1, while grounding -IN selects a gain of +2. A gain of -1 is
obtained by applying the input signal to -IN with +IN grounded.
The table below summarizes these connections:
GAIN
(ACL )
CONNECTIONS
+INPUT (PIN 3)
-INPUT (PIN 2)
-1
GND
Input
+1
Input
NC (Floating)
+2
Input
GND
Figure 1 details starting points for the selection of this resistor. The points on the curve indicate the RS and C L combinations for the optimum bandwidth, stability, and settling time,
but experimental fine tuning is recommended. Picking a
point above or to the right of the curve yields an overdamped
response, while points below or left of the curve indicate
areas of underdamped performance.
R S and CL form a low pass network at the output, thus limiting system bandwidth well below the amplifier bandwidth
of 850MHz. By decreasing R S as CL increases (as illustrated in the curves), the maximum bandwidth is obtained
without sacrificing stability. Even so, bandwidth does
decrease as you move to the right along the curve. For
example, at A V = +1, R S = 50Ω, C L = 30pF, the overall
bandwidth is limited to 300MHz, and bandwidth drops to
100MHz at A V = +1, R S = 5Ω, C L = 340pF.
PC Board Layout
RS (Ω)
The frequency response of this amplifier depends greatly on
the amount of care taken in designing the PC board. The
use of low inductance components such as chip resistors and chip capacitors is strongly recommended,
while a solid ground plane is a must!
Attention should be given to decoupling the power supplies.
A large value (10µF) tantalum in parallel with a small value
(0.1µF) chip capacitor works well in most cases.
Terminated microstrip signal lines are recommended at the
input and output of the device. Capacitance directly on the
output must be minimized, or isolated as discussed in the
next section.
For unity gain applications, care must also be taken to
minimize the capacitance to ground seen by the amplifier’s
inverting input. At higher frequencies this capacitance will
tend to short the -INPUT to GND, resulting in a closed loop
gain which increases with frequency. This will cause
excessive high frequency peaking and potentially other
problems as well.
Capacitive loads, such as an A/D input, or an improperly
terminated transmission line will degrade the amplifier’s
phase margin resulting in frequency response peaking and
possible oscillations. In most cases, the oscillation can be
avoided by placing a resistor (RS) in series with the output
prior to the capacitance.
AV = +1
AV = +2
0
40
80
120 160 200 240 280 320
LOAD CAPACITANCE (pF)
360 400
FIGURE 1. RECOMMENDED SERIES OUTPUT RESISTOR vs.
LOAD CAPACITANCE
Evaluation Board
The performance of the HFA1113 may be evaluated using
the HFA11XX Evaluation Board, slightly modified as follows:
1. Remove the 500Ω feedback resistor (R2), and leave the
connection open.
2. A. For AV = +1 evaluation, remove the 500Ω gain setting
resistor (R1), and leave pin 2 floating.
B. For AV = +2, replace the 500Ω gain setting resistor
with a 0Ω resistor to GND.
An example of a good high frequency layout is the Evaluation Board shown in Figure 2.
Driving Capacitive Loads
50
45
40
35
30
25
20
15
10
5
0
The layout and modified schematic of the board are shown
in Figure 2.
To order evaluation boards, please contact your local sales
office.
Spec Number
206
511106-883
HFA1113
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as
application and design information only. No guarantee is implied.
V+
BOTTOM LAYOUT
TOP LAYOUT
VH
QP3
QP4
1
QN2
+IN
OUT V+
VL VGND
QP1
+IN
R1
Z
ICLAMP
+1
VV+
VH
QN1
∞ (AV = +1)
or 0Ω (AV = +2)
VH
1
8
50Ω
2
7
3
6
OUT
4
5
VL
IN
10µF
QN5
QP2
R1
0.1µF
10µF
50K
(30K
FOR
VL)
QN6
200Ω
QP6
QN3
QN4
QP5
+5V
50Ω
GND
0.1µF
-5V
V-IN
V-
RF = 300Ω
RG
(INTERNAL) (INTERNAL)
-IN
300Ω
GND
VOUT
FIGURE 2. EVALUATION BOARD SCHEMATIC AND LAYOUT
FIGURE 3. HFA1113 SIMPLIFIED VH CLAMP CIRCUITRY
Clamp Operation
General
The HFA1113 features user programmable output clamps to
limit output voltage excursions. Clamping action is obtained
by applying voltages to the VH and VL terminals (DIP pins 8
& 5) of the amplifier. VH sets the upper output limit, while VL
sets the lower clamp level. If the amplifier tries to drive the
output above VH, or below VL, the clamp circuitry limits the
output voltage at VH or VL (± the clamp accuracy), respectively. The low input bias currents of the clamp pins allow
them to be driven by simple resistive divider circuits, or
active elements such as amplifiers or DACs.
Clamp Circuitry
Figure 3 shows a simplified schematic of the HFA1113 input
stage, and the high clamp (VH) circuitry. As with all current
feedback amplifiers, there is a unity gain buffer (QX1 - QX2)
between the positive and negative inputs. This buffer forces
-IN to track +IN, and sets up a slewing current of:
(V-IN - VOUT)/RF + V-IN / RG .
This current is mirrored onto the high impedance node (Z) by
QX3-QX4, where it is converted to a voltage and fed to the
output via another unity gain buffer. If no clamping is utilized,
the high impedance node may swing within the limits defined
by QP4 and QN4. Note that when the output reaches it’s quiescent value, the current flowing through -IN is reduced to
only that small current (-IBIAS) required to keep the output at
the final voltage.
Tracing the path from V H to Z illustrates the effect of the
clamp voltage on the high impedance node. VH decreases
by 2V BE (QN6 and QP6) to set up the base voltage on QP5.
QP5 begins to conduct whenever the high impedance node
reaches a voltage equal to QP5’s base voltage + 2VBE (QP5
and QN5). Thus, QP5 clamps node Z whenever Z reaches
VH. R1 provides a pull-up network to ensure functionality
with the clamp inputs floating. A similar description applies to
the symmetrical low clamp circuitry controlled by V L.
When the output is clamped, the negative input continues to
source a slewing current (ICLAMP) in an attempt to force the
output to the quiescent voltage defined by the input. QP5
must sink this current while clamping, because the -IN current is always mirrored onto the high impedance node. The
clamping current is calculated as:
ICLAMP = (V-IN - VOUT CLAMPED) / 300Ω + V-IN / RG .
As an example, a unity gain circuit with VIN = 2V, and VH =
1V, would have ICLAMP = (2V-1V) / 300Ω + 2V / ∞ = 3.33mA
(R G = ∞ because -IN is floated for unity gain applications).
Note that ICC will increase by ICLAMP when the output is
clamp limited.
Clamp Accuracy
The clamped output voltage will not be exactly equal to the
voltage applied to VH or VL. Offset errors, mostly due to VBE
mismatches, necessitate a clamp accuracy parameter which
is found in the device specifications. Clamp accuracy is a
function of the clamping conditions. Referring again to Figure
3, it can be seen that one component of clamp accuracy is the
VBE mismatch between the QX6 transistors, and the QX5
transistors. If the transistors always ran at the same current
level there would be no VBE mismatch, and no contribution to
the inaccuracy. The QX6 transistors are biased at a constant
current, but as described earlier, the current through QX5 is
equivalent to ICLAMP . VBE increases as ICLAMP increases,
Spec Number
207
511106-883
HFA1113
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as
application and design information only. No guarantee is implied.
causing the clamped output voltage to increase as well.
ICLAMP is a function of the overdrive level (AVCL x VIN - VOUT
CLAMPED), so clamp accuracy degrades as the overdrive
increases. As an example, the specified accuracy of ±100mV
for a 1.6X overdrive degrades to ±240mV for a 3X overdrive.
Consideration must also be given to the fact that the clamp
voltages have an affect on amplifier linearity. The “Nonlinearity Near Clamp Voltage” curve in the data sheet illustrates the impact of several clamp levels on linearity.
Clamp Range
Unlike some competitor devices, both VH and VL have usable
ranges that cross 0V. While VH must be more positive than
VL, both may be positive or negative, within the range restrictions indicated in the specifications. For example, the
HFA1113 could be limited to ECL output levels by setting
VH = -0.8V and VL = -1.8V. VH and VL may be connected to
the same voltage (GND for instance) but the result won’t be a
DC output voltage from an AC input signal. A 150 - 200mV AC
signal will still be present at the output.
Recovery from Overdrive
The output voltage remains at the clamp level as long as the
overdrive condition remains. When the input voltage drops
below the overdrive level (VCLAMP / AVCL) the amplifier will
return to linear operation. A time delay, known as the Overdrive Recovery Time, is required for this resumption of linear
operation. The plots of “Unclamped Performance” and
“Clamped Performance” highlight the HFA1113’s subnanosecond recovery time. The difference between the
unclamped and clamped propagation delays is the overdrive
recovery time. The appropriate propagation delays are 8.0ns
for the unclamped pulse, and 8.8ns for the clamped (2X
overdrive) pulse yielding an overdrive recovery time of
800ps. The measurement uses the 90% point of the output
transition to ensure that linear operation has resumed. Note:
The propagation delay illustrated is dominated by the fixturing. The delta shown is accurate, but the true HFA1113
propagation delay is 500ps.
TYPICAL PERFORMANCE CHARACTERISTICS
Device Characterized at: V SUPPLY = ±5V, AV = +2V/V, RL = 100Ω, Unless Otherwise Specified.
PARAMETERS
CONDITIONS
TEMPERATURE
TYPICAL
UNITS
+25oC
8
mV
Full
10
µV/oC
Output Offset Voltage
AV = +1, VCM = 0V
Average Offset Voltage Drift
Versus Temperature
+Input Current
AV = +1, VCM = 0V
+25oC
25
µA
+Input Resistance
AV = +1, ∆VCM = 2V
+25oC
50
kΩ
-Input Resistance
+25 C
300
Ω
+Input Noise Voltage *
f = 100kHz
+25oC
9
nV/√Hz
f = 100kHz
+25oC
37
pA/√Hz
Full
±2.8
V
Input Capacitance
+25oC
2.2
pF
Gain
+25oC
0.99
V/V
+Input Noise Current *
o
Input Common Mode Range
AV = +1, VIN = 2V
o
Gain
AV = +2, VIN = 1V
+25 C
1.98
V/V
DC Non-Linearity *
VOUT = ±2V Full Scale
+25oC
0.02
%
AV = -1, RL = 100Ω
+25oC
±3.3
V
Full
Output Voltage *
AV = -1, RL = 100Ω
Output Current *
+25oC
AV = -1, RL = 50Ω
DC Closed Loop Output Resistance
-3dB Bandwidth *
RL = Open
AV = -1, VOUT = 200mV P-P
V
±60
mA
0oC
±50
mA
o
+25 C
0.3
Ω
Full
24
mA
+25oC
800
MHz
-55oC
AV = -1, RL = 50Ω
Quiescent Supply Current *
to
±3.0
+125oC
to
o
AV = +1, VOUT = 200mVP-P
+25 C
850
MHz
AV = +2, VOUT = 200mVP-P
+25oC
550
MHz
Spec Number
208
511106-883
HFA1113
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as
application and design information only. No guarantee is implied.
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Device Characterized at: V SUPPLY = ±5V, AV = +2V/V, RL = 100Ω, Unless Otherwise Specified.
PARAMETERS
Slew Rate
Full Power Bandwidth (Note 1)
Gain Flatness (Note 1)
Gain Flatness (Note 1)
Gain Flatness (Note 1)
Linear Phase Deviation (Note 1)
2nd Harmonic Distortion (Note 1)
3rd Harmonic Distortion (Note 1)
2nd Harmonic Distortion (Note 1)
CONDITIONS
AV = -1, VOUT = 5VP-P
3rd Harmonic Distortion (Note 1)
UNITS
2400
V/µs
o
AV = +1, VOUT = 5VP-P
+25 C
1500
V/µs
AV = +2, VOUT = 5VP-P
+25oC
AV = -1, VOUT = 5VP-P
1900
V/µs
o
300
MHz
o
+25 C
AV = +1, VOUT = 5VP-P
+25 C
150
MHz
AV = +2, VOUT = 5VP-P
+25oC
To 30MHz, AV = -1
220
MHz
o
±±0.02
dB
o
+25 C
To 30MHz, AV = +1
+25 C
±±0.10
dB
To 30MHz, AV = +2
+25oC
±0.015
dB
To 50MHz, AV = -1
+25oC
±0.05
dB
To 50MHz, AV = +1
+25 C
±0.20
dB
To 50MHz, AV = +2
+25oC
±0.036
dB
To 100MHz, AV = -1
+25oC
±0.10
dB
o
To 100MHz, AV = +2
+25 C
±0.07
dB
To 100MHz, AV = -1
+25oC
±0.13
Degrees
To 100MHz, AV = +1
+25oC
±0.83
Degrees
o
To 100MHz, AV = +2
+25 C
±0.05
Degrees
30MHz, AV = -1, VOUT = 2VP-P
+25oC
-52
dBc
30MHz, AV = +1, VOUT = 2VP-P
+25oC
-57
dBc
o
o
30MHz, AV = +2, VOUT = 2VP-P
+25 C
-52
dBc
30MHz, AV = -1, VOUT = 2VP-P
+25oC
-71
dBc
30MHz, AV = +1, VOUT = 2VP-P
+25oC
-73
dBc
o
30MHz, AV = +2, VOUT = 2VP-P
+25 C
-72
dBc
50MHz, AV = -1, VOUT = 2VP-P
+25oC
-47
dBc
50MHz, AV = +1, VOUT = 2VP-P
+25oC
-53
dBc
o
-47
dBc
o
+25 C
50MHz, AV = -1, VOUT = 2VP-P
+25 C
-63
dBc
50MHz, AV = +1, VOUT = 2VP-P
+25oC
50MHz, AV = +2, VOUT = 2VP-P
2nd Harmonic Distortion (Note 1)
TYPICAL
o
+25 C
50MHz, AV = +2, VOUT = 2VP-P
3rd Harmonic Distortion (Note 1)
TEMPERATURE
-68
dBc
o
-65
dBc
o
+25 C
100MHz, AV = -1, VOUT = 2V P-P
+25 C
-41
dBc
100MHz, AV = +1, VOUT = 2V P-P
+25oC
-50
dBc
o
100MHz, AV = +2, VOUT = 2V P-P
+25 C
-42
dBc
100MHz, AV = -1, VOUT = 2V P-P
+25oC
-55
dBc
100MHz, AV = +1, VOUT = 2V P-P
+25oC
-49
dBc
-62
dBc
100MHz, AV = +2, VOUT = 2V P-P
o
+25 C
Spec Number
209
511106-883
HFA1113
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as
application and design information only. No guarantee is implied.
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Device Characterized at: V SUPPLY = ±5V, AV = +2V/V, RL = 100Ω, Unless Otherwise Specified.
PARAMETERS
3rd Order Intercept (Note 1)
1dB Compression (Note 1)
Reverse Isolation (S12) (Note 1)
Rise and Fall Time
Overshoot (Note 1)
Settling Time (Note 1)
Differential Gain
CONDITIONS
100MHz
TEMPERATURE
TYPICAL
UNITS
o
28
dBm
o
+25 C
300MHz
+25 C
13
dBm
100MHz
+25oC
19
dBm
300MHz
+25o
C
12
dBm
40MHz
+25 C
-70
dB
100MHz
+25oC
-60
dB
600MHz
+25o
C
-32
dB
AV = -1, VOUT = 0.5V P-P
+25 C
500
ps
AV = +1, VOUT = 0.5VP-P
+25oC
480
ps
AV = +2, VOUT = 0.5VP-P
+25oC
700
ps
o
o
o
AV = -1, VOUT = 0.5V P-P
+25 C
12
%
AV = +1, VOUT = 0.5VP-P
+25oC
45
%
AV = +2, VOUT = 0.5VP-P
+25oC
6
%
o
AV = +2, to 0.1%, VOUT = 2V to 0V
+25 C
13
ns
AV = +2, to 0.05%, VOUT = 2V to 0V
+25oC
20
ns
AV = +2, to 0.02%, VOUT = 2V to 0V
+25oC
36
ns
o
AV = +2, RL = 150Ω, NTSC
+25 C
0.02
%
Differential Phase
AV = +2, RL = 150Ω, NTSC
+25oC
0.04
Degrees
Overdrive Recovery Time, (2X Overdrive)
VIN = ±1V, VH = +1V, VL = -1V
+25oC
0.75
ns
Clamp Accuracy
AV = -1, VIN = ±1.6V, VH = +1V,
VL = -1V
+25 C
±100
mV
Clamped Overshoot
VIN = ±1V, VH = +1V, VL = -1V,
Input tR / tF = 2ns
+25oC
7
%
Negative Clamp Range (VL)
+25oC
-5.0 to +2.0
V
Positive Clamp Range (VH)
+25oC
Clamp Input Bias Current
VH = +1V, VL = -1V
Clamp Input Bandwidth
VIN = ±100mV, VH or VL = 100mVP-P
o
-2.0 to +5.0
V
o
50
µA
o
500
MHz
+25 C
+25 C
NOTE:
1. See Typical Performance Curves for more information.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Spec Number
210
511106-883