IJW120R100T1

SiC - JF ET
Silicon Carbide- Junction Field Effect Transistor
Cool Si C ™
1200 V CoolSiC™ Power Transistor
IJW120R100T1
Final Da ta sheet
Rev. 2.0, <2013-09-11>
Po wer Ma nage m ent & M ulti m ark et
1200 V Silicon Carbide JFET
IJW120R100T1
Description
CoolSiC™ is Infineon’s new family of active power switches based on
silicon carbide. Combining the excellent material properties of silicon
carbide with our normally-on JFET concept allows the next steps towards
higher performance paired with very high ruggedness. The extremely low
switching and conduction losses make applications even more efficient,
compact, lighter and cooler.
Gate
Drain
Source
Features





Drain
Pin 2
Ultra fast switching
Internal fast body diode
Low intrinsic capacitance
Low gate charge
175 °C maximum operating temperature
Gate
Pin 1
Benefits





Enabling higher system efficiency and/ or higher output power in same housing
Enabling higher frequency / increased power density solutions
System cost / space savings due to reduced cooling requirements
Higher system reliability due to enlarged junction temperatures rates
Reduced EMI
Source
Pin 3
Applications




Solar Inverters
High voltage DC/ DC or AC/ DC conversion
Bidirectional Inverter
Compliant for applications according to climate class IEC 60721-3-4 (4K4H)
Table 1
Key Performance Parameters
Parameter
Value
Unit
VDS
1200
V
RDS(on) max
100
mΩ
QG, typ
72
nC
ID, pulse
78
A
Eoss @ 800 V
28
µJ
Table 2
Pin 1
Gate
Pin Definition
Pin 2
Pin 3
Drain
Source
Type / ordering Code
1)
IJW120R100T1
1)
Package
PG-TO247-3
Marking
120R100T1
Related links
www.infineon.com/CoolSiC
J-STD20 and JESD22
Final Datasheet
2
Rev. 2.0, <2013-09-11>
Silicon Carbide JFET
IJW120R100T1
Description
Table of Contents
Description ............................................................................................................................................................. 2
1
1.1
1.2
1.3
1.3.1
1.3.2
1.3.3
1.3.4
1.3.5
1.4
Application considerations ............................................................................................................... 4
Introduction ........................................................................................................................................... 4
Driver circuit ......................................................................................................................................... 4
Device characteristics .......................................................................................................................... 5
Gate voltage window ............................................................................................................................ 5
Controllability ........................................................................................................................................ 5
Reverse biased behavior ..................................................................................................................... 6
Short circuit ruggedness ...................................................................................................................... 6
Switching and conduction losses ......................................................................................................... 6
Environmental Conditions .................................................................................................................... 6
2
Maximum ratings ................................................................................................................................ 7
3
Thermal characteristics ..................................................................................................................... 8
4
Electrical characteristics ................................................................................................................... 8
5
Electrical characteristics diagrams ................................................................................................ 10
6
Test circuits ...................................................................................................................................... 17
7
Package outlines .............................................................................................................................. 18
8
Revision History ............................................................................................................................... 19
Final Datasheet
3
Rev. 2.0, <2013-09-11>
Silicon Carbide JFET
IJW120R100T1
Application considerations
1 Application considerations
1.1 Introduction
Wide bandgap semiconductors are very attractive as a basematerial for power devices due to low losses,
improved temperature capability and high thermal conductivity. Infineon’s silicon carbide schottky diodes have
been commercially available on the market for many years. The material and technology knowhow has been
used to create new active switches based on silicon carbide providing significant improvement in the value
proposition in comparison to known devices such as:
•
•
•
•
Resistive forward characteristic in first and third quadrant
Monolithic integrated body diode, in switching performance very close to SiC schottky barrier diodes
Very fast and controllable switching transients
Very low capacitances and gate charge
These benefits result in higher system efficiency, allow higher switching frequencies, increased power density
and reduced cooling efforts. Due to the normally-on JFET concept any reliability-relevant issues from gate
oxides on SiC are completely avoided. To allow the use of this normally-on concept in voltage-source-inverter
configurations we propose the following driver circuit.
1.2 Driver circuit
Being a normally-on device, the JFET is in its on-state at zero gate voltage and will go into the off-state at
negative gate voltage. The normally off behavior can be easily realized by implementing a cascode
configuration with a low voltage MOSFET as shown in Figure 1 (state of the art cascode). At e.g. startup, the LV
MOSFET is in the off-state pushing the source of the JFET to positive potential relative to its gate and keeping
the JFET hence in the off-state.
In this conventional cascode, the LV MOSFET will be switched on and off together with the JFET in each
switching cycle. This approach has two major drawbacks: firstly, at turn-on additional switching losses will occur
as the output capacitance of the LV MOSFET needs to be charged from the positive rail voltage, secondly the
combination allows no direct control of the JFET due to the absence of a (JFET) - Drain- to- (LV MOS) - Gate
capacitance. These drawbacks can be avoided with the proposed “direct drive” approach. Here, the JFET is
directly switched on and off by applying a negative gate voltage and 0V respectively, whereas the series
connected LV MOSFET is always in its on- state. The LV MOSFET is turned off only during start- up and e.g.
emergency cases such as loss of auxiliary power supply. This solution represents the best match between
performance and safety requirements. The driving scheme with a dedicated driver is shown in Fig. 2 (direct
drive technology with 1EDI30J12Cx).
Figure 1: state of the art cascode
Final Datasheet
Figure 2: direct drive technology with 1EDI30J12Cx
4
Rev. 2.0, <2013-09-11>
Silicon Carbide JFET
IJW120R100T1
Application considerations
1.3 Device characteristics
1.3.1 Gate voltage window
VGS(th) [V]
The gate electrode of the JFET shows, in contrary to isolated MOSFET concepts, a bipolar pn-junction like
characteristic: it get’s forward biased at around +2.5 V, hence a bipolar current will flow into the gate once the
gate- to- source voltage exceeds 2.5 V. This is uncritical and may be used to turn-on the device faster than with
the recommended 0 V turn-on. At 25 °C the threshold voltage of the channel can vary between -12 V and -15 V
(Figure 3: VGS(th)=f(Tj ) parameter: IGSS). The products will be delivered within three groups (bin1, bin2, bin3) of
1 V range each. For paralleling, it is only allowed to parallel devices from the same bin. The use of devices from
different bins for paralleling leads to different thermal device behavior. At a voltage of around -23 V the gate- tosource junction enters reverse breakdown, which leads to a temperature dependend bipolar current flow across
the junction. In pure voltage driven turn-on and turn-off the lower gate voltage should stay within the window
between the pinch-off (threshold) and the punch-through (increased leakage) voltage. For fast and safe turn-off
it is strongly recommended to move the lower gate voltage level as close as possible to the punch-through
threshold.
-11
-12
-13
-14
-15
-16
-17
-18
-19
-20
bin 1
bin 2
bin 3
gate off window
-50
25
Tj [°C]
100
175
Figure 3: VGS(th)=f(Tj ) parameter: IDSS=10 µA
1.3.2 Controllability
The JFET can be well controlled through its miller plateau with an external gate resistor (Figure 4: dVoff/ dt=
f(IDS), dVon/ dt= f(IDS), dIoff/ dt= f(IDS), dIon/ dt= f(IDS) parameter: Tj=25 °C, RG, external). Especially dI/ dt is saturating
at high current levels. This helps to avoid voltage overshoots in peak current conditions. It is strongly
recommended to use very low turn-off gate resistors (down to zero Ohm external gate resistor) to achive
maximum performance from the device as well as to avoid any parasitic dV/dt or dI/dt coupled turn-on effects.
As shown in the maximum rating division of the datasheet the external gate loop resistance should be lower
than 5.1 Ω.
Figure 4: dVoff/ dt= f(IDS), dVon/ dt= f(IDS), dIoff/ dt= f(IDS), dIon/ dt= f(IDS) parameter: Tj=25 °C, RG, external
Final Datasheet
5
Rev. 2.0, <2013-09-11>
Silicon Carbide JFET
IJW120R100T1
Application considerations
1.3.3 Reverse biased behavior
The monolithically integrated body diode shows a switching performance close to that of an external SiC
schottky barrier diodes, renowned for their zero reverse recovery characteristic. Figure 5 (reverse recovery
characteristic ISD= 2 A left and ISD= 10 A; Tj= 150 °C; Vbulk=400 V; RG, external = (T1) 3.3 Ω, (T2) 10 Ω) shows the
reverse recovery characteristic of the monolithic integrated body diode of the JFET. The reverse recovery
charge is load current independent. To avoid any additional losses during hard commutation of the body diode,
it is recommended to couple the gate of the switch (acting as diode) with a very low external gate resistor to the
gate driver.
T1
RG external
LLoad
VDS
VDS
T2
IDS
IDS
VGS
VGS
VDS
RG external
10mΩ
IDS
VGS
Figure 5:
reverse recovery characteristic ISD= 2 A left and ISD= 10 A; Tj= 150 °C; Vbulk=400 V; RG,
(T2) 10 Ω
external
= (T1) 3.3 Ω
Due to the material properties of SiC the forward voltage drop Vf of the internal body diode is significantly higher
compared to a SiC schottky barrier diode. Therefore, active turn-on of the channel of the JFET during reverse
operation (synchronous rectification) is the preferred way of operation.
1.3.4 Short circuit ruggedness
Due to excellent material properties and a very high temperature level for intrinsic carrier generation the device
shows extremely good short circuit ruggedness.
1.3.5 Switching and conduction losses
The switching energies are typically one order of magnitude lower than the losses of IGBTs. It is noteworthy to
consider that the JFET, as pure majority carrier device, has no forward knee voltage and can be used on its
ohmic characteristic both in forward and reverse direction.
Nevertheless, the JFET shows a strong dependency of the switching energies as function of the used gate
resistor. A low resistive value of the gate resistor is recommended to operate the JFET at optimal conditions.
The conduction losses in comparison to Super Junction MOSFET’s are less temperature dependent. A factor of
only 1.6 between 25 °C and 100 °C is measurable.
1.4
Environmental Conditions
The parts are proofed according to IEC 60721-3-4 (4K4H). (Low air temperature -20 °C; High air temperature
+55 °C; Low relative humitidy 4 %; High relative humitidy 100 %; Low absolute humitidy 0.9 g/ m³; High absolute
humitidy 36 g/ m³…)
Final Datasheet
6
Rev. 2.0, <2013-09-11>
Silicon Carbide JFET
IJW120R100T1
Maximum ratings
2 Maximum ratings
Table 3
Parameter
Maximum ratings
Symbol
Continuous current, drain source
1)
IDS
Values
Unit
Min.
Typ.
Max.
–
–
26
–
–
18
5)
–
–
10
5)
VGS = 0 V; TC = 25 °C;
RthJC = RthJC, max
VGS = 0 V; TC = 100 °C;
RthJC = RthJC, max
A
–
–
–
–
68
5)
–
–
60
5)
VGS
-19.5
–
2
V
Power dissipation
Ptot
–
–
W
dV/ dt ruggedness, drain source
dVDS/ dt
–
–
190
80
–
–
78
–
–
Pulsed current, drain source
Gate source voltage
1)
2)
Pulsed current, source drain
1)
IDS, pulse
78
ISD, pulsed
60
5)
VGS = 0 V; TC = 150 °C;
RthJC = RthJC, max
TC = 25 °C
V/ ns IDS ≤ IDS, pulse
VGS = -19.5 V; Tj = 25 °C;
RthJC = RthJC, max
A
VGS = -19.5 V; Tj = 150 °C;
RthJC = RthJC, max
V/ ns ISD ≤ IDS, pulse
dVSD/ dt
–
–
80
Gate loop resistance, turn off
RG, off
–
–
5.1
Ω
Operating and storage temp.
4)
Tj;Tstg
-55
–
175
°C
–
–
60
Mounting torque
VGS = 0 V; TC = 150 °C;
RthJC = RthJC, max
VGS = 0 V; TC = 25 °C;
RthJC = RthJC, max
VGS = 0 V; TC = 100 °C;
RthJC = RthJC, max
3)
dV/ dt ruggedness, source drain
Note/Test Condition
Ncm M 2.5 screws
1)
Limited by Tj, max
2)
The device is proofed against VGS peaks. That allows to drive the parts shortly outside of the given maximum ratings
(VGS, max= 20 V, VGS, min= -50 V @ tp, max= 20 ns). This will result in a temporary gate leakage peak only.
3)
See application information
4)
Prolonged storage at high temperatures reduces the lifetime of the product. Tested according to EIA/JESD22-A103D
5)
Limits derived from product characterization, parameter not measured during production
Final Datasheet
7
Rev. 2.0, <2013-09-11>
Silicon Carbide JFET
IJW120R100T1
Thermal characteristics
3 Thermal characteristics
Table 4
Parameter
Thermal characteristics TO-247-3
Symbol
Values
Min.
Unit
Thermal resistance, junction-case
RthJC
–
Typ.
–
Max.
0.78
Thermal resistance, junctionambient
RthJA
–
–
62
Soldering temperature,
T
wavesoldering only allowed at leads sold
–
–
260
Note/Test Condition
K/W leaded
°C
1.6 mm (0.063 in.) from case for
10 s
4 Electrical characteristics
Table 5
Parameter
Static characteristics
Symbol
Breakdown voltage, drain source
V(BR)DSS
Values
Typ.
Max.
1200
–
–
-13.1
bin2
-14.1
bin3
-15.0
bin1
-13.5
bin2
-14.5
bin3
-15.4
bin1
-13.8
bin2
-14.8
bin3
-15.7
–
–
–
–
–
–
–
–
–
-12.0
bin2
-12.9
bin3
-13.9
bin1
-12.3
bin2
-13.2
bin3
-14.2
bin1
-12.4
bin2
-13.3
bin3
-14.3
–
1.5
30
–
3
60
–
6
120
bin1
Gate threshold voltage
2)
Drain- source leakage current
VGS(th)
IDSS
Unit
Min.
VGS= -19.5 V; IDS= 1 mA;
TC= -50 °C
bin1
IDS= 10 µA; VDS= 40 V;
Tj= 25 °C
V
Drain- source on- state resistance
IGSS
RDS(on)
VDS= 1200 V; VGS= -19.5 V;
TC= 25 °C
1)
1)
–
–
90
–
–
360
1)
–
–
720
1)
–
0.080
0.100
–
0.130
–
Gate resistance
1)
2)
RG
0.175
–
–
1.4
–
VDS= 1200 V; VGS= -19.5 V;
TC= 100 °C
VDS= 1200 V; VGS= -19.5 V;
Tj= 150 °C
VDS= 0 V; VGS=-19.5 V;
TC= 25 °C
VDS= 0 V; VGS= -19.5 V;
TC= 100 °C
VDS= 0 V; VGS= -19.5 V;
TC= 150 °C
Ω
–
IDS= 10 µA; VDS= 40V;
1)
Tj= 100 °C;
IDS= 10 µA; VDS= 40 V;
1)
Tj= 150 °C;
µA
Gate- source leakage current
Note/Test Condition
VGS= 0 V; ID=9 A;
TC= 25 °C
VGS= 0 V; ID=9 A;
TC= 100 °C
VGS= 0 V; ID=9 A;
TC= 150 °C
f= 1 MHz, open drain;
TC = 25 °C
Limits derived from product characterization, parameter not measured during production
For paralleling see application note
Final Datasheet
8
Rev. 2.0, <2013-09-11>
Silicon Carbide JFET
IJW120R100T1
Electrical characteristics
Table 6
Parameter
Dynamic characteristics
Symbol
Input capacitance
Output capacitance
Values
Unit
Min.
Typ.
Max.
–
1550
–
–
1200
–
–
1070
–
–
80
–
Ciss
Coss
Effective output capacitance,
1)
energy related
Co(er)
–
89
–
Effective output capacitance,
2)
time related
Co(tr)
–
112
–
Turn- on delay time
td(on)
–
49
–
Turn- off delay time
td(off)
–
30
–
Rise time
tr
–
26
–
Fall time
tf
–
19
–
pF
Note/Test Condition
VGS= -19.5 V; VDS= 0 V;
f= 1 MHz
VGS= -19.5 V; VDS= 800 V;
f= 1 MHz
VGS= -19.5 V; VDS= 0 V;
f= 1 MHz
VGS= -19.5 V; VDS= 800 V;
f= 1 MHz
VGS= -19.5 V; VDS= 0 V/ 800 V;
TC=25 °C
VGS= -19.5 V; VDS= 0 V/ 800 V;
TC=25 °C
ns
VDS= 800 V;
VGS= -19.5 V/ 0 V; ID= 20 A;
TC= 25 °C; RG,tot= 2 Ω
1)
Co(er) is a fixed capacitance that gives the same stored energy as Coss while VDS is rising from 0 V to 800 V
2)
Co(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 V to 800 V
Table 7
Parameter
Gate charge characteristics
Symbol
Values
Min.
Unit
Typ.
16
Max.
–
Gate charge, gate to source
QGS
Gate charge, gate to drain
QGD
–
–
32
–
Gate charge, total
QG
–
72
–
Gate plateau voltage
Vplateau
–
-8
–
Table 8
Parameter
Reverse diode characteristics
Symbol
Diode forward voltage
VSD
Values
nC
Typ.
Max.
–
7.2
–
–
7.5
–
–
7.6
–
V
trr
–
15.6
–
ns
Reverse recovery charge
Qrr
–
118
–
nC
Peak reverse recovery current
Irrm
–
11
–
A
Current slope forward
dIF/ dt
–
3
–
dIrr/ dt
–
1.3
–
Final Datasheet
9
Note/Test Condition
ISD = 18 A; VGS= -19.5 V;
TC = 25 °C
Reverse recovery time
Current slope reverse
VDS= 800 V to 0 V; IDS= 18 A;
VGS= -19.5 V to 0 V
V
Unit
Min.
Note/Test Condition
ISD = 18 A; VGS= -19.5 V;
TC = 100 °C
ISD = 18 A; VGS= -19.5 V;
TC = 150 °C
ISD = 18 A; VDS = 800 V;
RG= 0 Ω; Tj = 25 °C
A/ns
Rev. 2.0, <2013-09-11>
Silicon Carbide JFET
IJW120R100T1
Electrical characteristics diagrams
5 Electrical characteristics diagrams
Table 9
Typical output characteristic
Typical output characteristic
IDS= ƒ(VDS ); Tj= 25 °C; parameter: VGS; Vpi 25 °C
IDS= ƒ(VDS ); Tj= 100 °C; parameter: VGS; Vpi 25 °C
Table 10
Typical output characteristic
Typical drain- source on- state resistance
0.3
0.25
RDS(on) [Ω]
0.2
ID=18A
0.15
ID=9A
0.1
0.05
0
-50 -25 0
25 50 75 100 125 150 175
Tj [°C]
IDS= ƒ(VDS ); Tj= 150 °C; parameter: VGS; Vpi 25 °C
Final Datasheet
RDS(on)= ƒ(Tj ); VGS= 0 V; Tj= 25 °C; parameter: IDS
10
Rev. 2.0, <2013-09-11>
Silicon Carbide JFET
IJW120R100T1
Electrical characteristics diagrams
Table 11
Typical transfer characteristic- linear scale
Typical transfer characteristic- logarithmic scale
140
1 000
25°C
120
100
80
T = 25 °C
IDS [A]
IDS [A]
100
175 °C
60
10
40
20
0
1
-14
-12
-10
-8
-6
-4
-2
0
2
-14
-12
-10
VGS [V]
-8
-6
-4
-2
0
2
VGS [A]
IDS= ƒ(VGS ); VDS= 30 V; parameter: Tj; Vpi 25 °C
IDS= ƒ(VGS ); VDS= 30 V; parameter: Tj; Vpi 25 °C
Table 12
Gate voltage window
Body diode characteristics
-11
0V
50
-5 V
-12
-13
bin 1
bin 2
40
-10 V
ISD [A]
VGS(th) [V]
-14
bin 3
-15
-16
30
-15 V
20
-17
-18
10
-20 V
gate off window 1)
-19
0
-20
-50
25
Tj [°C]
100
0
175
VGS(th) = ƒ(Tj ), VDS=40 V; parameter: IDSS=10 µA
2
4
6
8
10
VDS (V)
ISD= ƒ(VDS ); Tj= 25 °C parameter: VGS
1) lower gate voltage leads to increased leakage current
Final Datasheet
11
Rev. 2.0, <2013-09-11>
Silicon Carbide JFET
IJW120R100T1
Electrical characteristics diagrams
Table 13
Typical gate charge
Typical breakdown voltage
5
1 620
1 610
0
1 600
1 590
IDS = 18A
VBR(dss) [V]
VGS [V]
-5
-10
-15
IDS = 2 A
-20
-100
1 580
1 570
1 560
1 550
1 540
-80
-60
-40
-20
0
20
-50
0
50
QG [nC]
100
150
200
Tj [°C]
VGS= ƒ(QG ); VDS= 800 V; parameter: IDS
VBR(dss)= ƒ(Tj ); IDS= 1 mA
Table 14
Typical capacitances
Typical stored energy in Coss
50
10 000
45
40
35
Ciss
1 000
100
Eoss [µJ]
C [pF]
30
Coss
25
20
15
10
Crss
5
10
0
250
500
750
0
1000
0
VDS [V]
Ciss= ƒ(VDS ); VGS= -19.5 V; f= 1 MHz
Coss= ƒ(VDS ); VGS= -19.5 V; f= 1 MHz
Crss= ƒ(VDS ); VGS= -19.5 V; f= 1 MHz
Final Datasheet
200
400
600
800
1000
VDS [V]
Eoss= ƒ(VDS )
12
Rev. 2.0, <2013-09-11>
Silicon Carbide JFET
IJW120R100T1
Electrical characteristics diagrams
Table 15
Typical stored charge in Coss
Maximum gate leakage current IGSS
140
1.E-02
120
1.E-03
80
IGSS [A]
Qoss [nC]
100
60
1.E-04
40
20
0
1.E-05
0
200
400
600
800
1000
-50
0
50
100
150
200
Tj [°C]
VDS [V]
Qoss= ƒ (VDS)
IGss= ƒ(Tj); parameter VGS= -19.5 V
Table 16
Typical switching losses- JFET vs. IDH15S120
Typical switching losses- JFET vs. JFET
Ids= 1A
0.50
Ids= 10A
0.50
Ids= 10A
0.45
Ids= 20A
0.45
Ids= 20A
0.40
0.40
0.35
0.35
0.30
0.30
Eoff [mJ]
Eoff [mJ]
Ids= 1A
0.25
0.20
0.15
0.25
0.20
0.15
0.10
0.10
0.05
0.05
0.00
0.00
0
2
4
6
8
10
12
0
2
4
6
Rg off [Ω]
Rg off [Ω]
Eoff= ƒ(RG); Vbulk= 800 V; Tj = 25 °C;
Vpi = -13.5 V; parameter: IDS
Eoff= ƒ(RG); Vbulk= 800 V; Tj = 25 °C;
Vpi = -13.5 V; parameter: IDS
Final Datasheet
13
8
10
12
Rev. 2.0, <2013-09-11>
Silicon Carbide JFET
IJW120R100T1
Electrical characteristics diagrams
Table 17
Typical switching losses- JFET vs. IDH15S120
1)
Typical switching losses- JFET vs. JFET
1.20
1.20
400V
1.00
400V
1.00
800V
800V
0.80
Eon [A]
0.80
Eon [mJ]
1)
0.60
0.40
0.20
0.60
0.40
0.20
0.00
0.00
0
10
20
30
0
10
IDS [A]
20
30
IDS [A]
Eon= ƒ(IDS); Vbulk= 800 V; Tj = 25 °C; RG on= 3.3 Ω;
Vpi = -13.5 V; parameter: Vbulk
Eon= ƒ(IDS); Vbulk= 800 V; Tj = 25 °C; RG on= 3.3 Ω;
Vpi = -13.5 V; parameter: Vbulk
Table 18
Typical switching losses- JFET vs. IDH15S120
1)
Typical switching losses- JFET vs. JFET
0.40
0.40
0.35
400V
0.35
400V
0.30
800V
0.30
800V
0.25
Eoff [mJ]
Eoff [mJ]
0.25
0.20
0.15
0.20
0.15
0.10
0.10
0.05
0.05
0.00
0.00
0
10
20
30
0
IDS [A]
10
20
30
IDS [A]
Eoff= ƒ(IDS); Vbulk= 800 V; Tj = 25 °C; RG off= 3.3 Ω;
Vpi = -13.5 V; parameter: Vbulk
1)
1)
Eoff= ƒ(IDS); Vbulk= 800 V; Tj = 25 °C; RG off= 3.3 Ω;
Vpi = -13.5 V; parameter: Vbulk
Measured with Push Pull stage close to the gate; Rg =0 Ω
Final Datasheet
14
Rev. 2.0, <2013-09-11>
Silicon Carbide JFET
IJW120R100T1
Electrical characteristics diagrams
Table 19
Power dissipation
Safe operating area
200
100
1 µs
180
160
10 µs
10
120
100
IDS [A]
Ptot [W]
140
80
100 µs
1
60
1 ms
40
10 ms
20
DC
0
0.1
0
50
100
150
200
1
10
Tc [°C]
100
1000
VDS [V]
Ptot= ƒ(TC )
IDS= ƒ(VDS ); Tc= 25 °C; D= 0 parameter: tp
Table 20
Safe operating area
Safe operating area
100
100
1 µs
1 µs
1 ms
10 µs
10
10 µs
IDS [A]
IDS [A]
10
100 µs
1
1
100 µs
1 ms
DC
DC
10 ms
0.1
10 ms
0.1
1
10
100
1000
1
VDS [V]
IDS= ƒ(VDS ); Tc= 100 °C; D= 0 parameter: tp
Final Datasheet
10
100
1000
VDS [V]
IDS= ƒ(VDS ); Tc= 150 °C; D= 0 parameter: tp
15
Rev. 2.0, <2013-09-11>
Silicon Carbide JFET
IJW120R100T1
Electrical characteristics diagrams
Table 21
Safe operating area diode
Maximum transient thermal impedance
1E0
ZTHjc [K/W]
ID max [A]
100
10
Pulse Width [s]
1E-06
1E-05
1E-04
1E-03
1
1E-04
1E-03
1E-02
1E-01
Final Datasheet
0.5
0.2
0.1
0.05
0.02
0.01
0
1E-2
1E-3
1E-6
1E+00
1E-4
1E-2
1E0
tp [s]
D
ISD max= ƒ(D= tp / T); Tc= 25 °C; parameter: tp
1E-1
ZTHjc= ƒ(tp ); parameter: D= tp / T
16
Rev. 2.0, <2013-09-11>
Silicon Carbide JFET
IJW120R100T1
Test circuits
6 Test circuits
Table 22
Switching times test circuit for inductive load
Switching time waveform
LLoad
V
90%
VDS
10%
VGS
T2
RG external
td(on)
10mΩ
td(off)
tf
tr
ton
toff
t
Table 23
Unclamped inductive load test circuit
Unclamped inductive waveform
V, I
LLoad
T2
V(BR)DS
RG external
VDS
10mΩ
IDS
t
Table 24
Test circuit for diode characteristics
Diode recovery waveform
T1
V, I
RG external
VDS(peak)
LLoad
VDS
VDS
trr
IF
T2
tF
IDS
QF
10mΩ
Irrm
Final Datasheet
tS
dIF/ dt
RG external
17
QS
t
10% Irrm
dIrr/ dt
trr = tF + tS
Qrr = QF + QS
Rev. 2.0, <2013-09-11>
Silicon Carbide JFET
IJW120R100T1
Package outlines
7 Package outlines
Figure 1
Final Datasheet
Outlines PG-TO247-3, dimensions in mm/inches
18
Rev. 2.0, <2013-09-11>
Silicon Carbide JFET
IJW120R100T1
Revision History
8 Revision History
IJW120R100T1, 1200 V CoolSiC™ Power Transistor
Revision History: Rev. 2.0, <2013-09-11>
Previous Revision:
Revision
Subjects (major changes since last version)
0.9
Target datasheet
1.0
Preliminary Datasheet
2.0
Final Datasheet
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Edition 2011-12-09
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2011 Infineon Technologies AG
All Rights Reserved.
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Final Datasheet
19
Rev. 2.0, <2013-09-11>
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