74HC4050-Q100 Hex non-inverting HIGH-to-LOW level shifter Rev. 1 — 30 January 2013 Product data sheet 1. General description The 74HC4050-Q100 is a hex buffer with over-voltage tolerant inputs. Inputs are overvoltage tolerant to 15 V which enables the device to be used in HIGH-to-LOW level shifting applications. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C Low-power dissipation Complies with JEDEC standard no. 7A ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Multiple package options 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC4050D-Q100 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 74HC4050PW-Q100 40 C to +125 C 74HC4050-Q100 NXP Semiconductors Hex non-inverting HIGH-to-LOW level shifter 4. Functional diagram 3 5 7 9 11 14 1A 1Y 2A 2Y 3A 3Y 4A 4Y 5A 5Y 6A 6Y 99 2 4 6 99 99 10 99 12 15 99 < $ DDD 001aae605 Fig 1. 99 Logic symbol Fig 2. DDD IEC logic symbol Fig 3. Logic diagram (one level shifter) 5. Pinning information 5.1 Pinning +&4 9&& QF < < $ $ < QF $ < < $ $ < *1' +&4 $ 9&& QF < < $ $ < QF $ < < $ $ < *1' DDD Fig 4. Pin configuration SO16 74HC4050_Q100 Product data sheet $ DDD Fig 5. Pin configuration TSSOP16 All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 January 2013 © NXP B.V. 2013. All rights reserved. 2 of 13 74HC4050-Q100 NXP Semiconductors Hex non-inverting HIGH-to-LOW level shifter 5.2 Pin description Table 2. Pin description Symbol Pin Description VCC 1 supply voltage 1Y to 6Y 2, 4, 6, 10, 12, 15 output 1A to 6A 3, 5, 7, 9, 11, 14 input GND 8 ground (0 V) n.c. 13, 16 not connected 6. Functional description Table 3. Function table [1] Input Output nA nY L L H H [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage VIK input clamping voltage IIK input clamping current VI < 0.5 V IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V IO output current VO = 0.5 V to (VCC + 0.5 V) ICC supply current - +50 mA IGND ground current - 50 mA Tstg storage temperature 65 +150 C - 500 mW [1] total power dissipation Ptot [1] Conditions Min Max Unit 0.5 +7 V 0.5 +16 V 20 - mA - 20 mA - 25 mA For SO16 packages: Ptot derates linearly with 8 mW/K above 70 C. For TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 C. 74HC4050_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 January 2013 © NXP B.V. 2013. All rights reserved. 3 of 13 74HC4050-Q100 NXP Semiconductors Hex non-inverting HIGH-to-LOW level shifter 100 Ω input to logic circuit polysilicon resistor D1 GND 001aan375 Fig 6. Input protection for the 74HC4050-Q100 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Min Typ Max Unit VCC supply voltage Conditions 2.0 5.0 6.0 V VI input voltage 0 - 15 V VO output voltage 0 - VCC V Tamb ambient temperature t/V input transition rise and fall rate 40 +25 +125 C VCC = 2.0 V; VI = 2.0 V - - 625 ns/V VCC = 4.5 V; VI = 4.5 V - 1.67 139 ns/V VCC = 6.0 V; VI = 6.0 V - - 83 ns/V VCC = 6.0 V; VI = 10.0 V - - 81 ns/V VCC = 6.0 V; VI = 15.0 V - - 83 ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage 74HC4050_Q100 Product data sheet Tamb = 25 C Conditions Tamb = 40 C to +85 C Tamb = 40 C to Unit +125 C Min Typ Max Min Max Min Max VCC = 2.0 V 1.5 1.3 - 1.5 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.1 - 4.2 - 4.2 - V VCC = 2.0 V - 0.7 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 1.8 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.3 1.8 - 1.8 - 1.8 V IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = 4.0 mA; VCC = 4.5 V 3.98 - - 3.84 - 3.7 - V IO = 5.2 mA; VCC = 6.0 V 5.48 - - 5.34 - 5.2 - V VI = VIH or VIL All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 January 2013 © NXP B.V. 2013. All rights reserved. 4 of 13 74HC4050-Q100 NXP Semiconductors Hex non-inverting HIGH-to-LOW level shifter Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = 25 C Conditions Min VOL II LOW-level output voltage input leakage current ICC supply current CI input capacitance Tamb = 40 C to +85 C Tamb = 40 C to Unit +125 C Typ Max Min Max Min Max VI = VIH or VIL IO = 20 A; VCC = 2.0 V - - 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 4.5 V - - 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 6.0 V - - 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - - 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - - 0.26 - 0.33 - 0.4 V VI = VCC or GND; VCC = 6.0 V - - 0.1 - 1.0 - 1.0 A VI = 15 V; VCC = 2.0 V to 6.0 V - - 0.5 - 5.0 - 5.0 A VI = 15 V or GND; IO = 0 A; VCC = 6.0 V - - 2.0 - 20 - 40 A - 3.5 - - - - - pF 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 8. Symbol Parameter tpd tt propagation delay transition time 74HC4050_Q100 Product data sheet Tamb = 25 C Conditions Tamb = 40 C to +85 C Tamb = 40 C to +125 C Unit Min Typ Max Min Max Min Max VCC = 2.0 V - 25 85 - 105 - 130 ns VCC = 4.5 V - 9 17 - 21 - 26 ns VCC = 5 V; CL = 15 pF - 7 - - - - - ns VCC = 6.0 V - 7 14 - 18 - 22 ns VCC = 2.0 V - 19 75 - 95 - 110 ns VCC = 4.5 V - 7 15 - 19 - 22 ns VCC = 6.0 V - 6 13 - 16 - 19 ns nA to nY; see Figure 7 Yn; see Figure 7 [1] [2] All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 January 2013 © NXP B.V. 2013. All rights reserved. 5 of 13 74HC4050-Q100 NXP Semiconductors Hex non-inverting HIGH-to-LOW level shifter Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 8. Symbol Parameter CPD power dissipation capacitance Tamb = 25 C Conditions Tamb = 40 C to +125 C Min Typ Max Min Max Min Max - 14 - - - - - [3] CL = 50 pF; f = 1 MHz; VI = GND to VCC Tamb = 40 C to +85 C [1] tpd is the same as tPLH and tPHL. [2] tt is the same as tTHL and tTLH. [3] CPD is used to determine the dynamic power dissipation (PD in W). Unit pF PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL VCC2 fo) = sum of outputs. 11. Waveforms 9, Q$LQSXW 90 90 *1' W3+/ W3/+ 92+ Q<RXWSXW 90 90 92/ W7+/ W7/+ DDD Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Table 8. The input (nA) to output (nY) propagation delays Measurement points Type 74HC4050-Q100 74HC4050_Q100 Product data sheet Input Output VM VM 0.5VCC 0.5VCC All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 January 2013 © NXP B.V. 2013. All rights reserved. 6 of 13 74HC4050-Q100 NXP Semiconductors Hex non-inverting HIGH-to-LOW level shifter VI negative pulse tW 90 % VM VM 10 % GND tr tf tr tf VI 90 % positive pulse GND VM VM 10 % tW VCC G VI VO DUT RT CL 001aah768 Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch. Fig 8. Table 9. Test circuit for measuring switching times Test data Type Input VI tr, tf CL 74HC4050-Q100 VCC 6.0 ns 15 pF, 50 pF 74HC4050_Q100 Product data sheet Load All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 January 2013 Test tPLH, tPHL © NXP B.V. 2013. All rights reserved. 7 of 13 74HC4050-Q100 NXP Semiconductors Hex non-inverting HIGH-to-LOW level shifter 12. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. Fig 9. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT109-1 (SO16) 74HC4050_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 January 2013 © NXP B.V. 2013. All rights reserved. 8 of 13 74HC4050-Q100 NXP Semiconductors Hex non-inverting HIGH-to-LOW level shifter TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 10. Package outline SOT403-1 (TSSOP16) 74HC4050_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 January 2013 © NXP B.V. 2013. All rights reserved. 9 of 13 74HC4050-Q100 NXP Semiconductors Hex non-inverting HIGH-to-LOW level shifter 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MIL Military MM Machine Model 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC4050_Q100 v.1 20130130 Product data sheet - - 74HC4050_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 January 2013 © NXP B.V. 2013. All rights reserved. 10 of 13 74HC4050-Q100 NXP Semiconductors Hex non-inverting HIGH-to-LOW level shifter 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 15.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 74HC4050_Q100 Product data sheet Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 January 2013 © NXP B.V. 2013. All rights reserved. 11 of 13 74HC4050-Q100 NXP Semiconductors Hex non-inverting HIGH-to-LOW level shifter No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74HC4050_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 January 2013 © NXP B.V. 2013. All rights reserved. 12 of 13 74HC4050-Q100 NXP Semiconductors Hex non-inverting HIGH-to-LOW level shifter 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10 Legal information. . . . . . . . . . . . . . . . . . . . . . . 11 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Contact information. . . . . . . . . . . . . . . . . . . . . 12 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 30 January 2013 Document identifier: 74HC4050_Q100