RFP45N02L,
RF1S45N02L, RF1S45N02LSM
45A, 20V, 0.022 Ohm, N-Channel
Logic Level Power MOSFETs
May 1997
Features
Description
• 45A, 20V
The RFP45N02L, RF1S45N02L, and RF1S45N02LSM are
N-Channel power MOSFETs manufactured using the
MegaFET process. This process, which uses feature sizes
approaching those of LSI circuits, gives optimum utilization
of silicon, resulting in outstanding performance. They were
designed for use in applications such as switching
regulators, switching converters, motor drivers and relay
drivers. These transistors can be operated directly from integrated circuits.
• rDS(ON) = 0.022Ω
• Temperature Compensating PSPICE Model
• Can be Driven Directly from CMOS, NMOS, and TTL
Circuits
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
Formerly developmental type TA49243.
• 175oC Operating Temperature
Ordering Information
PART NUMBER
PACKAGE
Symbol
D
BRAND
RFP45N02L
TO-220AB
FP45N02L
RF1S45N02L
TO-262AA
F45N02L
RF1S45N02LSM
TO-263AB
F45N02L
G
NOTE: When ordering, use the entire part number. Add the suffix,
9A, to obtain the TO-263AB variant in tape and reel, e.g.
RF1S45N02LSM9A.
S
Packaging
JEDEC TO-220AB
SOURCE
DRAIN
GATE
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
A
DRAIN
(FLANGE)
JEDEC TO-262AA
JEDEC TO-263AB
M
A
A
DRAIN
(FLANGE)
GATE
SOURCE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
File Number
4342
RFP45N02L, RF1S45N02L, RF1S45N02LSM
Absolute Maximum Ratings
TC = 25oC Unless Otherwise Specified
RFP45N02L, RF1S45N02L,
RF1S45N02LSM
UNITS
Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
20
V
Drain to Gate Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
20
V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
±10
V
Drain Current
Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
45
Refer to Peak Current Curve
A
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS
Refer to UIS Curve
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD
Derate Above 25oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
0.606
W
W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ, TSTG
-55 to 175
oC
Soldering Temperature of Leads for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
260
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
TC = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Drain to Source Breakdown Voltage
BVDSS
ID = 250µA, VGS = 0V
20
-
-
V
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA
1
-
2
V
-
-
1
µA
-
-
50
µA
VGS = ±10V
-
-
±100
nA
ID = 45A, VGS = 5V
-
-
0.022
Ω
-
-
260
ns
-
15
-
ns
tr
-
160
-
ns
td(OFF)
-
20
-
ns
tf
-
20
-
ns
tOFF
-
-
60
ns
-
50
60
nC
-
30
36
nC
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
Drain to Source On Resistance
Turn-On Time
Turn-On Delay Time
IDSS
IGSS
rDS(ON)
tON
td(ON)
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
VDS = 20V,
VGS = 0V
TC = 25oC
TC = 150oC
VDD = 15V, ID ≅ 45A,
RL = 0.33Ω, VGS = 5V,
RGS = 5Ω
Total Gate Charge
Qg(TOT)
VGS = 0V to 10V
Gate Charge at 5V
Qg(5)
VGS = 0V to 5V
Qg(TH)
VGS = 0V to 1V
-
1.5
1.8
nC
VDS = 15V, VGS = 0V,
f = 1MHz
-
1300
-
pF
-
724
-
pF
-
250
-
pF
Threshold Gate Charge
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VDD = 16V,
ID ≅ 45A,
RL = 0.35Ω
Thermal Resistance Junction to Case
RθJC
-
-
1.65
oC/W
Thermal Resistance Junction to Ambient
RθJA
-
-
80
oC/W
MIN
TYP
MAX
UNITS
ISD = 45A
-
-
1.5
V
ISD = 45A, dISD/dt = 100A/µs
-
-
125
ns
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
SYMBOL
VSD
trr
TEST CONDITIONS
2
RFP45N02L, RF1S45N02L, RF1S45N02LSM
Typical Performance Curves
50
1.0
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
40
30
20
10
0.2
0
25
0
0
25
50
75
100
125
TC , CASE TEMPERATURE (oC)
150
175
50
75
100
125
150
175
TC, CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs
TEMPERATURE DERATING
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
ZθJC, NORMALIZED
THERMAL IMPEDANCE
1
0.5
0.2
0.1
PDM
0.1
.05
t1
t2
.02
.01
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x RθJC x ZθJC + TC
SINGLE PULSE
0.01
10-5
10-4
10-3
10-2
10-1
101
100
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
500
TC = 25oC, TJ = MAX RATED
VGS = 10V
IDM, PEAK CURRENT (A)
ID, DRAIN CURRENT (A)
500
100
100µs
1ms
10
10ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
1
1
100ms
DC
VGS = 5V
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
I
100
= I25
175 - TC
150
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
VDSS MAX = 20V
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
TC = 25oC
10
10-5
50
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
10-4
10-3
10-2
10-1
t, PULSE WIDTH (s)
100
FIGURE 5. PEAK CURRENT CAPABILITY
3
101
RFP45N02L, RF1S45N02L, RF1S45N02LSM
Typical Performance Curves (Continued)
100
VGS = 10V
VGS = 5V
100
STARTING TJ = 25oC
ID, DRAIN CURRENT (A)
IAS, AVALANCHE CURRENT (A)
200
STARTING TJ = 150oC
10
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS-VDD) +1]
1
0.001
75
VGS = 4.5V
50
0.1
1
tAV , TIME IN AVALANCHE (ms)
VGS = 3.5V
25
VGS = 3V
PULSE DURATION = 250µs, TC = 25oC
0
0.01
VGS = 4V
10
100
0
2
1
4
3
5
VDS, DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
FIGURE 7. SATURATION CHARACTERISTICS
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
VDD = 15V
100
-55oC
175oC
75
75
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
ID(ON), ON-STATE DRAIN CURRENT (A)
100
25oC
50
25
PULSE TEST
PULSE DURATION = 250µs
DUTY CYCLE = 0.5% MAX
0
0
1.5
3.0
4.5
6.0
VGS, GATE TO SOURCE VOLTAGE (V)
ID = 30A
ID = 45A
50
ID = 2A
25
PULSE DURATION = 250µs
0
2.5
7.5
3.0
3.5
4.0
4.5
5.0
VGS, GATE TO SOURCE VOLTAGE (V)
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs
GATE VOLTAGE AND DRAIN CURRENT
350
2.0
VDD = 15V, ID = 45A, RL = 0.333Ω
NORMALIZED ON RESISTANCE
PULSE DURATION = 250µs, VGS = 5V, ID = 45A
300
tr
SWITCHING TIME (ns)
ID = 15A
250
200
150
tf
100
td(OFF)
50
1.5
1.0
0.5
td(ON)
0
0
0
30
20
40
10
RGS, GATE TO SOURCE RESISTANCE (Ω)
-80
50
FIGURE 10. SWITCHING TIME AS A FUNCTION OF GATE
RESISTANCE
-40
0
40
80
120
TJ, JUNCTION TEMPERATURE (oC)
160
FIGURE 11. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
4
200
RFP45N02L, RF1S45N02L, RF1S45N02LSM
Typical Performance Curves (Continued)
2.0
2.0
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
1.5
1.0
0.5
0
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
1.5
1.0
0.5
0
-80
200
-40
0
40
80
120
5.00
20
VDS , DRAIN TO SOURCE VOLTAGE (V)
VGS = 0V, f = 1MHz
1500
CISS
1000
COSS
CRSS
0
5
VDD = BVDSS
VDD = BVDSS
2000
0
10
15
200
FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
2500
500
160
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
C, CAPACITANCE (pF)
ID = 250µA
20
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
15
10
5
3.75
RL = 0.44Ω
IG(REF) = 0.5mA
VGS = 5V
2.50
PLATEAU VOLTAGES IN
DESCENDING ORDER:
VDD = BVDSS
VDD = 0.75 BVDSS
VDD = 0.50 BVDSS
VDD = 0.25 BVDSS
1.25
0
0
I G ( REF )
20 ---------------------I G ( AC T )
t, TIME (µs)
I G ( REF )
80 ---------------------I G ( AC T )
NOTE: Refer to Application Notes AN7254 and AN7260.
FIGURE 15. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
5
VGS , GATE TO SOURCE VOLTAGE (V)
NORMALIZED GATE
THRESHOLD VOLTAGE
VGS = VDS, ID = 250µA
RFP45N02L, RF1S45N02L, RF1S45N02LSM
Test Circuits and Waveforms
VDS
BVDSS
tP
L
VDS
IAS
VARY tP TO OBTAIN
VDD
+
RG
REQUIRED PEAK IAS
VDD
-
VGS
DUT
tP
0V
IAS
0.01Ω
tAV
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
tON
tOFF
td(ON)
td(OFF)
RL
tf
tr
VDS
+
RG
-
90%
90%
VDD
10%
10%
DUT
90%
VGS
VGS
50%
10%
FIGURE 18. RESISTIVE SWITCHING TEST CIRCUIT
50%
PULSE WIDTH
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 10V
VGS
Qg(5)
+
VDD
VGS = 5V
VGS
-
VGS = 1V
DUT
0
IG(REF)
Qg(TH)
IG(REF)
0
FIGURE 20. GATE CHARGE TEST CIRCUIT
FIGURE 21. GATE CHARGE WAVEFORMS
6
RFP45N02L, RF1S45N02L, RF1S45N02LSM
Temperature Compensated PSPICE Model for the
RFP45N02L, RF1S45N02L, RF1S45N02LSM
.SUBCKT RFP45N02L 2 1 3 ;
rev 11/22/94
CA 12 8 2.55e-9
CB 15 14 2.64e-9
CIN 6 8 1.05e-9
DPLCAP
DBODY 7 5 DBDMOD
DBREAK 5 11 DBKMOD
DPLCAP 10 5 DPLCAPMOD
RSCL2
RSCL1
5
51
-
1
EVTO
20 + 18 8
LGATE RGATE
VTO +
21
6
9
+
17
18
DBODY
-
16
MOS2
MOS1
RIN
CIN
MOS1 16 6 8 8 MOSMOD M = 0.99
MOS2 16 21 8 8 MOSMOD M = 0.01
8
RSOURCE
LSOURCE
7
3
SOURCE
S2A
S1A
12
13
8
S1B
RBREAK
15
14
13
17
18
S2B
13
CA
RVTO
CB
+
EGS
S1A
S1B
S2A
S2B
EBREAK
RDRAIN
+
GATE
11
ESCL
50
6
8
ESG
IT 8 17 1
RBREAK 17 18 RBKMOD 1
RDRAIN 50 16 RDSMOD 0.14e-3
RGATE 9 20 0.89
RIN 6 8 1e9
RSCL1 5 51 RSCLMOD 1e-6
RSCL2 5 50 1e3
RSOURCE 8 7 RDSMOD 10.31e-3
RVTO 18 19 RVTOMOD 1
DBREAK
+ 51
EBREAK 11 7 17 18 33.3
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTO 20 6 18 8 1
LDRAIN 2 5 1e-9
LGATE 1 9 4.9e-9
LSOURCE 3 7 4.9e-9
DRAIN
2
LDRAIN
5
10
14
+
6
8
EDS
-
5
8
IT
19
VBAT
+
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
VBAT 8 19 DC 1
VTO 21 6 0.583
ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/176,6))}
.MODEL DBDMOD D (IS = 3.61e-13 RS = 5.06e-3 TRS1 = 3.05e-3 TRS2 = 7.57e-6 CJO = 2.0e-9 TT = 2.18e-8)
.MODEL DBKMOD D (RS = 1.66e-1 TRS1 = -2.97e-3 TRS2 = 7.57e-6)
.MODEL DPLCAPMOD D (CJO = 1.25e-9 IS = 1e-30 N = 10)
.MODEL MOSMOD NMOS (VTO = 2.313 KP = 53.82 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL RBKMOD RES (TC1 = 8.95e-4 TC2 = -1e-7)
.MODEL RDSMOD RES (TC1 = 3.82e-3 TC2 = 1.17e-5)
.MODEL RSCLMOD RES (TC1 = 2.03e-3 TC2 = 0.45e-5)
.MODEL RVTOMOD RES (TC1 = -2.27e-3 TC2 = -5.75e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.82 VOFF= -2.82)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.82 VOFF= -4.82)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.67 VOFF= 2.33)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.33 VOFF= -2.67)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; written by William J. Hepp and C. Frank Wheatley.
7
RFP45N02L, RF1S45N02L, RF1S45N02LSM
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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8
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