RFP14N06
Data Sheet
14A, 60V, 0.100 Ohm, N-Channel Power
MOSFET
This N-Channel power MOSFET is manufactured using the
MegaFET process. This process which uses feature sizes
approaching those of LSI integrated circuits, gives optimum
utilization of silicon, resulting in outstanding performance. It
was designed for use in applications such as switching
regulators, switching convertors, motor drivers, and relay
drivers. This transistor can be operated directly from
integrated circuits.
Formerly developmental type TA09770.
Ordering Information
PART NUMBER
PACKAGE
BRAND
July 1999
File Number
4002.3
Features
• 14A, 60V
• rDS(ON) = 0.100Ω
• Temperature Compensating PSPICE® Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• 175oC Operating Temperature
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D
RFP14N06
TO-220AB
RFP14N06
NOTE: When ordering, use the entire part number.
G
S
Packaging
TO-220AB
SOURCE
DRAIN
GATE
DRAIN (FLANGE)
4-492
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures
PSPICE® is a registered trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
RFP14N06
Absolute Maximum Ratings
TC = 25oC Unless Otherwise Specified
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Linear Derating Factor Above TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg
RFP14N06
60
60
±20
14
Refer to Peak Current Curve
Refer to UIS Curve
48
0.32
-55 to 175
UNITS
V
V
V
A
300
260
oC
oC
W
W/oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
Electrical Specifications
TC = 25oC, Unless Otherwise Specified
MIN
TYP
MAX
UNITS
Drain to Source Breakdown Voltage
PARAMETER
SYMBOL
BVDSS
ID = 250µA, VGS = 0V (Figure 11)
60
-
-
V
Gate Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA, (Figure 10)
2
-
4
V
VDS = Rated BVDSS, VGS = 0V
-
-
1
µA
VDS = 0.8 x Rated BVDSS, VGS = 0V, TC = 150oC
-
-
25
µA
Zero Gate Voltage Drain Current
IDSS
VGS = ±20V
-
-
±100
nA
rDS(ON)
ID = 14A, VGS = 10V, (Figure 9)
-
-
0.100
Ω
tON
VDD =30V, ID = 7A, RL = 4.3Ω,
VGS = 10V, RGS = 25Ω
(Figure 13)
-
-
60
ns
Gate to Source Leakage Current
Drain to Source On Resistance (Note 2)
IGSS
Turn-On Time
Turn-On Delay Time
td(ON)
-
14
-
ns
tr
-
26
-
ns
td(OFF)
-
45
-
ns
tf
-
17
-
ns
tOFF
-
-
100
ns
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
Total Gate Charge
TEST CONDITIONS
Qg(TOT)
VGS = 0V to 20V
Gate Charge at 10V
Qg(10)
VGS = 0V to 10V
Threshold Gate Charge
Qg(TH)
VGS = 0V to 2V
VDD = 48V, ID = 14A,
RL = 3.42Ω,
IG(REF) = 0.4mA
(Figure 13)
-
-
40
nC
-
-
25
nC
-
-
1.5
nC
-
570
-
pF
Input Capacitance
CISS
Output Capacitance
COSS
-
185
-
pF
Reverse Transfer Capacitance
CRSS
-
50
-
pF
Thermal Resistance Junction to Case
RθJC
-
-
3.125
oC/W
Thermal Resistance Junction to Ambient
RθJA
-
-
62
oC/W
VDS = 25V, VGS = 0V, f = 1MHz
(Figure 12)
TO-220AB
Source to Drain Diode Specifications
PARAMETER
SYMBOL
Source to Drain Diode Voltage
VSD
Diode Reverse Recovery Time
trr
MIN
TYP
MAX
UNITS
ISD = 14A
TEST CONDITIONS
-
-
1.5
V
ISD = 14A, dISD/dt = 100A/µs
-
-
125
ns
NOTES:
2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%.
3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3) and Peak Current
Capability Curve (Figure 5).
4-493
RFP14N06
Typical Performance Curves
Unless Otherwise Specified
POWER DISSIPATION MULTIPLIER
1.2
16
ID, DRAIN CURRENT (A)
1.0
0.8
0.6
0.4
12
8
4
0.2
0
0
25
50
75
100
125
150
0
175
25
50
TC , CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
75
100
125
TC, CASE TEMPERATURE (oC)
150
175
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
ZθJC, NORMALIZED
THERMAL IMPEDANCE
1
0.5
0.2
0.1
0.1
PDM
0.05
0.02
0.01
t1
t2
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
0.01
10-5
10-4
10-2
10-1
10-3
t, RECTANGULAR PULSE DURATION (s)
100
101
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
TC = 25oC
TJ = MAX RATED
SINGLE PULSE
100µs
10
1ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
1
1
10ms
100ms
DC
10
100
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
4-494
200
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
IDM, PEAK CURRENT (A)
ID, DRAIN CURRENT (A)
100
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
100
175 – T C
I = I 25 ---------------------
150
VGS = 10V
TC = 25oC
VGS = 20V
10
10-5
10-4
10-3
10-2
10-1
t, PULSE WIDTH (s)
100
FIGURE 5. PEAK CURRENT CAPABILITY
101
RFP14N06
Typical Performance Curves
Unless Otherwise Specified (Continued)
35
VGS = 20V
30 VGS = 10V
ID, DRAIN CURRENT (A)
IAS, AVALANCHE CURRENT (A)
50
STARTING TJ = 25oC
10
STARTING TJ = 150oC
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
0.01
VGS = 7V
20
15
VGS = 6V
10
VGS = 5V
5
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS-VDD) +1]
1
VGS = 8V
25
PULSE DURATION = 250µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
VGS = 4.5V
0.1
1
tAV, TIME IN AVALANCHE (ms)
0
10
6
2
4
VDS , DRAIN TO SOURCE VOLTAGE (V)
0
8
NOTE: Refer to Intersil Application Notes AN9321 and AN9322
35
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
30
FIGURE 7. SATURATION CHARACTERISTICS
2.5
25oC
-55oC
175oC
25
20
15
10
5
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
IDS(ON), DRAIN TO SOURCE CURRENT (A)
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
2.0
1.5
1.0
0.5
0
-80
0
0
2
4
6
8
VGS, GATE TO SOURCE VOLTAGE (V)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 10V, ID = 14A
10
2.0
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
NORMALIZED GATE
THRESHOLD VOLTAGE
VGS = VDS, ID = 250µA
1.5
1.0
0.5
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
200
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
4-495
40
80
120
160
200
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
2.0
-40
0
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 8. TRANSFER CHARACTERISTICS
0
-80
-40
ID = 250µA
1.5
1.0
0.5
0
-80
-40
0
40
80
120
160
200
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
RFP14N06
Unless Otherwise Specified (Continued)
700
VDS, DRAIN TO SOURCE VOLTAGE (V)
60
CISS
C, CAPACITANCE (pF)
600
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
500
400
COSS
300
200
CRSS
100
VDD = BVDSS
5
10
15
20
VDS, DRAIN TO SOURCE VOLTAGE (V)
VDD = BVDSS
45
7.5
30
5.0
0.75 BVDSS
0.50 BVDSS
0.25 BVDSS
15
2.5
RL = 4.28Ω
IG(REF) = 0.4mA
VGS = 10V
0
0
0
10
0
25
20
IG(REF)
t, TIME (µs)
IG(ACT)
80
VGS, GATE TO SOURCE VOLTAGE (V)
Typical Performance Curves
IG(REF)
IG(ACT)
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
Test Circuits and Waveforms
VDS
BVDSS
L
tP
VARY tP TO OBTAIN
REQUIRED PEAK IAS
+
RG
VDS
IAS
VDD
VDD
-
VGS
DUT
tP
0V
IAS
0
0.01Ω
tAV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
tON
tOFF
td(ON)
VDS
td(OFF)
tf
tr
VDS
90%
90%
RL
VGS
+
DUT
RGS
VGS
-
VDD
90%
VGS
0
FIGURE 16. SWITCHING TIME TEST CIRCUIT
4-496
10%
10%
0
10%
50%
50%
PULSE WIDTH
FIGURE 17. RESISTIVE SWITCHING WAVEFORMS
RFP14N06
Test Circuits and Waveforms
(Continued)
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 20V
VGS
Qg(10)
+
VDD
DUT
Ig(REF)
VGS = 10V
VGS
-
VGS = 2V
0
Qg(TH)
Ig(REF)
0
FIGURE 18. GATE CHARGE TEST CIRCUIT
4-497
FIGURE 19. GATE CHARGE WAVEFORM
RFP14N06
PSPICE Electrical Model
.SUBCKT RFP14N06 2 1 3 ;
rev 9/12/94
CA 12 8 8.84e-10
CB 15 14 9.34e-10
CIN 6 8 5.2e-10
DPLCAP
RSCL1
+ 51
5
51
ESG
+
IT 8 17 1
GATE
9
1
LGATE
20
EVTO
+ 18
6
8
ESCL
17
EBREAK
18
VTO
-
+
21
6
S1A
S1B
S2A
S2B
DBODY
-
CIN
8
S1A
RSOURCE
7
LSOURCE
3
SOURCE
S2A
14
13
13
8
S1B
RBREAK
15
17
18
S2B
13
RVTO
CB
CA
MOS2
+
MOS1
MOS1 16 6 8 8 MOSMOD M = 0.99
MOS2 16 21 8 8 MOSMOD M = 0.01
12
11
RDRAIN
16
8
RGATE
DBREAK
50
RIN
RBREAK 17 18 RBKMOD 1
RDRAIN 50 16 RDSMOD 2.2e-3
RGATE 9 20 5.64
RIN 6 8 1e9
RSCL1 5 51 RSCLMOD 1e-6
RSCL2 5 50 1e3
RSOURCE 8 7 RDSMOD 42.3e-3
RVTO 18 19 RVTOMOD 1
DRAIN
2
LDRAIN
RSCL2
EBREAK 11 7 17 18 62.87
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTO 20 6 18 8 1
LDRAIN 2 5 1e-9
LGATE 1 9 4.34e-9
LSOURCE 3 7 3.79e-9
5
10
DBODY 7 5 DBDMOD
DBREAK 5 11 DBKMOD
DPLCAP 10 5 DPLCAPMOD
+
EGS
-
6
8
+
EDS
-
14
5
8
IT
19
VBAT
+
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
VBAT 8 19 DC 1
VTO 21 6 0.82
ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/50,6))}
.MODEL DBDMOD D (IS = 1.5e-13 RS = 10.9e-3 TRS1 = 2.3e-3 TRS2 = -1.75e-5 CJO = 6.84e-10 TT = 4.2e-8)
.MODEL DBKMOD D (RS = 4.15e-1 TRS1 = 3.73e-3 TRS2 = -3.21e-5)
.MODEL DPLCAPMOD D (CJO = 26.2e-11 IS = 1e-30 N = 10)
.MODEL MOSMOD NMOS (VTO = 3.91 KP = 12.68 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL RBKMOD RES (TC1 = 7.73e-4 TC2 = 2.12e-6)
.MODEL RDSMOD RES (TC1 = 5.0e-3 TC2 = 2.53e-5)
.MODEL RSCLMOD RES (TC1 = 2.05e-3 TC2 = 1.35e-5)
.MODEL RVTOMOD RES (TC1 = -4.44e-3 TC2 = -6.45e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.29 VOFF= -3.29)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.29 VOFF= -5.29)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.25 VOFF= 2.75)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.75 VOFF= -2.25)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; written by William J. Hepp and C. Frank Wheatley.
4-498
RFP14N06
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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4-499
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