RFG40N10LE, RFP40N10LE, RF1S40N10LESM
Data Sheet
October 1999
40A, 100V, 0.040 Ohm, Logic Level
N-Channel Power MOSFETs
File Number
4061.5
Features
• 40A, 100V
These N-Channel enhancement mode power MOSFETs are
manufactured using the latest manufacturing process
technology. This process, which uses feature sizes
approaching those of LSI integrated circuits gives optimum
utilization of silicon, resulting in outstanding performance.
They were designed for use in applications such as
switching regulators, switching converters, motor drivers and
relay drivers. These transistors can be operated directly from
integrated circuits.
• rDS(ON) = 0.040Ω
• Temperature Compensating PSPICE® Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• 175oC Operating Temperature
Formerly developmental type TA49163.
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Ordering Information
Symbol
PART NUMBER
PACKAGE
BRAND
RFG40N10LE
TO-247
FG40N10L
RFP40N10LE
TO-220AB
FP40N10L
RF1S40N10LESM
TO-263AB
F40N10LE
D
G
NOTE: When ordering, use the entire part number. Add the suffix, 9A, to
obtain the TO-263AB variant in tape and reel, i.e. RF1S40N10LESM9A.
S
Packaging
JEDEC STYLE TO-247
JEDEC TO-220AB
SOURCE
DRAIN
GATE
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
DRAIN (FLANGE)
JEDEC TO-263AB
DRAIN
(FLANGE)
GATE
SOURCE
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE® is a registered trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
RFG40N10LE, RFP40N10LE, RF1S40N10LESM
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified
Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Gate to Source Voltage (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
Single Pulse Avalanche Energy Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS
Power Dissipation (Figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg
RFG40N10LE, RFP40N10LE,
RF1S40N10LESM
100
100
±10
40
Refer to Peak Current Curve
Refer to UIS Curve
150
1.00
-55 to 175
UNITS
V
V
V
A
W
W/oC
oC
oC
oC
300
260
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
TC = 25oC, Unless Otherwise Specified
Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
100
-
-
V
VGS = VDS, ID = 250µA (Figure 12)
1
-
3
V
VDS = 95V, VGS = 0V
-
-
1
µA
VDS = 90V, VGS = 0V, TC = 150oC
-
-
250
µA
VGS = ±10V
-
-
10
µA
ID = 40A, VGS = 5V
-
-
0.040
Ω
VDD = 50V, ID = 40A, RL = 1.25Ω,
VGS = 5V, RGS = 2.5Ω
(Figures 10, 18, 19)
-
-
200
ns
-
22
-
ns
Drain to Source Breakdown Voltage
BVDSS
ID = 250µA, VGS = 0V (Figure 13)
Gate Threshold Voltage
VGS(TH)
Zero Gate Voltage Drain Current
IDSS
Gate to Source Leakage Current
IGSS
Drain to Source On Resistance (Note 2)
rDS(ON)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
tr
-
140
-
ns
td(OFF)
-
70
-
ns
tf
-
65
-
ns
tOFF
-
-
165
ns
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
Total Gate Charge
Qg(TOT)
VGS = 0V to 10V
Gate Charge at 5V
Qg(5)
VGS = 0V to 5V
Qg(TH)
VGS = 0V to 1V
Threshold Gate Charge
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VDD = 80V,
ID = 40A,
RL = 2.0Ω
(Figures 20, 21)
VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 14)
-
145
180
nC
-
85
105
nC
-
3
4
nC
-
3000
-
pF
-
500
-
pF
-
200
-
pF
Thermal Resistance Junction-to-Case
RθJC
All Packages
-
-
1.0
oC/W
Thermal Resistance Junction-to-Ambient
RθJA
TO-247
-
-
30
oC/W
TO-220AB and TO-263AB
-
-
80
oC/W
Source to Drain Diode Specifications
PARAMETER
SYMBOL
Source to Drain Diode Voltage
VSD
Diode Reverse Recovery Time
trr
MIN
TYP
MAX
UNITS
ISD = 40A
TEST CONDITIONS
-
-
1.5
V
ISD = 40A, dISD/dt = 100A/µs
-
-
205
ns
NOTES:
2. Pulse test: pulse width ≤ 80µs, duty cycle ≤ 2%.
3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3).
2
RFG40N10LE, RFP40N10LE, RF1S40N10LESM
Unless Otherwise Specified
1.2
50
1.0
40
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
Typical Performance Curves
0.8
0.6
0.4
0.2
30
20
10
0
0
0
125
50
75
100
TC , CASE TEMPERATURE (oC)
25
25
175
150
50
75
100
125
175
150
TC, CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
ZθJC, NORMALIZED
THERMAL IMPEDANCE
1
0.5
0.2
0.1
0.1
PDM
0.05
t1
t2
0.02
0.01
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
SINGLE PULSE
0.01
10-5
10-4
10-3
10-2
10-1
t, RECTANGULAR PULSE DURATION (s)
100
101
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
TC = 25oC
TJ = 175oC
100
100µs
1ms
10
10ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
1
1
10
100
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
3
200
500
IDM, PEAK CURRENT CAPABILITY (A)
ID, DRAIN CURRENT (A)
500
VGS = 10V
VGS = 5V
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
175 – TC
I = I 25 ----------------------
150
100
THERMAL IMPEDANCE
MAY LIMIT CURRENT
IN THIS REGION
TC = 25oC
10
10-5
10-4
10-3
10-2
10-1
t, PULSE WIDTH (s)
100
FIGURE 5. PEAK CURRENT CAPABILITY
101
RFG40N10LE, RFP40N10LE, RF1S40N10LESM
Typical Performance Curves
Unless Otherwise Specified (Continued)
80
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
100
ID, DRAIN CURRENT (A)
IAS, AVALANCHE CURRENT (A)
500
STARTING TJ = 25oC
10
STARTING TJ = 150oC
VGS = 10V
VGS = 5V
VGS = 4V
60
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
40
VGS = 3V
20
VGS = 2.5V
1
0.001
0.01
0.1
1
0
10
0
1.5
tAV, TIME IN AVALANCHE (ms)
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
VDD = 15V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
60
-55oC
ID = 40A
ID = 10A
175oC
20
ID = 80A
75
50
ID = 20A
25
PULSE DURATION = 80µs, VDD = 15V
DUTY CYCLE = 0.5% MAX.
0
0
1.5
3.0
4.5
6.0
2.0
2.5
VGS, GATE TO SOURCE VOLTAGE (V)
700
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
tr
400
tf
300
200
td(ON)
100
0
0
10
20
30
40
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 10. SWITCHING TIME vs GATE RESISTANCE
4
4.5
5.0
2.50
600
500
4.0
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
td(OFF)
VDD = 50V, ID = 40A, RL= 1.25Ω
3.5
3.0
VGS, GATE TO SOURCE VOLTAGE (V)
FIGURE 8. TRANSFER CHARACTERISTICS
SWITCHING TIME (ns)
6.0
100
25oC
40
0
4.5
FIGURE 7. SATURATION CHARACTERISTICS
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
IDS(ON), DRAIN TO SOURCE CURRENT (A)
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
80
3.0
VDS, DRAIN TO SOURCE VOLTAGE (V)
50
2.00
PULSE DURATION = 80µs,
DUTY CYCLE = 0.5% MAX.
VGS = 5V, ID = 40A
1.50
1.00
0.50
0
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
200
RFG40N10LE, RFP40N10LE, RF1S40N10LESM
Typical Performance Curves
Unless Otherwise Specified (Continued)
1.50
1.50
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
1.25
1.00
0.75
0.50
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
CISS
C, CAPACITANCE (pF)
2800
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
2100
1400
COSS
700
CRSS
5
10
15
20
0.75
-40
160
0
40
80
120
TJ , JUNCTION TEMPERATURE (oC)
200
5.00
100
0
0
1.00
FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
VDS , DRAIN TO SOURCE VOLTAGE (V)
3500
1.25
0.50
-80
200
ID = 250µA
VDD = BVDSS
VDD = BVDSS
75
3.75
RL = 2.5Ω
IG(REF) = 1.7mA
VGS = 5V
50
25
25
1.25
0
0
I G ( REF )
20 ---------------------I G ( ACT )
VDS, DRAIN TO SOURCE VOLTAGE (V)
2.50
PLATEAU VOLTAGES IN
DESCENDING ORDER:
VDD = BVDSS
VDD = 0.75 BVDSS
VDD = 0.50 BVDSS
VDD = 0.25 BVDSS
VGS , GATE TO SOURCE VOLTAGE (V)
NORMALIZED GATE
THRESHOLD VOLTAGE
VGS = VDS, ID = 250µA
I G ( REF )
80 ---------------------I G ( ACT )
t, TIME (µs)
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 15. SWITCHING WAVEFORMS FOR CONSTANT GATE
CURRENT
Test Circuits and Waveforms
VDS
BVDSS
L
VARY tP TO OBTAIN
REQUIRED PEAK IAS
tP
+
RG
VDS
IAS
VDD
VDD
-
VGS
DUT
0V
tP
IAS
0
0.01Ω
tAV
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
5
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
RFG40N10LE, RFP40N10LE, RF1S40N10LESM
Test Circuits and Waveforms
(Continued)
tON
tOFF
td(ON)
VDS
td(OFF)
tf
tr
VDS
90%
90%
RL
VGS
+
-
DUT
10%
10%
0
VDD
90%
RGS
VGS
VGS
0
10%
FIGURE 18. SWITCHING TIME TEST CIRCUIT
50%
50%
PULSE WIDTH
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
VDS
VDD
RL
Qg(TOT)
VDS
Qg(10) OR Qg(5)
VGS
+
VDD
VGS
DUT
Ig(REF)
VGS = 2V
0
VGS = 1V FOR
L2 DEVICES
Qg(TH)
VGS = 20V
VGS = 10V FOR
L2 DEVICES
VGS = 10V
VGS = 5V FOR
L2 DEVICES
Ig(REF)
0
FIGURE 20. GATE CHARGE TEST CIRCUIT
6
FIGURE 21. GATE CHARGE WAVEFORMS
RFG40N10LE, RFP40N10LE, RF1S40N10LESM
PSPICE Electrical Model
SUBCKT 40N10LE 2 1 3 ;
rev 8/15/95
CA 12 8 3.50e-9
CB 15 14 3.50e-9
CIN 6 8 1.70e-9
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
LDRAIN
DPLCAP
DRAIN
2
5
10
5
51
ESLC
11
-
RDRAIN
6
8
EVTHRES
+ 19 8
+
LGATE
GATE
1
EVTEMP
RGATE +
18 22
9
20
21
DBODY
-
16
MWEAK
6
MMED
MSTRO
RLGATE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
+
17
EBREAK 18
50
-
IT 8 17 1
LSOURCE
CIN
8
SOURCE
3
7
RSOURCE
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 2.04e-2
RGATE 9 20 2.15
RLDRAIN 2 5 10
RLGATE 1 9 51.7
RLSOURCE 3 7 21.3
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 4.85e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
S1B
S2A
S2B
DBREAK
+
RSLC2
ESG
LDRAIN 2 5 1.00e-9
LGATE 1 9 5.17e-9
LSOURCE 3 7 2.13e-9
RLDRAIN
RSLC1
51
EBREAK 11 7 17 18 120.7
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
RLSOURCE
S2A
S1A
12
S1B
CA
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
VBAT
5
8
EDS
-
-
IT
14
+
+
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
RBREAK
15
14
13
13
8
-
+
8
22
RVTHRES
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*79),3.5))}
.MODEL DBODYMOD D (IS = 1.96e-12 RS = 3.87e-3 TRS1 = 9.93e-4 TRS2 = 4.97e-6 CJO = 1.53e-9 TT = 7.41e-8 M = 0.50)
.MODEL DBREAKMOD D (RS = 3.12e-1 TRS1 = 1.07e-3 TRS2 = 0)
.MODEL DPLCAPMOD D (CJO = 1.97e-9 IS = 1e-30 M = 0.87)
.MODEL MMEDMOD NMOS (VTO = 1.73 KP = 2.80 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.15)
.MODEL MSTROMOD NMOS (VTO = 2.04 KP = 80 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.50 KP = 0.10 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 21.5 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 9.74e-4 TC2 = -3.71e-7)
.MODEL RDRAINMOD RES (TC1 = 9.71e-3 TC2 = 2.90e-5)
.MODEL RSLCMOD RES (TC1 = 2.17e-3 TC2 = 1.27e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 0)
.MODEL RVTHRESMOD RES (TC1 = -2.08e-3 TC2 = -6.82e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.52e-3 TC2 = -1.21e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = -6.00 VOFF= -1.50)
VON = -1.50 VOFF= -6.00)
VON = -0.50 VOFF= 0.0)
VON = 0.0 VOFF= -0.50)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
7
RFG40N10LE, RFP40N10LE, RF1S40N10LESM
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
8
ASIA
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029