RFG45N06, RFP45N06, RF1S45N06SM Data Sheet July 1999 45A, 60V, 0.028 Ohm, N-Channel Power MOSFETs 3574.4 Features • 45A, 60V These are N-Channel enhancement mode silicon gate power field effect transistors. They are advanced power MOSFETs designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. Formerly developmental type TA49028. • rDS(ON) = 0.028Ω • Temperature Compensating PSPICE® Model • Peak Current vs Pulse Width Curve • UIS Rating Curve • 175oC Operating Temperature • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Symbol Ordering Information PART NUMBER File Number DRAIN PACKAGE BRAND RFG45N06 TO-247 RFG45N06 RFP45N06 TO-220AB RFP45N06 RF1S45N06SM TO-263AB F1S45N06 GATE NOTE: When ordering, use the entire part number. Add the suffix, 9A, to obtain the TO-263AB variant in tape and reel, i.e. RF1S45N06SM9A. SOURCE Packaging JEDEC STYLE TO-247 JEDEC TO-220AB SOURCE DRAIN GATE DRAIN (FLANGE) DRAIN (BOTTOM SIDE METAL) SOURCE DRAIN GATE JEDEC TO-263AB DRAIN (FLANGE) GATE SOURCE 4-455 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. PSPICE® is a registered trademark of MicroSim Corporation. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 RFG45N06, RFP45N06, RF1S45N06SM Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified RFG45N06, RFP45N06 RF1S45N06SM 60 60 45 Refer to Peak Current Curve ±20 Refer to UIS Curve 131 0.877 -55 to 175 Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RG = 20KΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg UNITS V V A V W W/oC oC oC oC 300 260 CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V (Figure 11) 60 - - V Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 10) 2 - 4 V VDS = Rated BVDSS, VGS = 0V - - 1 µA - - 25 µA Zero Gate Voltage Drain Current IDSS VDS = 0.8 x Rated BVDSS, VGS Gate to Source Leakage Current Drain Source On Resistance (Note 2) IGSS rDS(ON) Turn-On Time tON Turn-On Delay Time td(ON) Rise Time Turn-Off Delay Time VGS = ±20V - - ±100 nA ID = 45A, VGS = 10V (Figure 9) - - 0.028 Ω VDD = 30V, ID = 45A RL = 0.667Ω, VGS = +10V RG = 3.6Ω (Figure 13) - - 120 ns - 12 - ns tr - 74 - ns td(OFF) - 37 - ns tf - 16 - ns tOFF - - 80 ns - 125 150 nC - 67 80 nC - 3.7 4.5 nC - 2050 - pF - 600 - pF - 200 - pF Fall Time Turn-Off Time Total Gate Charge = 0V (125oC) Qg(TOT) VGS = 0 to 20V Gate Charge at 10V Qg(10) VGS = 0 to 10V Threshold Gate Charge Qg(TH) VGS = 0 to 2V Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS VDD = 48V, ID = 45A, RL = 1.07Ω Ig(REF) = 1.5mA (Figure 13) VDS = 25V, VGS = 0V f = 1MHz (Figure 12) Thermal Resistance Junction to Case RθJC - - 1.14 oC/W Thermal Resistance Junction to Ambient RθJA - - 80 oC/W Source to Drain Diode Specifications PARAMETER SYMBOL Source to Drain Diode Voltage VSD Diode Reverse Recovery Time trr TEST CONDITIONS MIN TYP MAX UNITS ISD = 45A - - 1.5 V ISD = 45A, dISD/dt = 100A/µs - - 125 ns NOTES: 2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3) and Peak Current Capability Curve (Figure 5). 4-456 RFG45N06, RFP45N06, RF1S45N06SM Typical Performance Curves Unless Otherwise Specified 50 1.0 ID , DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 0.8 0.6 0.4 0.2 40 30 20 10 0 0 0 25 50 75 100 125 150 175 25 50 TC , CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE ZθJC, NORMALIZED TRANSIENT THERMAL IMPEDANCE 75 100 125 150 175 TC , CASE TEMPERATURE (oC) FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 1 0.5 PDM 0.2 0.1 0.1 t1 0.05 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC 0.02 0.01 SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 10-1 t, RECTANGULAR PULSE DURATION (s) 100 101 FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 100 100µs 1ms 10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1 103 TJ = MAX RATED SINGLE PULSE TC = 25oC 10ms VDSS(MAX) = 60V 1 FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT CAPABILITY AS FOLLOWS: VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA 100 175 – T C I = I 25 ------------------------ 150 VGS = 20V VGS = 10V TC = 25oC 102 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 100ms DC 10 4-457 IDM , PEAK CURRENT (A) ID , DRAIN CURRENT (A) 400 40 10-3 10-2 10-1 100 101 102 t, PULSE WIDTH (ms) 103 FIGURE 5. PEAK CURRENT CAPABILITY 104 RFG45N06, RFP45N06, RF1S45N06SM Typical Performance Curves Unless Otherwise Specified (Continued) 125 300 100 ID , DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) VGS = 10V STARTING TJ = 25oC STARTING TJ = 150oC 10 If R = 0 tAV = (L) (IAS) / (1.3 RATED BVDSS - VDD) 0.1 VGS = 7V 100 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX TC = 25oC 75 50 VGS = 6V 25 VGS = 5V If R ≠ 0 tAV = (L/R) ln [(IAS*R) / (1.3 RATED BVDSS - VDD) + 1] 1 0.01 VGS = 8V VGS = 4.5V 1 0 10 0 1.5 3 4.5 6 7.5 VDS, DRAIN TO SOURCE VOLTAGE (V) tAV, TIME IN AVALANCHE (ms) NOTE: Refer to Intersil Application Notes AN9321 and AN9322. 125 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDD = 15V 100 FIGURE 7. SATURATION CHARACTERISTICS 2.5 25oC -55oC NORMALIZED DRAIN TO SOURCE ON RESISTANCE IDS(ON) , DRAIN TO SOURCE CURRENT (A) FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING 175oC 75 50 25 2 1.5 1 0.5 0 0 1 2 3 4 5 6 7 8 9 PULSE DURATION = 80µs DUTY CYCLE = 0.5%MAX VGS = 10V, ID = 45A 0 -80 10 -40 FIGURE 8. TRANSFER CHARACTERISTICS 1.0 0.5 0 120 160 200 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC) FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 4-458 ID = 250µA BREAKDOWN VOLTAGE 1.5 -40 80 2.0 VGS = VDS, ID = 250µA 0 -80 40 FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE NORMALIZED DRAIN TO SOURCE NORMALIZED GATE THRESHOLD VOLTAGE 2.0 0 TJ, JUNCTION TEMPERATURE (oC) VGS , GATE TO SOURCE VOLTAGE (V) 1.5 1.0 0.5 0 -80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC) FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE RFG45N06, RFP45N06, RF1S45N06SM Typical Performance Curves Unless Otherwise Specified (Continued) CISS 2000 COSS 1000 CRSS VDD = BVDSS 7.5 5.0 30 0.75 BVDSS 0.75 BVDSS 0.50 BVDSS 0.50 BVDSS 0.25 BVDSS 0.25 BVDSS 15 5 10 15 20 2.5 RL = 1.33Ω IG(REF) = 1.5mA VGS = 10V 0 0 0 VDD = BVDSS 45 VGS, GATE TO SOURCE VOLTAGE (V) VDS, DRAIN TO SOURCE VOLTAGE (V) C, CAPACITANCE (pF) VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGD 3000 0 10 60 4000 25 20 VDS , DRAIN TO SOURCE VOLTAGE (V) IG(REF) t, TIME (µs) IG(ACT) 80 IG(REF) IG(ACT) NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT Test Circuits and Waveforms VDS BVDSS L tP VARY tP TO OBTAIN REQUIRED PEAK IAS + RG VDS IAS VDD VDD - VGS DUT tP 0V IAS 0 0.01Ω tAV FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(ON) td(OFF) tf tr RL VDS 90% 90% + RG - VDD 10% 10% 0 DUT 90% VGS VGS 0 FIGURE 16. SWITCHING TIME TEST CIRCUIT 4-459 10% 50% 50% PULSE WIDTH FIGURE 17. RESISTIVE SWITCHING WAVEFORMS RFG45N06, RFP45N06, RF1S45N06SM Test Circuits and Waveforms VDS VDD RL Qg(TOT) VDS VGS = 20V VGS Qg(10) + VDD DUT Ig(REF) VGS = 10V VGS - VGS = 2V 0 Qg(TH) Ig(REF) 0 FIGURE 18. GATE CHARGE TEST CIRCUIT 4-460 FIGURE 19. GATE CHARGE WAVEFORMS RFG45N06, RFP45N06, RF1S45N06SM PSPICE Electrical Model .SUBCKT RFP45N06 2 1 3 REV 1/18/93 *NOM TEMP = +25oC DRAIN 2 LDRAIN 5 10 DPLCAP ESG + DBREAK EVTO GATE 9 1 LGATE 20 + DBODY 7 5 DBDMOD DBREAK 5 11DBKMOD DPLCAP 10 5 DPLCAPMOD RGATE 18 8 - VTO 16 6 MOS1 S1A IT 8 17 1 13 8 S1B + EGS 6 - 8 17 18 CIN RSOURCE 7 LSOURCE S2A 14 13 15 17 RBREAK S2B 13 CA LDRAIN 2 5 1E-9 LGATE 1 9 5.65E-9 LSOURCE 3 7 4.13E-9 + 11 EBREAK 8 12 DBODY MOS2 21 RIN EBREAK 11 7 17 18 66.5 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTO 20 6 18 8 1 RDRAIN 6 8 + CA 12 8 3.49E-9 CB 15 14 3.8E-9 CIN 6 8 2E-9 3 SOURCE 18 RVTO CB 14 + 5 EDS 8 - IT 19 - VBAT + MOS1 16 6 8 8 MOSMOD M=0.99 MOS2 16 21 8 8 MOSMOD M=0.01 RBREAK 17 18 RBKMOD 1 RDRAIN 5 16 RDSMOD 3.58E-3 RGATE 9 20 0.681 RIN 6 8 1E9 RSOURCE 8 7 RDSMOD 13.6E-3 RVTO 18 19 RVTOMOD 1 S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 8 19 DC 1 VTO 21 6 0.92 .MODEL DBDMOD D (IS=8.2E-13 RS=7.86E-3 TRS1=2.26E-3 TRS2=2.90E-6 CJO=2.07E-9 TT=5.72E-8) .MODEL DBKMOD D (RS=1.93E-1 TRS1=5.13E-4 TRS2=-2.15E-5) .MODEL DPLCAPMOD D (CJO=1.25E-9 IS=1E-30 N=10) .MODEL MOSMOD NMOS (VTO=3.862 KP=55.57 IS=1E-30 N=10 TOX=1 L=1U W=1U) .MODEL RBKMOD RES (TC1=1.12E-3 TC2=-5.18E-7) .MODEL RDSMOD RES (TC1=4.64E-3 TC2=1.58E-5) .MODEL RVTOMOD RES (TC1=-4.27E-3 TC2=-6.55E-6) .MODEL S1AMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-6.5 VOFF=-1.7) .MODEL S1BMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-1.7 VOFF=-6.5) .MODEL S2AMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-3.0 VOFF=2) .MODEL S2BMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=2.0 VOFF=-3.0) .ENDS NOTE: For further discussion of the PSPICE model consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; authors, William J. Hepp and C. Frank Wheatley. 4-461 RFG45N06, RFP45N06, RF1S45N06SM All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. 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