INTERSIL ISL70227SRHF

36V Rad Hard Dual Precision Operational Amplifier
ISL70227SRH
Features
The ISL70227SRH is a high precision dual operational
amplifier featuring very low noise, low offset voltage, low input
bias current and low temperature drift. These features plus its
radiation tolerance make the ISL70227SRH the ideal choice
for applications requiring both high DC accuracy and AC
performance. The combination of precision, low noise, and
small footprint provides the user with outstanding value and
flexibility relative to similar competitive parts.
• Wide Supply Range . . . . . . . . . . . . . . . . . . . .4.5V to 36V Max.
• Very Low Voltage Noise . . . . . . . . . . . . . . . . . .2.5nV/√Hz, Typ.
Applications for these amplifiers include precision and
analytical instrumentation, active filters, precision power
supply controls, and industrial controls.
The ISL70227SRH is available in a 10 Ld hermetic ceramic
flatpack and operates over the extended temperature range of
-55°C to +125°C.
Applications
• Gain-bandwidth Product . . . . . . . . . . . . . . . . . . . . . . . . 10MHz
• Superb Offset Drift . . . . . . . . . . . . . . . . . . . . . . . . 1µV/°C, Max
• Operating Temperature Range. . . . . . . . . . . . -55°C to +125°
• Low Input Voltage Offset . . . . . . . . . . . . . . . . . . . . . . 10µV, Typ.
• Input Bias Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1nA, Typ.
• Unity Gain Stable
• No Phase Reversal
• Radiation Tolerance
- High Dose Rate. . . . . . . . . . . . . . . . . . . . . . . . . . 100krad(Si)
- Low Dose Rate . . . . . . . . . . . . . . . . . . . . . . . . . . 100krad(Si)
- SEL/SEB LETTH . . . . . . . . . . . . . . . . . . . . . . 86MeV/mg/cm2
Related Literature
• Precision Instruments
• Industrial Controls
• See AN1669, “ISL70227SRH Evaluation Board User’s
Guide”
• Active Filter Blocks
• Data Acquisition
• Power Supply Control
0
C1
-5
1.5nF
V+
-
VIN
R1
ISL70227SRH
R2
-15
232
68.3nF
C2
-25
V-30
Sallen-Key Low Pass Filter (1MHz)
FIGURE 1. TYPICAL APPLICATION
September 23, 2011
FN7925.1
BIASED
-20
+
95.3
OUTPUT
VOS (µV)
-10
1
GROUNDED
0
10
20
30
40
50
60
70
80
90
100
TOTAL DOSE (krad(Si))
FIGURE 2. OFFSET VOLTAGE vs RADIATION
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL70227SRH
Ordering Information
.
ORDERING NUMBER
PART MARKING
PACKAGE
(Pb-free)
TEMP RANGE (°C)
PKG.
DWG. #
ISL70227SRHMF (Notes 1, 2)
ISL70227 SRHMF
-55 to +125
10 Ld FLATPACK
K10.A
ISL70227SRHF/PROTO (Notes 1, 2)
ISL70227 SRHF/PROTO
-55 to +125
10 Ld FLATPACK
K10.A
ISL70227SRHMX
-55 to +125
DIE
ISL70227SRHX/SAMPLE
-55 to +125
DIE
ISL70227MHEVAL1Z
Evaluation Board
NOTES:
1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations.
2. For Moisture Sensitivity Level (MSL), please see device information page for ISL70227SRH. For more information on MSL please see techbrief TB363.
Pin Configuration
ISL70227SRH
(10 LD FLATPACK)
TOP VIEW
OUTA
1
10
-IN A
2
9
OUT B
8
-IN B
7
+IN B
6
NC
+IN A
3
NC
4
V-
5
- +
+ -
V+
Pin Descriptions
PIN NUMBER
PIN NAME
EQUIVALENT CIRCUIT
DESCRIPTION
3
+IN_A
Circuit 1
Amplifier A non-inverting input
5
V-
Circuit 3
Negative power supply
7
+IN_B
Circuit 1
Amplifier B non-inverting input
8
-IN_B
Circuit 1
Amplifier B inverting input
9
OUT B
Circuit 2
Amplifier B output
10
V+
Circuit 3
Positive power supply
1
OUT A
Circuit 2
Amplifier A output
2
-IN_A
Circuit 1
Amplifier A inverting input
4, 6
NC
-
Not Connected – This pin is not electrically connected internally.
V+
IN-
V+
V-
V-
CIRCUIT 2
2
CAPACITIVELY
TRIGGERED ESD
CLAMP
OUT
IN+
CIRCUIT 1
V+
V-
CIRCUIT 3
FN7925.1
September 23, 2011
ISL70227SRH
Absolute Maximum Ratings
Thermal Information
Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36V
Maximum Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Maximum Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5V
Min/Max Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V
Max/Min Input Current for
Input Voltage >V+ or <V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA
Output Short-Circuit Duration
(1 Output at a Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Indefinite
ESD Tolerance
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 2kV
Machine Model (Tested per EIA/JESD22-A115-A) . . . . . . . . . . . . . . 300V
Charged Device Model (Tested per JESD22-C101D) . . . . . . . . . . . . 750V
Di-electrically Isolated PR40 Process . . . . . . . . . . . . . . . . . . . Latch-up free
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
10 Ld Ceramic Flatpack (Notes 3, 4) . . . . .
130
20
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Recommended Operating Conditions
Ambient Operating Temperature Range . . . . . . . . . . . . . .-55°C to +125°C
Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . .+150°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V (±2.5V) to 30V (±15V)
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
3. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
4. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
VS ±15V, VCM = 0, VO = 0V, RL = Open, TA = +25°C, unless otherwise noted. Boldface limits apply over the
operating temperature range, -55°C to +125°C, and over the radiation tolerance limit with exposure at a high dose rate.
PARAMETER
VOS
DESCRIPTION
CONDITIONS
Offset Voltage
MIN
(Note 5)
TYP
MAX
(Note 5)
UNIT
-75
-10
75
µV
-100
-
100
µV
TCVOS
Offset Voltage Drift
-1
.1
1
µV/°C
IOS
Input Offset Current
-10
1
10
nA
-12
-
12
nA
-10
1
10
nA
-12
-
12
nA
-13
-
13
V
-12
-
12
V
VCM = -13V to +13V
115
120
-
dB
VCM = -12V to +12V
115
-
-
dB
VS = ±2.25V to ±5V
110
117
-
dB
VS = ±3V to ±15V
110
-
-
dB
IB
VCM
CMRR
PSRR
Input Bias Current
Input Voltage Range
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Guaranteed by CMRR
AVOL
Open-Loop Gain
VO = -13V to +13V
RL = 10kΩ to ground
1000
1500
-
V/mV
VOH
Output Voltage High
RL = 10kΩ to ground
13.5
13.65
-
V
13.2
-
-
V
13.4
13.5
-
V
13.1
-
-
V
-
-13.65
-13.5
V
-
-
-13.2
V
-
-13.5
-13.4
V
-
-
-13.1
V
RL = 2kΩ to ground
VOL
Output Voltage Low
RL = 10kΩ to ground
RL = 2kΩ to ground
3
FN7925.1
September 23, 2011
ISL70227SRH
Electrical Specifications
VS ±15V, VCM = 0, VO = 0V, RL = Open, TA = +25°C, unless otherwise noted. Boldface limits apply over the
operating temperature range, -55°C to +125°C, and over the radiation tolerance limit with exposure at a high dose rate. (Continued)
PARAMETER
IS
ISC
VSUPPLY
DESCRIPTION
CONDITIONS
Supply Current/Amplifier
Short-Circuit
RL = 0Ω to ground
Supply Voltage Range
Guaranteed by PSRR
MIN
(Note 5)
TYP
MAX
(Note 5)
-
2.2
2.8
mA
-
-
3.7
mA
-
±45
-
mA
±2.25
-
±15
V
-
10
-
MHz
UNIT
AC SPECIFICATIONS
GBW
Gain Bandwidth Product
enp-p
Voltage Noise
0.1Hz to 10Hz
-
85
-
nVP-P
en
Voltage Noise Density
f = 10Hz
-
3
-
nV/√Hz
en
Voltage Noise Density
f = 100Hz
-
2.8
-
nV/√Hz
en
Voltage Noise Density
f = 1kHz
-
2.5
-
nV/√Hz
en
Voltage Noise Density
f = 10kHz
-
2.5
-
nV/√Hz
in
Current Noise Density
f = 10kHz
-
0.4
-
pA/√Hz
Total Harmonic Distortion + Noise
1kHz, G = 1, VO = 3.5VRMS,
RL = 2kΩ
-
0.00022
-
%
Slew Rate
AV = 10, RL = 2kΩ, VO = 4VP-P
-
±3.6
-
V/µs
Rise Time
10% to 90% of VOUT
AV = -1, VOUT = 100mVP-P,
Rf = Rg = 2kΩ, RL = 2kΩ to VCM
-
36
-
ns
Fall Time
90% to 10% of VOUT
AV = -1, VOUT = 100mVP-P,
Rf = Rg = 2kΩ, RL = 2kΩ to VCM
-
38
-
ns
Settling Time to 0.1%
10V Step; 10% to VOUT
AV = -1, VOUT = 10VP-P,
Rg = Rf = 10k, RL = 2kΩ to VCM
-
3.4
-
µs
Settling Time to 0.01%
10V Step; 10% to VOUT
AV = -1, VOUT = 10VP-P,
RL = 2kΩ to VCM
-
3.8
-
µs
Output Overload Recovery Time
AV = 100, VIN = 0.2V,
RL = 2kΩ to VCM
-
1.7
-
µs
THD + N
TRANSIENT RESPONSE
SR
tr, tf, Small
Signal
ts
tOL
Electrical Specifications
temperature range, -55°C to +125°C.
VS ±5V, VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply over the operating
MIN
(Note 5)
TYP
MAX
(Note 5)
UNIT
Offset Voltage
-
-10
-
µV
TCVOS
Offset Voltage Drift
-
.1
-
µV/°C
IOS
Input Offset Current
-
1
-
nA
IB
Input Bias Current
-
1
-
nA
PARAMETER
VOS
DESCRIPTION
CONDITIONS
CMRR
Common-Mode Rejection Ratio
VCM = -3V to +3V
-
120
-
dB
PSRR
Power Supply Rejection Ratio
VS = ±2.25V to ±5V
-
125
-
dB
AVOL
Open-Loop Gain
VO = -3V to +3V
RL = 10kΩ to ground
-
1500
-
V/mV
VOH
Output Voltage High
RL = 10kΩ to ground
-
3.65
-
V
RL = 2kΩ to ground
-
3.5
-
4
FN7925.1
September 23, 2011
ISL70227SRH
Electrical Specifications
VS ±5V, VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply over the operating
temperature range, -55°C to +125°C. (Continued)
PARAMETER
VOL
DESCRIPTION
Output Voltage Low
MIN
(Note 5)
TYP
MAX
(Note 5)
UNIT
RL = 10kΩ to ground
-
-3.65
-
V
RL = 2kΩ to ground
-
-3.5
-
CONDITIONS
IS
Supply Current/Amplifier
-
2.2
-
mA
ISC
Short-Circuit
-
±45
-
mA
-
10
-
MHz
1kHz, G = 1, Vo = 2.5VRMS,
RL = 2kΩ
-
0.0034
-
%
Slew Rate
AV = 10, RL = 2kΩOH
-
±3.6
-
V/µs
Rise Time
10% to 90% of VOUT
AV = -1, VOUT = 100mVP-P,
Rf = Rg = 2kΩ, RL = 2kΩ to VCM
-
36
-
ns
Fall Time
90% to 10% of VOUT
AV = -1, VOUT = 100mVP-P,
Rf = Rg = 2kΩ, RL = 2kΩ to VCM
-
38
-
ns
Settling Time to 0.1%
AV = -1, VOUT = 4VP-P,
Rf = Rg = 2kΩ, RL = 2kΩ to VCM
-
1.6
-
µs
Settling Time to 0.01%
AV = -1, VOUT = 4VP-P,
Rf = Rg = 2kΩ, RL = 2kΩ to VCM
-
4.2
-
µs
AC SPECIFICATIONS
GBW
THD + N
Gain Bandwidth Product
Total Harmonic Distortion + Noise
TRANSIENT RESPONSE
SR
tr, tf, Small
Signal
ts
NOTE:
5. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
Post Radiation Characteristics
VS ±15V, VCM = 0V, VO = 0V, RL = Open, TA = +25°C, unless otherwise noted. This data is ATE test
data of the ISL70227SRH post radiation exposure at a high dose rate of 50 to 300rad(Si)/s, these are not limits nor are they guaranteed.
PARAMETER
DESCRIPTION
CONDITIONS
50k RAD
75k RAD
100k RAD
UNIT
VOS
Offset Voltage
34
30
30
µV
IOS
Input Offset Current
-1
-1
-2
nA
IB
Input Bias Current
-1
-2
-3
nA
CMRR
Common-Mode Rejection Ration
VCM = -13V to +13V
155
155
155
dB
PSRR
Power Supply Rejection Ratio
VS = ±2.25V to ±15V
116
116
116
dB
AVOL
Open-Loop Gain
VO = -13V to +13V
RL = 10kΩ to ground
3500
3500
3500
V/mV
2.2
2.2
2.2
mA
IS
Supply Current/Amplifier
5
FN7925.1
September 23, 2011
ISL70227SRH
Post Radiation Characteristics
VS ±15V, VCM = 0V, VO = 0V, RL = Open, TA = +25°C, unless otherwise noted. This data
is ATE test data of the ISL70227SRH post radiation exposure at a low dose rate of <10mrad(Si)/s, these are not limits nor are they guaranteed.
15
0
-5
10
IB+ (nA)
VOS (µV)
-10
-15
BIASED
-20
BIASED
5
GROUNDED
0
-25
-30
GROUNDED
0
10
20
30
40
50
60
70
80
90
-5
100
0
10
20
TOTAL DOSE (krad(Si))
30
FIGURE 3. OFFSET VOLTAGE vs RADIATION
50
60
70
80
90
100
FIGURE 4. POSITIVE INPUT BIAS CURRENT vs RADIATION
5
15
10
BIASED
IIO (nA)
IB- (nA)
40
TOTAL DOSE (krad(Si))
5
GROUNDED
0
GROUNDED
0
BIASED
-5
0
10
20
30
40
50
60
70
80
90
-5
100
0
10
20
TOTAL DOSE (krad(Si))
30
40
50
60
70
80
90
100
TOTAL DOSE (krad(Si))
FIGURE 5. NEGATIVE INPUT BIAS CURRENT vs RADIATION
FIGURE 6. OFFSET CURRENT vs RADIATION
SUPPLY CURRENT (mA)
10
BIASED
5
GROUNDED
0
0
10
20
30
40
50
60
70
80
90
100
TOTAL DOSE (krad(Si))
FIGURE 7. TOTAL SUPPLY CURRENT vs RADIATION
6
FN7925.1
September 23, 2011
ISL70227SRH
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified.
100
INPUT NOISE VOLTAGE (nV/√Hz)
INPUT NOISE VOLTAGE (nV)
100
80
60
40
20
0
-20
V+ = 38V
RL = 10k
CL = 3.5pF
Rg = 10, Rf = 100k
AV = 10,000
-40
-60
-80
-100
0
1
2
3
4
5
6
7
8
9
VS = ±19V
AV = 1
10
1
0.1
10
1
10
TIME (s)
FIGURE 8. INPUT NOISE VOLTAGE 0.1Hz TO 10Hz
10
PSRR (dB )
INPUT NOISE CURRENT (pA/√Hz)
VS = ±19V
AV = 1
1
1
10
100
1k
10k
100k
130
120
110
100
90
80
70
60
50
40
30
20
10
0
-10
RL = INF
CL = 5.25pF
AV = +1
VS = 1VP-P
PSRR+ and PSRR- VS = ±15V
10
100
1k
10k
100k
10M
1M
FIGURE 11. PSRR vs FREQUENCY, V S = ±5V, ±15V
VS = ±5V
70
VS = ±2.25V
60
50
VS = ±15V
VOS (µV)
CMRR (dB)
100k
FREQUENCY (Hz)
FIGURE 10. INPUT NOISE CURRENT SPECTRAL DENSITY
RL = INF
CL = 5.25pF
AV = +1
VCM = 1VP-P
100
10k
PSRR+ AND PSRR- VS = ±5V
FREQUENCY (Hz)
130
120
110
100
90
80
70
60
50
40
30
20
10
0
-10
10
1k
FIGURE 9. INPUT NOISE VOLTAGE SPECTRAL DENSITY
100
0.1
0.1
100
FREQUENCY (Hz)
VS = ±15V
40
30
20
10
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 12. CMRR vs FREQUENCY, VS = ±2.25, ±5V, ±15V
7
0
-60
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
140
FIGURE 13. VOS vs TEMPERATURE
FN7925.1
September 23, 2011
ISL70227SRH
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
1.0
0
-0.1
0.8
-0.2
VS = ±15V
-0.3
0.4
IB- (nA)
IB+ (nA)
0.6
VS = ±15V
IB+
0.2
-0.4
-0.5
IB-
-0.6
0
-0.7
-0.2
-0.8
-0.4
-60
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
-0.9
-60
140
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
140
100
120
140
FIGURE 15. IB- vs TEMPERATURE
FIGURE 14. IB+ vs TEMPERATURE
3.5
0
-0.2
3.0
VS = ±15V
2.5
IIO
-0.6
ICC (mA)
IIO (nA)
-0.4
-0.8
VS = ±15V
2.0
1.5
-1.0
1.0
-1.2
0.5
-1.4
-60
-40
-20
0
20
40
60
80
100
120
ICC
0
-60
140
-40
-20
TEMPERATURE (°C)
-12.2
13.1
-12.3
13.0
-12.4
12.6
-12.5
VOH @ RL = 100k
VOUT (V)
VOUT (V)
12.7
VOH @ RL = 2k
-12.6
AV = 10,
VIN = 1.31V
VS = ±15V
12.4
12.3
-40
-20
0
20
40
60
TEMPERATURE (°C)
80
100
FIGURE 18. VOH vs TEMPERATURE, VS = ±15V
8
60
80
120
AV = 10,
VIN = - 1.31V
VS = ±15V
VOL @ RL = 2k
-12.7
-12.8
-12.9
12.5
12.2
-60
40
FIGURE 17. SUPPLY CURRENT vs TEMPERATURE
13.2
12.8
20
TEMPERATURE (°C)
FIGURE 16. IOS vs TEMPERATURE
12.9
0
VOL @ RL = 100k
-13.0
-13.1
-13.2
-60
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 19. VOL vs TEMPERATURE, VS = ±15V
FN7925.1
September 23, 2011
ISL70227SRH
14
13
12
11
10
9
8
7
6
5
4
AV = 10,
3
VIN = 1.31V
2
VS = ±15V
1
0
0.0001
0.001
VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
OPEN LOOP GAIN (dB)/PHASE (°)
VOH (V)
Typical Performance Curves
VOUT (V) -55°C
VOUT (V) 0°C
VOUT (V) +25°C
VOUT (V) +125°C
0.01
0.1
1
10
OUTPUT CURRENT (mA)
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
-11
-12
-13
-14
0.0001
FIGURE 21. OPEN-LOOP GAIN, PHASE vs FREQUENCY, R L = 10kΩ,
CL = 10pF
AV = 10,
VIN = - 1.31V
VS = ±15V
OPEN LOOP GAIN (dB)/PHASE(°)
VOL (V)
FIGURE 20. VOH vs OUTPUT CURRENT
VOUT (V) +125°C
VOUT (V) +25°C
VOUT (V) 0°C
VOUT (V) -55°C
0.001
0.01
0.1
200
180
160
140
PHASE
120
100
80
60
40
GAIN
20
0
-20 R = 10k
L
-40
CL = 10pF
-60
-80 SIMULATION
-100
0.1m 1m 10m 100m 1 10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
1
10
200
180
160
140
120
100
80
60
40
20
0
-20 R = 10k
L
-40
CL = 100pF
-60
SIMULATION
-80
-100
0.1m 1m 10m 100m 1
OUTPUT CURRENT (mA)
21
AV = 1000
Rg = 100, Rf = 100k
AV = 10
0
17
16
15
13
AV = 1
12
Rg = OPEN, Rf = 0
1k
-60°C
14
Rg = 10k, Rf = 100k
-10
100
GAIN (dB)
GAIN (dB)
VS = ±15V
CL = 3.5pF
RL = INF
VOUT = 100mVP-P
30
+25°C
+125°C
19
18
AV = 100
10
+130°C
20
Rg = 1k, Rf = 100k
50
20
10 100 1k 10k 100k 1M 10M 100M
FIGURE 23. OPEN-LOOP GAIN, PHASE vs FREQUENCY, R L = 10kΩ,
CL = 100pF
70
40
GAIN
FREQUENCY (Hz)
FIGURE 22. VOL vs OUTPUT CURRENT
60
PHASE
10k
100k
1M
FREQUENCY (Hz)
10M
100M
FIGURE 24. FREQUENCY RESPONSE vs CLOSED LOOP GAIN
9
AV = 10,
VOUT = 100mVP-P,
VS = +-15V, RL = 2kΩ
11
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 25. GAIN vs FREQUENCY vs TEMPERATURE
FN7925.1
September 23, 2011
ISL70227SRH
Typical Performance Curves
15
2
Rf = Rg = 100k
13
RL = 10k
Rf = Rg = 10k
11
1
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
Rf = Rg = 1k
9
7
5
3
VS = ±15V
1 RL = 10k
-1 CL = 3.5pF
AV = +2
-3
VOUT = 100mVP-P
-5
10k
1k
Rf = Rg = 100
100k
1M
10M
RL = 1k
0
-1
RL = 499
-2
-3
CL = 3.5pF
AV = +1
VOUT = 100mVP-P
-4
-5
1k
100M
RL = 100
VS = ±15V
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 26. FREQUENCY RESPONSE vs FEEDBACK RESISTANCE
Rf/Rg
NORMALIZED GAIN (dB)
6
5
4
NORMALIZED GAIN (dB)
VS = ±15V
RL = 10k
AV = +1
VOUT = 100mVP-P
CL = 1000pF
CL = 220pF
3
CL = 100pF
2
CL = 25.5pF
1
0
-1
-3
1k
10k
100k
1M
FREQUENCY (Hz)
10M
VS = ±5V
-1
VS = ±15V
CL = 3.5pF
RL = 10k
AV = +1
VOUT = 100mVP-P
-2
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 29. GAIN vs FREQUENCY vs SUPPLY VOLTAGE
6
6
5
5
4
4
VS = ±15V
CL = 3.5pF
AV = 1
Rf = 0 Rg = inf
VOUT = 10VP-P
3
2
1
0
LARGE SIGNAL (V)
LARGE SIGNAL (V)
0
-3
100M
FIGURE 28. GAIN vs FREQUENCY vs CL
1
-2
-3
RL = 2k
RL = 10k
-4
0
5
10
15
TIME (µs)
20
25
30
FIGURE 30. LARGE SIGNAL 10V STEP RESPONSE, VS = ±15V
10
OUTPUT +125°C
3
2
OUTPUT +25°C
1
OUTPUT -55°C
0
-1
VS = ±15V
RL = 2k
AV = 1
Rf = 0 Rg = inf
VOUT = 10VP-P
-2
-3
-4
-5
-5
-6
100M
VS = ±2.25V
CL = 3.5pF
-2
10M
FIGURE 27. GAIN vs FREQUENCY vs RL
1
7
RL = 49.9
-6
0
10
20
TIME (µs)
30
40
FIGURE 31. LARGE SIGNAL 10V STEP RESPONSE, VS = ±15V vs
TEMPERATURE
FN7925.1
September 23, 2011
ISL70227SRH
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
80
2.4
60
VS = ±15V, RL = 2k, 10k
0.8
0.4
0
-0.4
VS = ±5V, RL = 2k, 10k
-0.8
-1.2
CL = 3.5pF
AV = 1
VOUT = 4VP-P
-1.6
-2.0
-2.4
0
5
10
15
30
35
-0.26
13
0.22
11
0.08
9
7
5
OUTPUT
5
10
15
20
25
TIME (µs)
30
35
INPUT (V)
VS = ±15V
RL = 10k
CL = 3.5pF
AV = 100
Rf = 100k, Rg = 1k
VIN = 200mVP-P
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0.26
OUTPUT (V)
INPUT (V)
-0.02
-0.20
0
FIGURE 33. SMALL SIGNAL TRANSIENT RESPONSE,
VS = ±5V, ±15V
INPUT
-0.18
RL = 2k
CL = 3.5pF
AV = 1
VOUT = 100mVP-P
40
80
15
-0.14
20
TIME (ms)
0.06
-0.10
VS = ±5V, ±15V
0
40
FIGURE 32. LARGE SIGNAL TRANSIENT RESPONSE vs RL,
VS = ±5V, ±15V
-0.06
20
60
20
25
TIME (µs)
0.02
40
2
OUTPUT
0.04
0.10
0.06
3
0.02
1
-0.02
FIGURE 34. POSITIVE OUTPUT OVERLOAD RESPONSE TIME,
VS = ±15V
VS = ±15V
RL = 10k
CL = 3.5pF
AV = 100
Rf = 100k, Rg = 1k
VIN = 200mVP-P
-2
INPUT
-10
-4
-6
-8
-12
-0.06
0
-1
40
0
OUTPUT (V)
1.6
1.2
SMALL SIGNAL (mV)
LARGE SIGNAL (V)
2.0
5
10
15
20
25
TIME (µs)
30
35
-14
40
FIGURE 35. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME,
VS = ±15V
90
80
OVERSHOOT (%)
70
60
VS = ±15V
RL = 10k
AV = 1
VOUT = 100mVP-P
50
40
O
RS
VE
30
20
O
HO
OT
HO
RS
VE
+
OT
-
10
0
10
100
1000
CAPACITANCE (pF)
10000
FIGURE 36. % OVERSHOOT vs LOAD CAPACITANCE, VS = ±15V
11
FN7925.1
September 23, 2011
ISL70227SRH
Applications Information
Functional Description
V+
The ISL70227SRH is a dual, low noise 10MHz BW precision
op amp fabricated in a new precision 40V complementary
bipolar DI process. A super-beta NPN input stage with input bias
current cancellation provides low input bias current (1nA typical),
low input offset voltage (10µV typ), low input noise voltage
(3nV/√Hz), and low 1/f noise corner frequency (5Hz). These
amplifiers also feature high open loop gain (1500V/mV) for
excellent CMRR (120dB) and THD+N performance (0.0002% @
3.5VRMS, 1kHz into 2kΩ). A complimentary bipolar output stage
enables high capacitive load drive without external
compensation.
Operating Voltage Range
VINVIN+
RIN-
-
RIN+
+
VOUT
RL
V-
FIGURE 38. INPUT ESD DIODE CURRENT LIMITING - DIFFERENTIAL
INPUT
Output Current Limiting
The devices are designed to operate over the 4.5V (±2.25V) to
36V (±18V) range and are fully characterized at 30V (±15V).
Parameter variation with operating voltage is shown in the
“Typical Performance Curves” beginning on page 7.
The output current is internally limited to approximately ±45mA
at +25°C and can withstand a short circuit to either rail as long
as the power dissipation limits are not exceeded. This applies to
only 1 amplifier at a time. Continuous operation under these
conditions may degrade long term reliability.
Input ESD Diode Protection
Output Phase Reversal
The input terminals (IN+ and IN-) have internal ESD protection
diodes to the positive and negative supply rails, and an additional
anti-parallel diode pair across the inputs (see Figures 37 and 38).
Output phase reversal is a change of polarity in the amplifier
transfer function when the input voltage exceeds the supply
voltage. The ISL70227SRH are immune to output phase reversal,
even when the input voltage is 1V beyond the supplies.
V+
Power Dissipation
VIN
RIN
VOUT
+
RL
V-
FIGURE 37. INPUT ESD DIODE CURRENT LIMITING - UNITY GAIN
For unity gain applications (see Figure 37) where the output is
connected directly to the non-inverting input a current limiting
resistor (RIN) will be needed under the following conditions to
protect the anti-parallel differential input protection diodes.
• The amplifier input is supplied from a low impedance source.
• The input voltage rate-of-rise (dV/dt) exceeds the maximum
slew rate of the amplifier (±3.6V/µs).
If the output lags far enough behind the input, the anti-parallel
input diodes can conduct. For example, if an input pulse ramps
from 0V to +10V in 1µs, then the output of the ISL70227SRH will
reach only +3.6V (slew rate = 3.6V/µs) while the input is at 10V,
The input differential voltage of 6.4V will force input ESD diodes to
conduct, dumping the input current directly into the output stage
and the load. The resulting current flow can cause permanent
damage to the ESD diodes. The ESD diodes are rated to 20mA,
and in the previous example, setting RIN to 1k resistor (see
Figure 37) would limit the current to <6.4mA, and provide
additional protection up to ±20V at the input.
In applications where one or both amplifier input terminals are at
risk of exposure to high voltage, current limiting resistors may be
needed at each input terminal (see Figure 38 RIN+, RIN-) to limit
current through the power supply ESD diodes to 20mA.
12
It is possible to exceed the +150°C maximum junction
temperatures under certain load and power supply conditions. It
is therefore important to calculate the maximum junction
temperature (TJMAX) for all applications to determine if power
supply voltages, load conditions, or package type need to be
modified to remain in the safe operating area. These parameters
are related using Equation 1:
(EQ. 1)
T JMAX = T MAX + θ JA xPD MAXTOTAL
where:
• PDMAXTOTAL is the sum of the maximum power dissipation of
each amplifier in the package (PDMAX)
• PDMAX for each amplifier can be calculated using Equation 2:
V OUTMAX
PD MAX = V S × I qMAX + ( V S - V OUTMAX ) × -----------------------R
(EQ. 2)
L
where:
• TMAX = Maximum ambient temperature
• θJA = Thermal resistance of the package
• PDMAX = Maximum power dissipation of 1 amplifier
• VS = Total supply voltage
• IqMAX = Maximum quiescent supply current of 1 amplifier
• VOUTMAX = Maximum output voltage swing of the application
• RL = Load resistance
FN7925.1
September 23, 2011
ISL70227SRH
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev.
REVISION
DATE
CHANGE
FN7925.1
9/20/11 Added “Related Literature” on page 1.
Made correction to Ordering Information - Eval board name changed from "ISL70227SRHEVAL1Z" TO
"ISL70227MHEVAL1Z"
FN7925.0
9/7/11
Initial Release.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
intersil.com: ISL70227SRH
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at: http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
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For information regarding Intersil Corporation and its products, see www.intersil.com
13
FN7925.1
September 23, 2011
ISL70227SRH
Ceramic Metal Seal Flatpack Packages (Flatpack)
K10.A MIL-STD-1835 CDFP3-F10 (F-4A, CONFIGURATION B)
10 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
e
A
INCHES
A
-A-
D
-BPIN NO. 1
ID AREA
b
E1
0.004 M
H A-B S
Q
D S
S1
0.036 M
H A-B S
D S
C
E
-D-
A
-C-
-HL
E2
E3
SEATING AND
BASE PLANE
c1
L
E3
(c)
b1
M
M
(b)
SECTION A-A
MIN
MILLIMETERS
MAX
MIN
MAX
NOTES
A
0.045
0.115
1.14
2.92
-
b
0.015
0.022
0.38
0.56
-
b1
0.015
0.019
0.38
0.48
-
c
0.004
0.009
0.10
0.23
-
c1
0.004
0.006
0.10
0.15
-
D
-
0.290
-
7.37
3
E
0.240
0.260
6.10
6.60
-
E1
-
0.280
-
7.11
3
E2
0.125
-
3.18
-
-
E3
0.030
-
0.76
-
7
2
e
LEAD FINISH
BASE
METAL
SYMBOL
0.050 BSC
1.27 BSC
-
k
0.008
0.015
0.20
0.38
L
0.250
0.370
6.35
9.40
-
Q
0.026
0.045
0.66
1.14
8
S1
0.005
-
0.13
-
6
M
-
0.0015
-
0.04
-
N
10
10
Rev. 0 3/07
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark. Alternately, a tab (dimension k)
may be used to identify pin one.
2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply.
3. This dimension allows for off-center lid, meniscus, and glass
overrun.
4. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate
lead finish is applied.
5. N is the maximum number of terminal positions.
6. Measure dimension S1 at all four corners.
7. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the
leads.
8. Dimension Q shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension Q minimum
shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
14
FN7925.1
September 23, 2011