UCT T PROD ACEMEN at E T E L r L P e OBSO NDED RE port Cent /tsc E p m M u sil.co COM cal S O RE ur Techni www.inter N Data Sheet o r o ct conta -INTERSIL 8 8 8 1 ® EL2008 December 23, 1999 55MHz 1 Amp Buffer Amplifier Features The EL2008 is a patented high speed bipolar monolithic buffer amplifier designed to provide currents over 1 amp at high frequencies, while drawing only 13mA of quiescent supply current. The EL2008’s 1500V/µs slew rate and 55MHz bandwidth driving a 10Ω load is second only to the EL2009 and insures stability in fast op amp feedback loops. Elantec has applied for patents on unique circuitry within the EL2008. • High slew rate 2500V/µs Used as an open loop buffer, the EL2008’s low output impedance (1Ω) gives a gain of 0.99 when driving a 100Ω load and 0.9 driving a 10Ω load. The EL2008 has output short circuit current limiting which will protect the device under both a DC fault condition and AC operation with reactive loads. FN7023 • Wide bandwidth 100MHz @ RL = 50Ω and 55MHz @ RL = 10Ω • Output current 1A continuous • Output impedance 1Ω • Quiescent current 13mA • Short circuit protected • Power package with isolated metal tab Applications • Video distribution amplifier • Fast op amp booster • Flash converter driver The EL2008 is constructed using Elantec's proprietary Complementary Bipolar process that produces PNP and NPN transistors with essentially identical AC and DC characteristics. In the EL2008, the Complementary Bipolar process also insulates the package's metal heat sink tab from all supply voltages. Therefore the tab may be mounted to an external heat sink or the chassis without an insulator. • Motor driver • Pulse transformer driver • A.T.E. pin driver Ordering Information PART NUMBER Pinout EL2008CT EL2008 (5-PIN TO-220) TOP VIEW TEMP. RANGE PACKAGE PKG. NO. 0°C to +75°C 5-Pin TO-220 MDP0028 Simplified Schematic Manufactured under U.S. Patent No. 4,833,424 and 4,827,223 and U.K. Patent No. 2217134. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc. All other trademarks mentioned are the property of their respective owners. EL2008 Absolute Maximum Ratings (TA = 25°C) VS Supply Voltage (V+ - V-) . . . . . . . . . . . . . . . . . . . . ±18V or 36V The maximum power dissipation depends on package type, ambient temperature and heat sinking. See the characteristic curves for more details. Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±15V or VS VIN If the input exceeds the ratings shown (or the supplies) or if the input to output voltage exceeds ±7.5V then the input current must be limited to ±50mA. See the applications section for more information. TA Operating Temperature Range . . . . . . . . . . . . . . 0°C to +75°C TJ Operating Junction Temp . . . . . . . . . . . . . . . . . . . . . . . . . 175°C TST Storage Temp Range . . . . . . . . . . . . . . . . . . .-65°C to +150°C IIN Input Current (See above note) . . . . . . . . . . . . . . . . . . . ±50mA TLD Lead Solder Temp <10 seconds . . . . . . . . . . . . . . . . . . . 300°C PD Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . See Curves CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications VS= ±15V, RS= 50Ω, unless otherwise specified. TEST CONDITIONS PARAMETER VOS DESCRIPTION Output Offset Voltage LIMITS VIN LOAD TEMP MIN TYP MAX UNITS 0 ∞ 25°C -40 10 +40 mV TMIN, TMAX -50 +50 mV 25°C -35 +35 µA 0 ∞ TMIN, TMAX -50 Input Impedance ±12V 100Ω 25°C 0.5 2 MΩ AV1 AV2 AV3 Voltage Gain Voltage Gain Voltage Gain, VS = ±15V ±10V ±10V ±3V ∞ 10Ω 10Ω 25°C 25°C 25°C 0.985 0.88 0.87 0.9995 0.91 0.89 V/V V/V V/V V01 Output Voltage Swing ±14V 100Ω 25°C ±13 V02 Output Voltage Swing ±12V 10Ω 25°C ±10.5 R01 Output Impedance ±10V ±10mA 25°C R02 Output Impedance ±10V ±1A 25°C IO Output Current ±12V (Note 1) 25°C 1.25 TMIN, TMAX 1 IIN Input Current RIN -5 +50 µA V ±11 V 1.8 2.5 Ω 0.8 1.15 Ω 1.8 A A IS Supply Current 0 ∞ 25°C 12 PSRR Supply Rejection (Note 2) 0 ∞ 25°C 60 VS+, VS- Supply Sensitivity (Note 3) ∞ 25°C SR1 Slew Rate (Note 4) ±10V ±10V 50Ω 10Ω 25°C 25°C 2500 1500 V/µs V/µs SR2 Slew Rate (Note 5) ±5V 10Ω 25°C 800 V/µs tR, tF Rise/Fall Time 100mV 10Ω 25°C 7 ns BW -3dB Bandwidth 100mV 10Ω 25°C 55 MHz CIN Input Capacitance 25°C 25 THD 17 26 dB 2 25°C 1. Force the input to +12V and the output to +10V and measure the output current. Repeat with -12V and -10V on the output. 2. VS = ±4.5V then VS is changed to ±18V. 3. VS+ = +15V, VS- = -4.5V then VS - is changed to -18V and VS- = -15V, VS+ = +4.5V then VS+ is changed to +18V. 5. 7:Slew Rate is measured between VOUT = +2.5V and -2.5V. 2 mV/V pF 1 NOTES: 4. Slew Rate is measured between VOUT = +5V and -5V. mA % EL2008 Typical Performance Curves Slew Rate vs Capacitance Load Slew Rate vs Supply Voltage Rise Time vs Temperature Output Impedance vs Frequency Output Resistance vs Supply Voltage Small Signal Output Resistance vs DC Output Current -3dB Bandwidth vs Supply Voltage 3 Quiescent Supply Current vs Supply Voltage Input Current vs Input Voltage EL2008 Typical Performance Curves (Continued) Voltage Gain vs Frequency at Various Resistive Loads Voltage Gain vs Frequency at Various Capacitive Loads Voltage Gain vs Frequency at Various Capacitive Loads Phase Shift vs Frequency at Various Resistive Loads Reverse Isolation vs Frequency Power Supply Rejection Ratio vs Frequency Active Operating Area 4 Active Operating Area EL2008 Burn-In Circuit Internal clamp diodes from the input to the output are provided. These diodes protect the transistor base emitter junctions and limit the boost current during slew to avoid saturation of internal transistors. The diodes begin conduction at about ±2.5V input to output differential. When that happens the input resistance drops dramatically. The diodes are rated at 50mA. When conducting they have a series resistance of about 20Ω. If the output of the EL2008 is accidentally shorted it is possible that some devices driving the EL2008’s input could be damaged or destroyed driving the EL2008’s load through the diodes while the EL2008 is unaffected. In such cases a resistor in series with the input of the EL2008 can limit the current. Source Impedance Applications Information The EL2008 is a monolithic buffer amplifier built on Elantec's proprietary dielectric isolation process that produces NPN and PNP transistors with essentially identical DC and AC characteristics. The EL2008 takes full advantage of the complementary process with a unique circuit topology. Elantec has applied for two patents based on the EL2008’s topology. The patents relate to the base drive and feedback mechanism in the buffer. This feedback makes 3000V/µs slew rates with 10Ω load possible with modest supply current. The EL2008 has good input to output isolation. Open loop, capacitive and resistive sources up to 100kΩ present no oscillation problem driving resistive loads as long as care is used in board layout to minimize output to input coupling and the supplies are properly bypassed. When driving capacitive loads in the 100pF to 1000pF region source resistances above 25Ω can cause peaking and oscillation. Such problems can be eliminated by placing a capacitor from the EL2008s input to ground. The value should be about 1/4 the load capacitance. In a feedback loop there is a speed penalty and a possibility of oscillation when the EL2008 is driven with a source impedance of 200Ω or more. Significant phase shift can occur due to the EL2008’s 25pF input capacitance. Inductive sources can cause oscillations. A series resistor of a few hundred ohms to 1kΩ will usually solve the problem. Power Supplies The EL2008 may be operated with single or split supplies with total voltage difference between 10V (±5V) and 36V (±18V). However, bandwidth, slew rate and output impedance are affected by total supply voltages below 20V (±10V) as shown by the characteristic curves. It is not necessary to use equal split value supplies. For example -5V and +12V would be excellent for signals from -2V to +9V. Bypass capacitors from each supply pin to ground are highly recommended to reduce supply ringing and the interference it can cause. At a minimum a 10µF tantalum capacitor in parallel with a 0.1µF capacitor with short leads should be used for both supplies. Input Characteristics The input to the EL2008 looks like a resistance in parallel with about 25pF in addition to a DC bias current. The DC bias current is due to the mismatch in beta and collector current between the NPN and PNP transistors connected to the input pin. The bias current can be either positive or negative. The change in input current with input voltage (RIN) is affected by the output load, beta and the internal boost. RIN can actually appear negative over portions of the input range in some units. A few typical input current (IIN) curves are shown in the characteristic curves. 5 Current Limit The EL2008 has internal current limiting to protect the output transistors. The current limit is about 1.5A at room temperature and decreases with junction temperature. At 150°C junction temperature it is above 1A. Heat Sinking A suitable heat sink will be required for most applications. The thermal resistance junction to case for the TO-220 package is 4°C per watt. No voltage appears at the heat sink tab so no precautions need to be taken to avoid shorting the tab to a supply voltage or ground. As there is a small parasitic capacitance between the tab and the buffer circuitry, it is recommended that the tab be connected to AC ground (either supply voltage or DC ground). The center lead is internally connected to the tab so the connection can be made at the tab or the center lead. Parallel Operation If more than 1A is required or if heat management is a problem, several EL2008s may be paralleled together. The result is as through each device was driving only part of the load. For example, if two units are paralleled then a 5Ω load looks like 10Ω to each EL2008. Of course, parallel operation reduces both the input and output impedance and increases EL2008 bias current. But there is no increase in offset voltage. Three units in parallel can drive a 3Ω load ±10V at 2500V/µs. The output impedance will be about 0.33Ω. Resistive Loads The DC gain of the EL2008 is the product of the unloaded gain (0.999) and the voltage divider formed by the device output resistance and the load resistance. AV = 0.999* (RL/RL + ROUT) The high frequency response varies with the load resistance as shown by the characteristic curves. Both gain and phase are shown. If the 80MHz peaking is undesirable when driving load resistors greater than 50Ω, an RC snubber circuit can be used from output to ground. The capacitive load section discusses snubber usage in more detail. Capacitive Loads The EL2008 is not stable driving purely capacitive loads between 100pF and 500pF. Purely capacitive loads from 500pF to 1000pF will also have excessive peaking as shown in the characteristic curves. The squarewave response will have large overshoots and ring for hundreds of nanoseconds. When driving capacitive loads, stability can be achieved and peaking and ringing can be minimized either by adding a 50Ω (or less) load in parallel with the capacitive load or by an RC snubber circuit from output to ground. The snubber values can be found empirically by observing a squarewave or the frequency response. First just put a resistor alone from the output to ground until the desired response is achieved. The gain will be reduced due to the output resistance of the EL2008 and power consumption will be high. Then put a capacitor in series with the resistor to restore gain at low frequencies and eliminate the DC current. Start with a small capacitor and increase until the response is optimum. The figure below shows an example of an EL2008 driving a 100pF load. DRIVING A PURE CAPACITIVE LOAD. TOP TRACE IS WITHOUT A SNUBBER. BOTTOM TRACE IS WITH A SNUBBER CIRCUIT. Inductive Loads The EL2008 with its 1A output current can drive small motors and other inductive loads. The EL2008’s current limiting into inductive loads does NOT in and of itself cause spikes and kickbacks. However, if the EL2008 is in current limit and the input voltage is changing very quickly (i.e., a squarewave) the inductive load can kick the output beyond the supply voltages. Motors are also able to generate kickback voltages when the EL2008 is in current limit. To prevent damage to the EL2008 when the output kicks beyond the supplies, it is recommended that catch diodes be placed from each supply to the output. Op Amp Booster The EL2008 can boost the output drive of almost any monolithic op amp. If the phase shift in the EL2008 is low at the op amp's unity gain frequency, no additional frequency compensation is required. An op amp followed with the EL2008 can drive loads as low as 10Ω to ±10V. Driving capacitive loads with any closed loop system creates special problems. The open loop output impedance works into the load capacitance to generate phase lag which can make the loop unstable. The EL2008 output impedance is less than 10Ω from DC to 30MHz. But a capacitive load of 1000pF will generate about 45 degrees of phase shift at 30MHz. More capacitance will cause the problem at lower frequency. With enough capacitance even slow op amps will become unstable. The simplest way to drive capacitive loads is to isolate them from the feedback with a series resistor. 1Ω to 5Ω is usually enough but the final value will depend on the op amp used and the range of load capacitance. 6 EL2008 Video Distribution Amplifier CL tR O.S. 13pF 45ns 20% 470pF 50ns 20% 1000pF 55ns 30% 3300pF 60ns 30% 0.1µF 350ns 0% 1µF 4µs 0% 5µF 20µs 0% Unfortunately the isolation resistor is not inside the op amp feedback loop and cannot be neglected when computing the DC voltage gain into a resistive load. If load dependent DC gain is not tolerable then additional high frequency feedback from the op amp output (the EL2008 input) and an isolation resistor from the buffer output can be used to stabilize the loop. This configuration requires the op amp to be unity gain stable. This feedback method will allow the EL2008 to boost the output of the EHA2505 amplifier below and serve as a variable, bipolar 1A voltage supply with short circuit protection. Slew Rate = 1A/CL 7 The EL2008 can drive 15 double matched 75Ω cables. If the EL2008 is used within an op amp feedback loop the output levels are independent of loading. The circuit below accepts 1 of 2 inputs and drives 15 cables. Pin 8 of the EL2020 (Disable) is used to multiplex between the inputs and can be easily expanded to accept more inputs. The circuit as shown when fully loaded has differential phase < 0.1° and differential gain < 0.1%. The 100Ω resistor at the EL2008 input (R1) is necessary to stabilize the loop. The 100Ω resistor at the EL2008 output (R2) to the -12V supply, insures that the EL2008 sources current even when the output voltage is at 0V. This is necessary to achieve the excellent differential gain and phase values. More information about driving cables can be found in the EL2003 data sheet. See the EL2020 data sheet to learn more about using it as a multiplexer. INPUT (TOP TRACE) AND OUTPUT (BOTTOM TRACE) OF EHA2505 OP AMP BOOSTED BY EL2008. EL2008 Video Mux and Distribution Amplifier EL2008 Macromodel * Connections: +input * | +Vsupply * | | -Vsupply * | | | output * | | | | .subckt M2008 4 5 1 2 * * Input Stage * e1 10 0 4 0 1.0 r1 10 0 1K rh 10 11 1K ch 11 0 2.65pF rc 11 12 10K cc 12 0 0.159pF e2 13 0 12 0 1.0 * * Output Stage * q1 1 13 14 qp q2 5 13 15 qn q3 5 14 16 qn 15 q4 1 15 19 qp 15 r2 16 2 0.4 r3 19 2 0.4 c1 14 0 0.6pF c2 15 0 0.6pF i1 5 14 1.2mA i2 15 1 1.2mA * * Bias Current * iin+ 4 0 5µA * * Models * .model qn npn (is=5e-15 bf=1500) .model qp pnp (is=5e-15 bf=1500) .ends* All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 8