INTERSIL EL9115ILZ

EL9115
®
Data Sheet
September 22, 2009
FN7441.5
Triple Analog Video Delay Line
Features
The EL9115 is a triple analog delay line that allows skew
compensation between any three signals. This part is perfect
for compensating for the skew introduced by a typical CAT-5
cable with differing electrical lengths on each pair.
• 62ns total delay
The EL9115 can be programmed in steps of 2ns up to 62ns
total delay on each channel.
• Up to 122MHz bandwidth
Ordering Information
• 20 Ld QFN (5mmx5mm) package
PART
NUMBER
PART
MARKING
PACKAGE
PKG.
DWG. #
EL9115IL
9115IL
20 Ld 5mmx5mm QFN L20.5x5C
EL9115ILZ
(Note)
9115ILZ
20 Ld 5mmx5mm QFN L20.5x5C
(Pb-free)
EL9115ILZ-T7* 9115ILZ
(Note)
20 Ld 5mmx5mm QFN L20.5x5C
(Pb-free)
EL9115ILZ-T13* 9115ILZ
(Note)
20 Ld 5mmx5mm QFN L20.5x5C
(Pb-free)
• 2ns delay step increments
• Operates from ±5V supply
• Low power consumption
• Pb-free available (RoHS compliant)
Applications
• Skew control for RGB
• Analog beamforming
Pinout
EL9115
(20 LD 5X5 QFN)
TOP VIEW
16 VSPO
17 TESTB
18 TESTG
19 TESTR
VSP 1
15 ROUT
RIN 2
14 GNDO
THERMAL
PAD
GND 3
13 GOUT
SCLOCK 10
11 BOUT
SDATA 9
VSM 5
NSENABLE 8
12 VSMO
BIN 6
GIN 4
CENABLE 7
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
20 X2
*Please refer to TB347 for details on reel specifications.
EXPOSED DIEPLATE SHOULD BE CONNECTED TO -5V
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004-2006, 2008, 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
EL9115
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Supply Voltage (VS+ to VS-) . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V
Maximum Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . ±60mA
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
DC Electrical Specifications
PARAMETER
VSA+ = VA+ = +5V, VSA- = VA- = -5V, TA = +25°C, exposed die plate = -5V, unless otherwise specified.
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
V+
Positive Supply Range
+4.5
+5.5
V
V-
Negative Supply Range
-4.5
-5.5
V
G_0
Gain Zero Delay
G_m
X2 = 5V, 150Ω load
1.81
1.89
2.04
Gain Mid Delay
1.66
1.84
2.04
G_f
Gain Full Delay
1.52
1.79
2.04
DG_m0
Difference in Gain, 0 to Mid
-7.5
-2.5
2.5
%
DG_f0
Difference in Gain, 0 to Full
-13.5
-6.0
2.5
%
DG_fm
Difference in Gain, Mid to Full
-10.0
-2.6
4.0
%
VIN
Input Voltage Range
1.3
V
IB
Input Bias Current
1
5
µA
RIN
Input Resistance
10
VOS_0
Output Offset 0 Delay
VOS_M
Gain falls to 90% of nominal
X2 = +5V, 75 + 75Ω load
-0.7
MΩ
-200
-150
60
mV
Output Offset Full Delay
-200
-140
60
mV
VOS_F
Output Offset Mid Delay
-200
-130
60
mV
ZOUT
Output Impedance
4.5
5
6.3
Ω
Chip enable = +5V
Chip enable = 0V
1
MΩ
+PSRR
Rejection of Positive Supply
X2 = +5V into 75 + 75Ω load
-38
dB
-PSRR
Rejection of Negative Supply
X2 = +5V into 75 + 75Ω load
-53
dB
ISP
Supply Current (Note 1)
Chip enable = +5V current on VSP
75
87
115
mA
ISM
Supply Current (Note 1)
Chip enable = +5V current in VSM
-10.5
-8.6
-7
mA
ISMO
Supply Current (Note 1)
Chip enable = +5V current in VSMO
-13
-11.6
-10
mA
ISPO
Supply Current (Note 1)
Chip enable = +5V current in VSPO
10
11.8
15.5
mA
ΔISP
Supply Current (Note 1)
Increase in ISP per unit step in delay
0.9
mA
ISP OFF
Supply Current (Note 1)
Chip enable = 0V current in VSP
1.6
mA
IOUT
Output Drive Current
10Ω load, 0.5V drive, X2 = 5V
LHI
Logic High
Switch high threshold
LLO
Logic Low
Switch low threshold
2
30
mA
1.25
0.8
1.15
1.6
V
V
FN7441.5
September 22, 2009
EL9115
AC Electrical Specifications
PARAMETER
VSA+ = VA+ = +5V, VSA- = VA- = -5V, TA = +25°C, exposed die plate = -5V, unless otherwise specified.
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
BW -3dB
3dB Bandwidth
0ns Delay Time
122
MHz
BW 0.1dB
0.1dB Bandwidth
0ns Delay Time
60
MHz
SR
Slew Rate
0ns Delay Time
400
V/µs
tR - t F
Transient Response Time
20% to 80%, for all delays, 1V step
2.5
ns
VOVER
Voltage Overshoot
for any delay, response to 1V step input
5
%
Glitch
Switching Glitch
Time for o/p to settle after last s_clock edge
100
ns
THD
Total Harmonic Distortion
1VP-P 10MHz sinewave, offset by +0.2V at
mid delay setting
-50
Xt
Hostile Crosstalk
Stimulate G, measure R/B at 1MHz
-80
dB
VN
Output Noise
Gain X2, measured at 75Ω load
2.5
mVRMS
dt
Nominal Delay Increment
Note 2
tMAX
Maximum Delay
DELDT
Delay Diff Between Channels
tPD
Propagation Delay
Measured input to output
tMAX
Max s_clock Frequency
Maximum programming clock speed
t_en_ck
Minimum Separation Between Serial
Enable and Clock
Check enable low edge can occur after
t_en_ck of previous (ignored) clock and up to
before t_en_ck of next (wanted) clock. Clock
edges occurring within t_en_ck of the enable
edge will have uncertain effect.
-40
dB
1.75
2
2.25
ns
55
62
70
ns
1.6
%
9.8
ns
10
10
MHz
ns
NOTES:
1. All supply currents measured with Delay R = 0ns, G = mid delay, B = full delay.
2. Delay increment limits are derived by taking Maximum Delay limits and dividing by the number of steps for the device (e.g. the number of steps
for the EL9115 is 31).
Pin Descriptions
PIN NUMBER
PIN NAME
PIN DESCRIPTION
1
VSP
+5V for delay circuitry and input amp
2
RIN
Red channel input, ref GND
3
GND
0V for delay circuitry supply
4
GIN
Green channel input, ref GND
5
VSM
-5V for input amp
6
BIN
7
CENABLE
8
NSENABLE
ENABLE for serial input; enable on low
9
SDATA
Data into registers; logic threshold 1.2V
10
SCLOCK
11
BOUT
Blue channel output, ref GNDO
12
VSMO
-5V for output buffers
13
GOUT
Green channel output, ref GNDO
14
GNDO
0V reference for input and output buffers
15
ROUT
Red channel output, ref GNDO
16
VSPO
+5V for output buffers
17
TESTB
Blue channel phase detector output
18
TESTG
Green channel phase detector output
3
Blue channel input, ref GND
Chip enable logical +5V enables chip
Clock to enter data; logical; data written on negative edge
FN7441.5
September 22, 2009
EL9115
Pin Descriptions (Continued)
PIN NUMBER
PIN NAME
19
TESTR
20
X2
PIN DESCRIPTION
Red channel phase detector output
Sets gain to 2X if input high; X1 otherwise
Thermal Pad
Must be connected to -5V
Typical Performance Curves
Delay = 0ns
-3dB@122MHz
Delay = 0ns
Delay = 62ns
Delay = 62ns
-3dB@80MHz
Delay 10, 20, 30, 40 and 50ns
FIGURE 1. GAIN vs FREQUENCY
DELAY TIME (ns)
FIGURE 3. TYPICAL DC OFFSET vs DELAY TIME (X2 = Hi)
DELAY TIME (ns)
FIGURE 5. RISE TIME vs DELAY TIME
4
Delay 10, 20, 30, 40 and 50ns
FIGURE 2. GAIN vs FREQUENCY
DELAY
DELAY TIME (ns)
FIGURE 4. TYPICAL DC OFFSET vs DELAY TIME (X2 = Low)
DELAY TIME (ns)
FIGURE 6. FALL TIME vs DELAY TIME
FN7441.5
September 22, 2009
EL9115
Typical Performance Curves (Continued)
Vout = 1Vptp
3 Channels
DELAY TIME (ns)
FIGURE 7. DISTORTION vs FREQUENCY
FIGURE 8. POSITIVE SUPPLY CURRENT vs DELAY TIME
X2 Hi_62ns Delay
X2 Hi_62ns Delay
X2 Hi_0ns Delay
X2 Low_62ns Delay
X2 Hi_0ns Delay
X2 Low_62ns Delay
X2 Low_0ns Delay
X2 Low_0ns Delay
FIGURE 9. ISUPPLY+ vs VSUPPLY+
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
4.0
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD - QFN EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
3.5
1.0
POWER DISSIPATION (W)
POWER DISSIPATION (W)
1.2
FIGURE 10. ISUPPLY- vs VSUPPLY-
833mW
0.8
θJ
A=
0.6
QF
N2
15 0
0°
C/
W
0.4
0.2
3.0
2.5
θJ
QF
N2
0
2 °C
/W
A=
3
2.0
1.5
1.0
0.5
0
0
0
25
75 85 100
50
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 11. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
5
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90
AMBIENT TEMPERATURE (°C)
FIGURE 12. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FN7441.5
September 22, 2009
2
R_IN
1
19
17
18
16
VSP
TESTR
TESTB
TESTG
VSPO
EL9115
+
CENABLE 7
DELAY LINE
+
4
G_IN
+
DELAY LINE
+
6
B_IN
+
B_OUT 11
X2 20
SDATA
SCLOCK
CONTROL LOGIC
5
C
GND
[BOTTOM PLATE]
3
VSMO
VSM
NSENABLE
GND
8
G_OUT 13
DELAY LINE
+
9
10
R_OUT 15
12
14
FIGURE 13. EL9115 BLOCK DIAGRAM
Applications Information
EL9115 is a triple analog delay line receiver that allows skew
compensation between any three high frequency signals.
This part compensates for time skew introduced by a typical
CAT-5 cable with differing electrical lengths on each pair.
The EL9115 can be independently programmed via SPI
interface in steps of 2ns up to 62ns total delay on each
channel while achieving over 80MHz bandwidth.
Figure 13 shows the EL9115 block diagram. The 3 analog
inputs are ground reference single-ended signals. After the
signal is received, the delay is introduced by switching filter
blocks into the signal path. Each filter block is an all-pass
filter introducing 2ns delay. In addition to time delay, each
filter block also introduces some low pass filtering. As a
result, the bandwidth of the signal path decreases from
120MHz at 0ns delay setting to 80MHz at the maximum
delay setting, as shown in Figure 1 of the “Typical
Performance Curves” on page 4.
In addition to delay, the extra amplifiers in the signal path
also introduce offset voltage. The output offset voltage can
shift by 100mV for X2 high setting and 50mV for X2 low.
In operation, it is best to allocate the most delayed signal
0ns delay then increase the delay on the other channels to
bring them into line. This will result in the lowest power and
distortion solution to balancing delays.
Power Dissipation
As the delay setting increases, additional filter blocks turn on
and insert into the signal path. For each 2ns of delay per
channel, VSP current increases by 0.9mA while VSM does
not change significantly. Under the extreme settings, the
positive supply current reaches 140mA and the negative
6
supply current can be 35mA. Operating at ±5V power supply,
the total power dissipation is:
PD = 5 • 140mA + 5 • 35mA = 875mW
(EQ. 1)
θJA required for long term reliable operation can be
calculated. This is done using Equation 2:
θ JA = ( T J – T A ) ⁄ PD = 57° C ⁄ W
(EQ. 2)
Where:
TJ is the maximum junction temperature (+135°C)
TA is the maximum ambient temperature (+85°C)
For a 20 Ld package in a proper layout PCB heatsinking
copper area, 40°C/W θJA thermal resistance can be
achieved. To disperse the heat, the bottom heatspeader
must be soldered to the PCB. Heat flows through the
heatspreader to the circuit board copper then spreads and
convects to air. Thus, the PCB copper plane becomes the
heatsink (see TB389). This has proven to be a very effective
technique. A separate application note, which details the
20 Ld QFN PCB design considerations, is available.
TABLE 1. SERIAL BUS DATA
vwxyz
DELAY
00000
0
00001
2
00010
4
00011
6
00100
8
00101
10
00110
12
FN7441.5
September 22, 2009
EL9115
Serial Bus Operation
TABLE 1. SERIAL BUS DATA (Continued)
vwxyz
DELAY
00111
14
01000
16
01001
18
01010
20
01011
22
01100
24
01101
26
01110
28
01111
30
10000
32
10001
34
On the first negative clock edge after NSEnable goes low,
read the input from DATA. This DATA level should be 0 (write
into registers); READ is not supported. Read the next two
data bits on subsequent negative edges and interpret them
as the register to be filled. Reg 01 = R, 02 = G, 03 = B, 00
test use. Read the next five bits of data and send them to
register. At the end of each block of 8 bits, any further data is
treated as being a new word. Data entered is shifted directly
to the final registers as it is clocked in. Initial value of all
registers on power-up is 0. It is the user's responsibility to
send complete patterns of 8 clock cycles, even if the first bit
is set to 1. If less than 8 bits are sent, data will only be
partially shifted through the registers. The pattern of 8 starts
with NSEnable going low, so it is good practice to frame
each word within an NS enable burst.
10010
36
Test Pins
10011
38
10100
40
10101
42
Three test pins are provided (Test R, Test G, Test B). During
normal operation, the test pins output pulses of current for a
duration of the overlap between the inputs, as shown in
Figure 15:
10110
44
10111
46
11000
48
Test_G pulse = Green out
wrt Blue out
11001
50
Test_B pulse = Blue out
wrt Red out
11010
52
11011
54
11100
56
Averaging the current gives a direct measure of the delay
between the two edges. When A precedes B the current
pulse is +50µA, and the output voltage goes up. When B
precedes A, the pulse is -50µA.
11101
58
11110
60
11111
62
Test_R pulse = Red out (A) wrt Green out (B)
For the logic to work correctly, A and B must have a period of
overlap while they are high (a delay longer than the pulse
width cannot be measured).
NOTE: Delay register word = 0abvwxyz; Red register - ab = 01;
Green register - ab = 10; Blue register - ab = 11; vwxyz selects delay.
NSENABLE
SCLOCK
0
A1
A0
D4
D3
D2
D1
D0
a
b
v
w
x
y
z
SDATA
FIGURE 14.
7
FN7441.5
September 22, 2009
EL9115
Signals A and B are derived from the video input by
comparing the video signal with a slicing level, which is set by
an internal DAC. This enables the delay to be measured
either from the rising edges of sync-like signals encoded on
top of the video or from a dedicated set-up signal. The outputs
can be used to set the correct delays for the signals received.
TABLE 2.
wxyz
DAC/mV
1000
-400
1001
-350
1010
-300
The DAC level is set through the serial input by bits 1
through 4 directed to the test register (00).
1011
-250
1100
-200
Test Mode
1101
-150
Bit zero of the test register is set to 0 for normal operation. If
it is set to 1 then the device is in Test Mode. In Test Mode,
the DAC voltage is directed to the Green channel output,
while for the Red and Blue channels, the test outputs are
now pulses of current which are generated by looking at the
delay between the input and output of the channel. They
thus enable the delay to be measured.
1110
-100
1111
-50
0000
0
0001
50
0010
100
0011
150
0100
200
0101
250
0110
300
0111
350
A
B
OUTPUT
4
NOTE: Test Register word = 000wxyzt. If t = 1 test mode else
normal. wxyz fed to DAC. z is LSB
SLICING LEVEL
COMPARATORS
A
VIDEO IN
B
FIGURE 15. DELAY DETECTOR
8
FN7441.5
September 22, 2009
EL9115
Quad Flat No-Lead Plastic Package (QFN)
A
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220)
B
N
(N-1)
(N-2)
D
1
2
3
L20.5x5C
MILLIMETERS
SYMBOL
PIN #1
I.D. MARK
E
(2X)
0.075 C
TOP VIEW
(2X)
(N/2)
0.075 C
SEATING
PLANE
MAX
NOTES
A
0.80
0.90
1.00
-
0.00
0.02
0.05
-
b
0.28
0.30
0.32
-
c
0.20 REF
-
D
5.00 BASIC
-
D2
3.70 REF
8
E
5.00 BASIC
-
E2
3.70 REF
8
e
0.10 C
e
NOMINAL
A1
L
C
MIN
0.65 BASIC
0.35
0.40
0.45
-
N
20
4
ND
5 REF
6
NE
5 REF
5
Rev. 0 6/06
0.08 C
N LEADS AND
EXPOSED PAD
NOTES:
SEE DETAIL “X”
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
SIDE VIEW
2. Tiebar view shown is a non-functional feature.
3. Bottom-side pin #1 I.D. is a diepad chamfer as shown.
4. N is the total number of terminals on the device.
b
L
N LEADS
(N-2)
(N-1)
N
0.01 M C A B
PIN #1 I.D.
3
1
2
3
NE 5
(N/2)
6. ND is the number of terminals on the “D” side of the package
(or X-direction). ND = (N/2)-NE.
7. Inward end of terminal may be square or circular in shape with
radius (b/2) as shown.
(E2)
(D2)
5. NE is the number of terminals on the “E” side of the package
(or Y-direction).
8. If two values are listed, multiple exposed pad options are
available. Refer to device-specific datasheet.
9. One of 10 packages in MDP0046
7
BOTTOM VIEW
C
A
2
(c)
(L)
N LEADS
A1
DETAIL “X”
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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9
FN7441.5
September 22, 2009