DATASHEET

DATASHEET
Triple Analog Video Delay Lines
ISL59920, ISL59921, ISL59922, ISL59923
The ISL59920, ISL59921, ISL59922, and ISL59923 are triple
Features
analog delay lines that provide skew compensation between
• 30, 31, 46.5, or 62ns Total delay
three high-speed signals. These parts are ideal for
compensating for the skew introduced by a typical CAT-5,
CAT-6 or CAT-7 cable (with differing electrical lengths on each
twisted pair) when transmitting analog video.
• 1.0, 1.5, or 2.0ns Delay step increments
• Very low offset voltage
• Drop-in compatible with the EL9115
Using a simple serial interface, the ISL59920, ISL59921,
ISL59922, and ISL59923’s delays are programmable in steps
of 2, 1.5, 1, or 2ns (respectively) for up to a total delay of 62,
46.5, 31, or 30ns (respectively) on each channel. The gain of
the video amplifiers can be set to x1 (0dB) or x2 (6dB) for
back-termination. The delay lines require a ±5V supply.
• Low power consumption
• 20 Ld QFN package
• Pb-Free (RoHS compliant)
Applications
• Skew control for RGB video signals
17
18
16
TESTB
TESTG
VSPO
RIN
19
TESTR
2
1
VSP
• Generating programmable high-speed analog delays
+
CENABLE 7
DELAY LINE
ROUT 15
+
+
+
GOUT 13
+
BOUT 11
DELAY LINE
X2 20
SDATA
SCLOCK
SENABLE
CONTROL LOGIC
[BOTTOM PLATE]
3
5
C
GND
8
BIN
DELAY LINE
VSMO
9
10
+
VSM
6
GIN
GND
4
12
14
FIGURE 1. ISL59920, ISL59921, ISL59922, ISL59923 BLOCK DIAGRAM
August 27, 2015
FN6826.4
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2009, 2010, 2014, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL59920, ISL59921, ISL59922, ISL59923
Ordering Information
MAX
DELAY
(ns)
DELAY STEP
SIZE (ns)
TYPICAL POWER
DISSIPATION
(mW)
62
2.0
645
20 Ld 5mmx5mm QFN
L20.5x5C
ISL59921IR (No longer 59921 IRZ
available or supported)
46.5
1.5
645
20 Ld 5mmx5mm QFN
L20.5x5C
ISL59922IRZ(No longer 59922 IRZ
available or supported)
31
1.0
645
20 Ld 5mmx5mm QFN
L20.5x5C
ISL59923IRZ(No longer 59923 IRZ
available or supported)
30
2.0
540
20 Ld 5mmx5mm QFN
L20.5x5C
PART NUMBER
(Notes 1, 2, 3)
ISL59920IRZ
PART
MARKING
59920 IRZ
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pbfree products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information pages for ISL59920, ISL59921, ISL59922, ISL59923. For more information on
MSL, please see tech brief TB363
Pin Configuration
16 VSPO
17 TESTB
18 TESTG
19 TESTR
20 X2
ISL59920, ISL59921, ISL59922, ISL59923
(20 LD 5x5 QFN)
TOP VIEW
VSP 1
15 ROUT
RIN 2
14 GNDO
THERMAL
PAD
GND 3
13 GOUT
SCLOCK 10
SDATA 9
11 BOUT
SENABLE 8
VSM 5
CENABLE 7
12 VSMO
BIN 6
GIN 4
Pin Descriptions
PIN NUMBER
PIN NAME
PIN DESCRIPTION
1
VSP
+5V for delay circuitry and input amp
2
RIN
Red channel video input
3
GND
0V for delay circuitry supply
4
GIN
Green channel video input
5
VSM
-5V for input amp
6
BIN
Blue channel video input
7
CENABLE
Chip Enable input, active high: logical high enables chip, low disables chip. This pin should be low
at power-on until at least 30ms after the power supply has settled to within 5% of its final value.
For more information, see “CENABLE at Power-On” on page 16.
8
SENABLE
Serial Enable input, active low: logical low enables serial communication
9
SDATA
Serial Data input, logic threshold 1.2V: data to be programmed into chip
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2
FN6826.4
August 27, 2015
ISL59920, ISL59921, ISL59922, ISL59923
Pin Descriptions (Continued)
PIN NUMBER
PIN NAME
10
SCLOCK
PIN DESCRIPTION
11
BOUT
Blue channel video output
12
VSMO
-5V for video output buffers
Serial Clock input: Clock to enter data; logical; data written on negative edge
13
GOUT
Green channel video output
14
GNDO
0V reference for input and output buffers
15
ROUT
Red channel video output
16
VSPO
+5V for video output buffers
17
TESTB
Blue channel phase detector output
18
TESTG
Green channel phase detector output
19
TESTR
Red channel phase detector output
20
X2
Thermal Pad
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Gain Select Input: logical high = 2x (+6dB), logical low = 1x (0dB)
MUST be tied to -5V. For best thermal conductivity, tie to a larger -5V copper plane (inner or
bottom). Use many vias to minimize thermal resistance between thermal pad and copper plane.
Do not connect to GND - connection to GND is equivalent to shorting the -5V and GND planes
together.
3
FN6826.4
August 27, 2015
ISL59920, ISL59921, ISL59922, ISL59923
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Supply Voltage (VS+ to VS-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V
Maximum Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±60mA
Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
ESD Classification
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3000V
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300V
Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1200V
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
20 Lead QFN (Notes 4, 5) . . . . . . . . . . . . . .
31
2
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+135°C
Ambient Operating Temperature . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTE:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
VSP = VSPO = +5V, VSM = VSMP = -5V, GAIN = 2, TA = +25°C, exposed die plate = -5V, x2 = 5V, RLOAD = 150Ω
on all video outputs, unless otherwise specified.
PARAMETER
dt
tMAX
DESCRIPTION
Nominal Delay Increment (Note 7)
Maximum Delay
DELDT
Delay Difference Between Channels for Same
Delay Settings On All Channels
tPD
Propagation Delay
BW -3dB
BW ±0.1dB
SR
3dB Bandwidth, 0ns Delay Time
±0.1dB Bandwidth, 0ns Delay Time
Slew Rate
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4
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
ISL59920
1.8
2
2.2
ns
ISL59921
1.4
1.5
1.7
ns
ISL59922
0.9
1
1.2
ns
ISL59923
1.8
2
2.3
ns
ISL59920
55
62
68
ns
ISL59921
42.5
46.5
53.5
ns
ISL59922
26.5
31
38.5
ns
ISL59923
26.5
30
34.5
ns
1
ns
ISL59920, ISL59923, measured input to
output, delay setting = 0ns
10
ns
ISL59921, measured input to output, delay
setting = 0ns
8
ns
ISL59922, measured input to output, delay
setting = 0ns
7
ns
ISL59920, ISL59923
153
MHz
ISL59921
200
MHz
ISL59922
230
MHz
ISL59920, ISL59923
50
MHz
ISL59921
60
MHz
ISL59922
50
MHz
ISL59920, 20 to 80, delay = 0ns
550
V/µs
ISL59921, 20 to 80, delay = 0ns
640
V/µs
ISL59922, 20 to 80, delay = 0ns
700
V/µs
ISL59923; 20 to 80, delay = 0ns
550
V/µs
FN6826.4
August 27, 2015
ISL59920, ISL59921, ISL59922, ISL59923
Electrical Specifications
VSP = VSPO = +5V, VSM = VSMP = -5V, GAIN = 2, TA = +25°C, exposed die plate = -5V, x2 = 5V, RLOAD = 150Ω
on all video outputs, unless otherwise specified. (Continued)
PARAMETER
tR - tF
DESCRIPTION
Transient Response Time
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
ISL59920, 20% to 80%, for any delay, 1V step
delay = 0ns
1.7
ns
ISL59921, 20% to 80%, for any delay, 1V step
delay = 0ns
1.6
ns
ISL59922, 20% to 80%, for any delay, 1V step
delay = 0ns
1.43
ns
ISL59923, 20% to 80%, for any delay, 1V step
delay = 0ns
1.7
ns
VOVER
Voltage Overshoot
For any delay, response to 1V step input
4
%
Settling Time
Output Settling after Delay Change / Offset
Calibration
Output settling time from rising edge of
SENABLE
3
µs
THD
Total Harmonic Distortion
1VP-P 10MHz sinewave, offset by +0.2V at mid
delay setting
-43
-38
dB
X
Crosstalk
Stimulate G, measure R/B at 1MHz,
ISL59920, ISL59921, ISL59923
-80
-63
dB
ISL59922
-78
-59
dB
VN
Output Noise
Bandwidth = 150MHz
2
mVRMS
G_0
Gain Zero Delay
1.74
1.8
1.92
V/V
G_m
Gain Mid Delay
1.67
1.8
1.97
V/V
G_f
Gain Full Delay
1.6
1.8
2
V/V
DG_m0
Difference in Gain, 0 to Mid
-8
0.6
7.5
%
DG_f0
Difference in Gain, 0 to Full
-12
-1.8
10
%
DG_fm
Difference in Gain, Mid to Full
-10
-1.7
7.5
%
VIN
Input Voltage Range
IB
RIN, GIN, BIN Input Bias Current
ISL59920, Gain remains > 90% of nominal,
Gain = 2
-0.7
1.1
V
ISL59921, Gain remains > 90% of nominal,
Gain = 2
-0.7
1.04
V
ISL59922, Gain remains > 90% of nominal,
Gain = 2
-0.7
1.04
V
ISL59923, Gain remains > 90% of nominal,
Gain = 2
-0.7
1.15
V
8
µA
8
µA
ISL59920, ISL59921
3
ISL59922, ISL59923
1.5
6
VOS
Output Offset Voltage
Post offset calibration (Note 9), Delay = 0ns
and Delay = Full
-25
-4
+20
mV
ZOUT
Output Impedance
ISL59920, ISL59921, Enabled,
Chip enable = 5V
4.5
5.4
6.3
Ω
ISL59922, ISL59923, Enabled,
Chip enable = 5V
3.5
6.3
Ω
Disabled, Chip enable = 0V
8
MΩ
+PSRR
Rejection of Positive Supply
-42
-29
dB
-PSRR
Rejection of Negative Supply
-58
-46
dB
IOUT
Output Drive Current
10Ω load, 0.5V drive
53
70
mA
VIH
Logic High
Switch high threshold
1.6
V
VIL
Logic Low
Switch low threshold
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5
43
0.8
V
FN6826.4
August 27, 2015
ISL59920, ISL59921, ISL59922, ISL59923
Electrical Specifications
VSP = VSPO = +5V, VSM = VSMP = -5V, GAIN = 2, TA = +25°C, exposed die plate = -5V, x2 = 5V, RLOAD = 150Ω
on all video outputs, unless otherwise specified. (Continued)
PARAMETER
DESCRIPTION
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
POWER SUPPLY CHARACTERISTICS
V+
VSP, VSPO Positive Supply Range
+4.5
+5.5
V
V-
VSM, VSMO Negative Supply Range
-4.5
-5.5
V
ISP
Positive Supply Current (Note 8)
ISPO
Positive Output Supply Current (Note 8)
ISL59920
98
115
127
mA
ISL59921, ISL59922
98
125
146
mA
ISL59923
74
90
106
mA
ISL59920
11.3
13
15.3
mA
ISL59921, ISL59922
11.3
13
16.3
mA
9.9
13
16
mA
-35.45
-31
-26
mA
ISL59920, ISL59921, ISL59922
-15.5
-13
-11
mA
ISL59923
-17.5
-13
-9.5
mA
ISL59923
ISM
Negative Supply Current (Note 8)
ISMO
Negative Output Supply Current (Note 8)
ISP
Supply Current (Note 8)
Increase in ISP per unit step in delay per
channel
0.9
mA
ISTANDBY
Positive Supply Standby Current (Note 8)
Chip enable = 0V
2.6
mA
SERIAL INTERFACE CHARACTERISTICS
tMAX
Max SCLOCK Frequency
Maximum programming clock speed
tSEN_SETUP
SENABLE to SCLOCK falling edge setup time.
(see Figure 35).
SENABLE falling edge should occur at least
tSEN_SETUP ns after previous (ignored) clock
and tSEN_SETUP before next (desired) clock.
Clock edges occurring within t_en_ck of the
SENABLE falling edge will have indeterminate
effect.
tSEN_CYCLE
Minimum Separation Between SENABLE rising If SENABLE is taken low less than 3µs after it
edge and next SENABLE falling edge.
was taken high, there is a small possibility that
an offset correction will not be initiated.
(see Figure 35).
10
10
3
MHz
ns
µs
NOTES:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
7. The limits for the “Nominal Delay Increment” are derived by taking the limits for the “Maximum Delay” and dividing by the number of steps for the
device. For the ISL59920, ISL59921, and ISL59922 the number of steps is 31; for the ISL59923 the number of steps is 15.
8. All supply currents measured with Delay R = 0ns, G = mid delay, B = full delay.
9. Offset measurements are referred to 75Ω load as shown in Figure 2.
75
VIN
x2 -
VOUT
VOS
75
FIGURE 2. VOS MEASUREMENT CONDITIONS
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6
FN6826.4
August 27, 2015
ISL59920, ISL59921, ISL59922, ISL59923
Typical Performance Curves
0ns
2
1
0
-1
-2
-3
-4
-5
-6
-7
-8 VIN = 700mVP-P
-9 GAIN = 2
-10
100k
1M
20ns
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
2
1
0
-1
-2
-3
-4
-5
-6
-7
VIN = 700mVP-P
-8
GAIN = 1
-9
-10
100k
1M
40ns
10ns
62ns
30ns
50ns
10M
100M
1G
FIGURE 3. ISL59920 FREQUENCY RESPONSE (GAIN = 1)
-2
10.5ns
46.5ns
21ns
-4
30ns
-6
VIN = 700mVP-P
GAIN = 1
100k
1M
10M
100M
NORMALIZED MAGNITUDE (dB)
NORMALIZED MAGNITUDE (dB)
0
10M
100M
1G
0ns
46.5ns
-2
10.5ns
21ns
-4
-6
30ns
-8
VIN = 700mVP-P
GAIN = 2
-10
1G
100k
1M
10M
100M
1G
FREQUENCY (Hz)
FIGURE 5. ISL59921 FREQUENCY RESPONSE (GAIN = 1)
FIGURE 6. ISL59921 FREQUENCY RESPONSE (GAIN = 2)
4
4
NORMALIZED MAGNITUDE (dB)
NORMALIZED MAGNITUDE (dB)
50ns
0
FREQUENCY (Hz)
0ns
2
0
10ns
-2
31ns
20ns
-4
-6
-10
62ns
30ns
2
0ns
-8
40ns
10ns
FIGURE 4. ISL59920 FREQUENCY RESPONSE (GAIN = 2)
2
-10
20ns
FREQUENCY (Hz)
FREQUENCY (Hz)
-8
0ns
VIN = 700mVP-P
GAIN = 1
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 7. ISL59922 FREQUENCY RESPONSE (GAIN = 1)
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7
1G
0ns
2
10ns
0
-2
31ns
-4
-6
-8
-10
20ns
VIN = 700mVP-P
GAIN = 2
100k
1M
10M
100M
1G
FREQUENCY (Hz)
FIGURE 8. ISL59922 FREQUENCY RESPONSE (GAIN = 2)
FN6826.4
August 27, 2015
ISL59920, ISL59921, ISL59922, ISL59923
Typical Performance Curves (Continued)
2
NORMALIZED MAGNITUDE (dB)
NORMALIZED MAGNITUDE (dB)
2
0ns
0
10ns
-2
-4
30ns
20ns
-6
-8
-10
VIN = 700mVP-P
GAIN = 1
100k
1M
10M
100M
10ns
-2
-4
30ns
-8
VIN = 700mVP-P
GAIN = 2
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 9. ISL59923 FREQUENCY RESPONSE (GAIN = 1)
20ns
-6
-10
1G
0ns
0
100M
1G
FIGURE 10. ISL59923 FREQUENCY RESPONSE (GAIN = 2)
250
OUTPUT REFERRED
GAIN = 2
TIMEBASE: 500ns/div
SENABLE: 1V/div
OUTPUT: 100mV/div
GAIN: 1
OUTPUT
SPECTRUM (nV/Hz)
SENABLE
200
150
100
50
0
0M
100M
200M
300M
400M
500M
600M
FREQUENCY (Hz)
FIGURE 11. OFFSET CORRECTION DAC ADJUST
FIGURE 12. ISL59920 NOISE SPECTRUM (10k TO 500MHz)
250
200
160
SPECTRUM (nV/HZ)
SPECTRUM (nV/HZ)
180
140
120
100
80
60
40
20
100M
200M
300M
400M
FREQUENCY (Hz)
500M
600M
FIGURE 13. ISL59921 NOISE SPECTRUM (10k TO 500MHz)
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150
100
50
OUTPUT REFERRED
GAIN = 2
OUTPUT REFERRED
GAIN = 2
0
0M
200
8
0
0M
100M
200M
300M
400M
FREQUENCY (Hz)
500M
600M
FIGURE 14. ISL59922 NOISE SPECTRUM (10k TO 500MHz)
FN6826.4
August 27, 2015
ISL59920, ISL59921, ISL59922, ISL59923
Typical Performance Curves (Continued)
250
3.0
RISE/FALL TIME
SPECTRUM (nV/HZ)
RISE
2.5
200
150
100
50
100M
1.5
FALL
1.0
0.5
OUTPUT REFERRED
GAIN = 2
0
0M
2.0
200M
300M
400M
FREQUENCY (Hz)
500M
0
600M
0
4
FIGURE 16. ISL59920 RISE/FALL TIME vs DELAY TIME
(GAIN = 2)
2.0
3.0
FALL
1.8
1.6
FALL
RISE/FALL TIME
RISE/FALL TIME
2.5
2.0
1.5
RISE
1.0
1.2
RISE
1.0
0.8
0.6
0.2
0
4
12
8
16
20 24 28
DELAY (ns)
32
36
40
44
0
0
48
FIGURE 17. ISL59921 RISE/FALL TIME vs DELAY TIME
(GAIN = 2)
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
DELAY (ns)
FIGURE 18. ISL59922 RISE/FALL TIME vs DELAY TIME
(GAIN = 2)
0
HARMONIC DISTORTION (dBc)
2.5
FALL
2.0
RISE/FALL TIME
1.4
0.4
0.5
1.5
RISE
1.0
0.5
0
12 16 20 24 28 32 36 40 44 48 52 56 60
DELAY (ns)
FIGURE 15. ISL59923 NOISE SPECTRUM (10k TO 500MHz)
0
8
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
DELAY (ns)
FIGURE 19. ISL59923 RISE/FALL TIME vs DELAY TIME
(GAIN = 2)
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9
V+ = +5.0V, V- = -5.0V
VOUT = 1.0VP-P, SINE WAVE
RL = 150
GAIN = 2
-10
-20
-30
-40
2ND HD
-50
-60
3RD HD
-70
-80
2M
6M
10M
14M
18M
22M
26M
30M
34M
38M
FREQUENCY (Hz)
FIGURE 20. HARMONIC DISTORTION vs FREQUENCY
FN6826.4
August 27, 2015
ISL59920, ISL59921, ISL59922, ISL59923
180
160
POSITIVE SUPPLY CURRENT (mA)
POSITIVE SUPPLY CURRENT (mA)
Typical Performance Curves (Continued)
3 CHANNELS
140
120
100
2 CHANNELS
80
1 CHANNEL
GAIN = 2
60
0
4
8
12 16 20 24 28 32 36 40 44 48 52 56 60
DELAY (ns)
200
3 CHANNELS
180
160
140
120
100
2 CHANNELS
1 CHANNEL
80 GAIN = 2
NO INPUT, NO LOAD
60
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32
DELAY (ns)
POSITIVE SUPPLY CURRENT (mA)
220
200
180
3 CHANNELS
160
140
120
100
1 CHANNEL
2 CHANNELS
80 GAIN = 2
NO INPUT, NO LOAD
60
0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48
DELAY (ns)
FIGURE 22. ISL59921 POSITIVE SUPPLY CURRENT (VSP) vs DELAY
TIME
150
140
3 CHANNELS
130
120
110
100
90
2 CHANNELS
1 CHANNEL
80
70 GAIN = 2
NO INPUT, NO LOAD
60
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32
DELAY (ns)
FIGURE 23. ISL59922 POSITIVE SUPPLY CURRENT (VSP) vs DELAY
TIME
FIGURE 24. ISL59923 POSITIVE SUPPLY CURRENT (VSP) vs DELAY
TIME
200
-42.5
NEGATIVE SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
POSITIVE SUPPLY CURRENT (mA)
FIGURE 21. ISL59920 POSITIVE SUPPLY CURRENT (VSP) vs DELAY
TIME
220
180
DELAY = 62ns
160
140
120
DELAY = 0ns
100
80
GAIN = 1 OR 2
60
4.0
4.2
4.4
4.6
4.8
5.0
5.2
5.4
5.6
SUPPLY VOLTAGE (V)
FIGURE 25. ISL59920 ISUPPLY+ vs VSUPPLY+
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10
5.8
6.0
-43.0
-43.5
DELAY = 62ns
-44.0
-44.5
-44.0
DELAY = 0ns
-45.5
-46.0
GAIN = 1 OR 2
-46.5
-4.0 -4.2 -4.4 -4.6
-4.8
-5.0
-5.2
-5.4
-5.6
-5.8
-6.0
SUPPLY VOLTAGE (V)
FIGURE 26. ISL59920 ISUPPLY- vs VSUPPLY-
FN6826.4
August 27, 2015
ISL59920, ISL59921, ISL59922, ISL59923
Typical Performance Curves (Continued)
SUPPLY CURRENT (mA)
220
NEGATIVE SUPPLY CURRENT (mA)
240
DELAY = 46.5ns
200
180
160 GAIN = 1 OR 2
DELAY APPLIED TO ALL
140 CHANNELS
120 NO INPUT, NO LOAD
100
DELAY = 0ns
80
60
4.0
4.2
4.4
4.6
4.8
5.0 5.2
5.4
SUPPLY VOLTAGE (V)
5.6
5.8
6.0
-46.0
GAIN = 2
-46.5
-47.0 DELAY = 46.5ns
-47.5
-48.0
-48.5
-49.0
-49.5
DELAY = 0ns
-50.0
-50.5
-51.0
4.0
FIGURE 27. ISL59921 ISUPPLY+ vs VSUPPLY+
SUPPLY CURRENT (mA)
NEGATIVE SUPPLY CURRENT (mA)
DELAY = 31ns
180
160
GAIN = 1 OR 2
140 DELAY APPLIED TO ALL
120 CHANNELS
NO INPUT, NO LOAD
100
DELAY = 0ns
80
60
4.0
4.2
4.4
4.6
4.8
5.0
5.2
5.4
SUPPLY VOLTAGE (V)
5.6
5.8
6.0
SUPPLY CURRENT (mA)
120
110
100
DELAY = 0ns
70
60
4.0
GAIN = 1 OR 2
DELAY APPLIED TO ALL
CHANNELS
NO INPUT, NO LOAD
4.2
4.4
4.6
4.8
5.0 5.2
5.4
SUPPLY VOLTAGE (V)
5.6
FIGURE 31. ISL59923 ISUPPLY+ vs VSUPPLY+
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5.8
6.0
NEGATIVE SUPPLY CURRENT (mA)
DELAY = 30ns
130
80
4.8
5.0 5.2
5.4
SUPPLY VOLTAGE (V)
5.6
5.8
6.0
GAIN = 2
-45.5 DELAY = 31ns
-46.0
-46.5
-47.0
-47.5
-48.0
-48.5
-49.0 DELAY = 0ns
-49.5
-50.0
-50.5
4.0
4.2
4.4
4.6
4.8
5.0 5.2
5.4
SUPPLY VOLTAGE (V)
5.6
5.8
6.0
FIGURE 30. ISL59922 ISUPPLY- vs VSUPPLY-
150
90
4.6
-45.0
FIGURE 29. ISL59922 ISUPPLY+ vs VSUPPLY+
140
4.4
FIGURE 28. ISL59921 ISUPPLY- vs VSUPPLY-
220
200
4.2
-46.0
-46.5
GAIN = 2
DELAY = 30ns
-47.0
-47.5
-48.0
-48.5 DELAY = 0ns
-49.0
-49.5
4.0
4.2
4.4
4.6
4.8
5.0 5.2
5.4
SUPPLY VOLTAGE (V)
5.6
5.8
6.0
FIGURE 32. ISL59923 ISUPPLY- vs VSUPPLY-
FN6826.4
August 27, 2015
ISL59920, ISL59921, ISL59922, ISL59923
Typical Performance Curves (Continued)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD - QFN EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
4.5
POWER DISSIPATION (W)
4.0
3.54W

JA
=
3.5
3.0
QF
N2
0
31
°C
/W
2.5
2.0
1.5
1.0
0.5
0
0
25
50
75 85 100
150
125
AMBIENT TEMPERATURE (°C)
FIGURE 33. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
TABLE 1. ISL5992x DELAY VARIATIONS
Applications Information
ISL59921
46.5
1.5
ISL59922
31
1.0
ISL59923
30
2.0
1
19
17
18
16
VSPO
2.0
TESTG
62
TESTB
RIN
ISL59920
TESTR
2
PART NUMBER
NOMINAL DELAY
INCREMENT
(ns)
VSP
The ISL59920, ISL59921, ISL59922, and ISL59923 are triple
analog delay lines that provide skew compensation between
three high-speed signals. These devices compensate for time
skew introduced by a typical CAT-5, CAT-6 or CAT-7 cable with
differing electrical lengths (due to different twist ratios) on each
pair. Via their SPI interface, these devices can be programmed to
independently compensate for the three different cable delays
while maintaining 80MHz bandwidth at their maximum setting.
There are four different variations of the ISL5992x (ISL5992x will
be used when talking about characteristics that are common to
all four devices).
MAX DELAY
(ns)
+
CENABLE 7
DELAY LINE
ROUT 15
+
+
+
GOUT 13
+
BOUT 11
DELAY LINE
X2 20
SDATA
SCLOCK
SENABLE
CONTROL LOGIC
[BOTTOM PLATE]
3
5
C
GND
8
BIN
DELAY LINE
VSMO
9
10
+
VSM
6
GIN
GND
4
12
14
FIGURE 34. ISL59920, ISL59921, ISL59922, ISL59923 BLOCK DIAGRAM
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FN6826.4
August 27, 2015
ISL59920, ISL59921, ISL59922, ISL59923
SENABLE
tSEN_CYCLE
tSEN_SETUP
SCLOCK
SDATA
0
*D0 is 0 when addressing the test register
A1
A0
D4
D3
D2
D1
D0*
a
b
v
w
x
y
z
FIGURE 35. SERIAL TIMING
Figure 34 on page 12 shows the ISL5992x block diagram. The
3 analog inputs are ground referenced single-ended signals.
After the signal is received, the delay is introduced by
switching filter blocks into the signal path. Each filter block is
an all-pass filter introducing either 1, 1.5 or 2ns of delay. In
addition to adding delay, each filter block also introduces
some low pass filtering. As a result, the bandwidth of the
signal path decreases from the 0ns delay setting to the
maximum delay setting, as shown in Figures 3 through 10 of
the “Typical Performance Curves”.
In operation, it is best to allocate the most delayed signal 0ns
delay then increase the delay on the other channels to bring
them into line. This will result in delay compensation with the
lowest power and distortion.
TABLE 2. SERIAL BUS DATA (Continued)
vwxyz
ISL59920
DELAY
ISL59921
DELAY
ISL59922
DELAY
ISL59923
DELAY
00110
12
9
6
12
00111
14
10.5
7
14
01000
16
12
8
16
01001
18
13.5
9
18
01010
20
15
10
20
01011
22
16.5
11
22
01100
24
18
12
24
01101
26
19.5
13
26
Serial Bus Operation
01110
28
21
14
28
The ISL5992x is programmed via 8-bit words sent through its
serial interface. The first bit (MSB) of SDATA is latched on the
first falling clock edge after SENABLE goes low, as shown in
Figure 35. This bit should be a 0 under all conditions. The next
two bits determine the color register to be written to: 01 = R,
02 = G, and 03 = B (00 is reserved for the test register). The
final five bits set the delay for the specified color. After 8 bits
are latched, any additional clocks are treated as a new word
(data is shifted directly to the final registers as it is clocked in).
This allows the user to write (for example) the 24 bits of data
necessary for R, G, and B as a single 24-bit word. It is the user's
responsibility to send complete multiples of 8 clock cycles. The
serial state machine is reset on the falling edge of SENABLE,
so any data corruption that may have occurred due to too
many or too few clocks can be corrected with a new word with
the correct number of clocks. The initial value of all registers
on power-up is 0.
01111
30
22.5
15
30
10000
32
24
16
N/A
10001
34
25.5
17
N/A
10010
36
27
18
N/A
10011
38
28.5
19
N/A
10100
40
30
20
N/A
10101
42
31.5
21
N/A
10110
44
33
22
N/A
10111
46
34.5
23
N/A
11000
48
36
24
N/A
11001
50
37.5
25
N/A
11010
52
39
26
N/A
11011
54
40.5
27
N/A
TABLE 2. SERIAL BUS DATA
vwxyz
ISL59920
DELAY
ISL59921
DELAY
ISL59922
DELAY
ISL59923
DELAY
00000
0
0
0
0
00001
2
1.5
1
2
00010
4
3
2
4
00011
6
4.5
3
6
00100
8
6
4
8
00101
10
7.5
5
10
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13
11100
56
42
28
N/A
11101
58
43.5
29
N/A
11110
60
45
30
N/A
11111
62
46.5
31
N/A
NOTE: Delay register word = 0abvwxyz; Red register - ab = 01; Green
register - ab = 10; Blue register - ab = 11; vwxyz selects delay; ab = 00
writes to the test register to change the DAC slice level.
FN6826.4
August 27, 2015
ISL59920, ISL59921, ISL59922, ISL59923
Offset Compensation
Offset Calibration with Sync-On-Video
To counter the effects of offset, the ISL5992x incorporates an
offset compensation circuit that reduces the offset to less than
±25mV. An offset correction cycle is triggered by the rising edge
of the SENABLE pin after writing a delay word to any of the 3
channels. The offset calibration starts about 500ns after the
SENABLE rising edge to allow the ISL5992x time to settle
(electrically and thermally) to the new delay setting. It lasts
about 2.5µs, for a total offset correction time of 3.0µs. During
calibration, the ISL5992x’s inputs are internally shorted
together (however the characteristics of the ISL5992x’s
differential input pins stay the same), and the offset of the
output stage is adjusted until it has been minimized.
The offset correction mechanism temporarily disconnects the
input signals to perform the offset calibration. This introduces
several discontinuities in the video signal, as shown in
Figure 11 on page 8:
• 200mV to 300mV spike when calibration is engaged
• Successive approximation offset null
• 200mV to 300mV spike when calibration is disengaged
• In addition, because an offset calibration is performed any
time the delay changes, the output video signal may be
moved forward or back in time by up to 62ns.
In addition to automatically triggering after a delay change (or
any register write), an additional offset calibration may be
initiated at any time, such as:
If the video signals going through the ISL5992x contain only
video (with no sync signals), this appears as a 2µs “sparkle” on
the screen - usually it is not even visible to the eye.
• When the die temperature changes. Applying power to the
ISL5992x will cause the die temperature to quickly increase
then slowly settle over 20 to 30ns. Because the ISL5992x
powers-down unused delay stages (to minimize power
consumption), the die temp will also change and settle after a
delay change. Initiating an offset 20ns (or longer, depending
on the thermal characteristics of the system) after power-on
or a delay change will minimize the offset in normal operation
thereafter.
However if sync signals are embedded on the video, the spikes
may be misinterpreted as a sync signal, causing the
downstream circuitry to see an asynchronous sync pulse. In
some receiving systems (typically monitors), a single
asynchronous sync pulse can cause the system to think the
video signal has changed. Depending on the receiving
monitor’s design, this can initiate a new video acquisition cycle
(for example, the monitor blanks the screen while it measures
the “new” HSYNC and VSYNC timing, selects the right mode,
and optimizes the image). This can cause the monitor to go
blank for up to several seconds after a single delay change.
• When the ambient temperature changes. If you are
monitoring the temperature, initiate a calibration every time
the temperature shifts by 5 to 10 degrees. If you are not
monitoring temperature, initiate a calibration periodically, as
expected by the environment the device is in.
• After a CENABLE (Chip Enable) cycle. The CENABLE pin may
be taken low to put the ISL5992x in a low power standby
mode to conserve power when not needed. When the
CENABLE pin goes high to exit this low power mode, the
ISL5992x will recall the delay settings but it will not recall
the correct offset calibration settings, so to maintain low
offset, a write to the delay register is required after a
CENABLE cycle. Offset errors may be as large as ±200mV
coming out of standby mode - recalibration is a necessity.
For best performance, initiate an additional calibration
again once the die temperature has settled (20 to 30ns after
coming out of standby).
• After a gain change (X2 pin changes state). The systematic
offset is different for a gain of x1 vs. a gain of x2, so an offset
calibration is recommended after a gain change. However in
a typical application the gain is permanently fixed at x1 or x2,
so this is not usually a concern.
Since this only happens at power-on and when the delays are
initially set, this is not a problem in normal use, but if the
monitor is blanking for several seconds every time the delay is
adjusted, it can cause calibration to take longer than
absolutely necessary. If this behavior is undesirable, it can be
eliminated as follows:
1. Synchronize the rising edge of SENABLE to the sync pulse,
so that the SENABLE goes high immediately after the
trailing edge of the sync pulse. SENABLE can be taken low
and the serial data written asynchronously at any time - it
is the rising edge of SENABLE that triggers a calibration.
2. If the Sync Processor is part of the same design as
ISL5992x, ensure that the sync processor ignores the first
x microseconds after a valid sync, where x = 3µs + the delay
between the end of a sync and rising edge of SENABLE. This
will prevent the sync processor from generating invalid sync
signals due to the spikes.
3. If the Sync Processor is external to the design with the
ISL5992x (video with Sync-On-Green, for example), the
video signal should disconnected from the ISL59920 and
shorted to ground via an analog switch for the first x
microseconds after a valid sync, where x = 3µs + the delay
between the end of a sync and rising edge of SENABLE. This
will remove the calibration signals from the video signal.
These steps are only necessary if the sync signal is embedded
on the video.
Note: Avoid possible monitor blanking during skew
adjustment.
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14
FN6826.4
August 27, 2015
ISL59920, ISL59921, ISL59922, ISL59923
Test Pins
Three test pins are provided (Test R, Test G, Test B). During
normal operation, the test pins output pulses of current for a
duration of the overlap between the inputs, as shown in
Figure 36:
4 INTERNAL DAC
SLICING LEVEL
000wxyz0
COMPARATORS
REDOUT
A
TESTR pulse = REDOUT (A) with respect to GREENOUT (B)
TESTG pulse = GREENOUT with respect to BLUEOUT
TESTR
B
TESTB pulse = BLUEOUT with respect to REDOUT
Averaging the current gives a direct measure of the delay
between the two edges. When A precedes B, the current pulse is
+50µA, and the output voltage goes up. When B precedes A, the
pulse is -50µA.
For the logic to work correctly, A and B must have a period of
overlap while they are high (a delay longer than the pulse width
cannot be measured).
GREENOUT
A
TESTG
B
BLUEOUT
Signals A and B are derived from the video input by comparing the
video signal with a slicing level, which is set by an internal DAC.
This enables the delay to be measured either from the rising edges
of sync-like signals encoded on top of the video or from a
dedicated set-up signal. The outputs can be used to set the correct
delays for the signals received.
A
TESTB
B
A
B
The DAC level is set through the serial input by bits 1 through 4
directed to the test register (00).
OUTPUT
Internal DAC Voltage
FIGURE 36. DELAY DETECTOR
The slice level of the internal DAC may be programmed by writing
a byte to the test register (00). Table 3 shows the values that
should be written to change the DAC slice level. Please keep in
mind when writing to the test register that the LSB should always
be zero.
TABLE 3. DAC VOLTAGE RANGE - INPUT REFERRED
Referred to the input, the DAC slice range for the ISL5992x is cut
in half for gain of 2 mode because the slicing occurs after the
x1/x2 stage output amplifier. (In the EL9115, the slicing occurred
before the amplifier so the range of the DAC voltage was the
same for either gain of 1 or gain of 2).
wxyz
DAC RANGE [mV]
(GAIN 1)
DAC RANGE [mV]
(GAIN 2)
1000
-400
-200
1001
-350
-175
1010
-300
-150
1011
-250
-125
1100
-200
-100
1101
-150
-75
1110
-100
-50
1111
-50
-25
0000
0
0
0001
50
25
0010
100
50
0011
150
75
0100
200
100
0101
250
125
0110
300
150
0111
350
175
NOTE: Test Register word = 000wxyz0. wxyz fed to DAC. z is LSB
Submit Document Feedback
15
FN6826.4
August 27, 2015
ISL59920, ISL59921, ISL59922, ISL59923
CENABLE at Power-On
Power Dissipation
To guarantee proper operation, the CENABLE pin should be held
low for at least 30ms after the power supply has settled to within
5% of its final value.
As the delay setting increases, additional filter blocks turn on and
insert into the signal path. When the delay per channel
increments, VSP current increases by 0.9mA while VSM does not
change significantly. Under the extreme settings, the positive
supply current reaches 141mA and the negative supply current
can be 41mA. Operating at ±5V power supply, the worst-case
ISL5992x power dissipation is shown by Equation 1:
If CENABLE cannot be guaranteed to be held low during this time,
an RC delay can be inserted between the CENABLE source and
the CENABLE input to meet this requirement as shown in
Figure 37. R1 and C1 generate an ~33ms delay, and D1
discharges any charge on C1 when the power to the ISL5992x is
removed.
+5V
R1
33k
ISL5992x
CENABLE
C1
1F
FIGURE 37. CENABLE RC DELAY
Submit Document Feedback
16
(EQ. 1)
The minimum JA required for long term reliable operation of the
ISL5992x is calculated using Equation 2:
 JA =  T J – T A   PD = 55 C  W
VSP
D1
PD = 5  141mA + 5  41mA = 910mW
(EQ. 2)
Where:
TJ is the maximum junction temperature (+135°C)
TA is the maximum ambient temperature (+85°C)
For a 20 Ld package on a well laid-out PCB with good
connectivity between the QFN’s pad and the PCB copper area,
31°C/W JA thermal resistance can be achieved. This yields a
much higher power dissipation of 3.54W using Equation 2 (see
Figure 33). To disperse the heat, the bottom heat spreader must
be soldered to the PCB. Heat flows through the heat spreader to
the circuit board copper then spreads and convects to air. Thus,
the PCB copper plane becomes the heatsink (see TB389). This
has proven to be a very effective technique. A separate
application note, which details the 20 Ld QFN PCB design
considerations, is available.
FN6826.4
August 27, 2015
ISL59920, ISL59921, ISL59922, ISL59923
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
CHANGE
August 27, 2015
FN6826.4
Updated Ordering Information table on page 2.
September 25, 2014
FN6826.3
Added Revision History.
Converted to new datasheet template.
Added note on CENABLE delay to CENABLE entry in Pin Descriptions table on page 2.
Added “CENABLE at Power-On” on page 16.
About Intersil
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17
FN6826.4
August 27, 2015
ISL59920, ISL59921, ISL59922, ISL59923
Quad Flat No-Lead Plastic Package (QFN)
A
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220)
B
N
(N-1)
(N-2)
D
1
2
3
L20.5x5C
MILLIMETERS
SYMBOL
PIN #1
I.D. MARK
E
(2X)
0.075 C
TOP VIEW
(2X)
(N/2)
0.075 C
SEATING
PLANE
MAX
NOTES
A
0.80
0.90
1.00
-
0.00
0.02
0.05
-
b
0.28
0.30
0.32
-
c
0.20 REF
-
D
5.00 BASIC
-
D2
3.70 REF
8
E
5.00 BASIC
-
E2
3.70 REF
8
e
0.10 C
e
NOMINAL
A1
L
C
MIN
0.65 BASIC
0.35
0.40
0.45
-
N
20
4
ND
5 REF
6
NE
5 REF
5
Rev. 0 6/06
0.08 C
N LEADS AND
EXPOSED PAD
NOTES:
SEE DETAIL “X”
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
SIDE VIEW
2. Tiebar view shown is a non-functional feature.
3. Bottom-side pin #1 I.D. is a diepad chamfer as shown.
4. N is the total number of terminals on the device.
b
L
N LEADS
(N-2)
(N-1)
N
0.01 M C A B
PIN #1 I.D.
3
1
2
3
5. NE is the number of terminals on the “E” side of the package
(or Y-direction).
6. ND is the number of terminals on the “D” side of the package
(or X-direction). ND = (N/2)-NE.
7. Inward end of terminal may be square or circular in shape with
radius (b/2) as shown.
(E2)
8. If two values are listed, multiple exposed pad options are available.
Refer to device-specific datasheet.
(N/2)
NE 5
9. One of 10 packages in MDP0046
7
(D2)
BOTTOM VIEW
C
2
(c)
A
A1
(L)
N LEADS
DETAIL “X”
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in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
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18
FN6826.4
August 27, 2015