TVS Diodes Transient Voltage Suppressor Diodes ESD5V5U5ULC Ultra-low Capacitance ESD / Transient / Surge Protection Array ESD5V5U5ULC Data Sheet Revision 1.2, 2013-02-07 Final Power Management & Multimarket Edition 2013-02-07 Published by Infineon Technologies AG 81726 Munich, Germany © 2013 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). 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ESD5V5U5ULC Revision History: Rev. 1.1, 2013-02-07 Page or Item Subjects (major changes since previous revision) Revision 1.2, 2013-02-07 4 Halogen free deleted Trademarks of Infineon Technologies AG AURIX™, BlueMoon™, COMNEON™, C166™, CROSSAVE™, CanPAK™, CIPOS™, CoolMOS™, CoolSET™, CORECONTROL™, DAVE™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, EUPEC™, FCOS™, HITFET™, HybridPACK™, ISOFACE™, I²RF™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OmniTune™, OptiMOS™, ORIGA™, PROFET™, PRO-SIL™, PRIMARION™, PrimePACK™, RASIC™, ReverSave™, SatRIC™, SIEGET™, SINDRION™, SMARTi™, SmartLEWIS™, TEMPFET™, thinQ!™, TriCore™, TRENCHSTOP™, X-GOLD™, XMM™, X-PMU™, XPOSYS™. Other Trademarks Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, PRIMECELL™, REALVIEW™, THUMB™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™, FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG. FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. Mifare™ of NXP. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Sattelite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited. Last Trademarks Update 2010-06-09 Final Data Sheet 3 Revision 1.2, 2013-02-07 ESD5V5U5ULC Ultra-low Capacitance ESD / Transient / Surge Protection Array 1 Ultra-low Capacitance ESD / Transient / Surge Protection Array 1.1 Features • • • • • • • ESD / Transient protection of high speed data lines exceeding – IEC61000-4-2 (ESD): ±25 kV (air / contact) – IEC61000-4-4 (EFT): ±2.5 kV / ±50 A (5/50 ns) – IEC61000-4-5 (surge): ±6 A (8/20 μs) Maximum working voltage: VRWM = 5.5 V Extremely low capacitance CL = 0.45 pF I/O to GND (typical) Very low dynamic resistance: RDYN I/O to GND = 0.2 Ω (typical) Very low reverse clamping voltage: VCL = 9 V (typical) at IPP = 16 A Protection of VBUS with one line freely selectable Pb-free (RoHS compliant) package 1.2 • • • Application Examples Protection of all I/O and VBUS lines in dual USB2.0 ports 10/100/100 Ethernet DVI, HDM, FireWire 1.3 Product Description Pin 6 Pin 5 Pin 4 Pin 1 Pin 4 Pin 3 Pin 5 Pin 6 SC74 Pin 1 Pin 2 GND Pin 3 Pin 2 b) Schematic diagram a) Pin configuration ESD5V5U5ULC_PinConf_and_SchematicDiag.vsd Figure 1 Pin Configuration and Schematic Diagram Table 1 Ordering Information Type Package Configuration ESD5V5U5ULC SC74 5 lines, uni-directional Final Data Sheet 4 Marking code 20 Revision 1.2, 2013-02-07 ESD5V5U5ULC Characteristics 2 Characteristics Table 2 Maximum Rating at TA = 25 °C, unless otherwise specified Parameter Symbol Values Unit Min. Typ. Max. VESD -25 – 25 kV IPP -6 – 6 A Operating temperature range TOP -40 – 125 °C Storage temperature 1) VESD according to IEC61000-4-2 2) IPP according to IEC61000-4-5 Tstg -65 – 150 °C ESD contact discharge 1) Peak pulse current (tp = 8/20 μs) 2) Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. 2.1 Electrical Characteristics at TA = 25 °C, unless otherwise specified Figure 2 ! "# ! # "# Definitions of Electrical Characteristics[1] Final Data Sheet 5 Revision 1.2, 2013-02-07 ESD5V5U5ULC Characteristics Table 3 DC Characteristics at TA = 25 °C, unless otherwise specified Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Reverse working voltage VRWM – – 5.5 V I/O to GND Reverse current – <1 100 nA VR = 5.5 V, I/O to GND Unit Note / Test Condition pF VR = 0 V, f = 1 MHz, Table 4 IR RF Characteristics at TA = 25 °C, unless otherwise specified Parameter Line capacitance Symbol CL Values Min. Typ. Max. – 0.45 1 I/O to GND – 0.23 0.5 pF VR = 0 V, f = 1 MHz, I/O to I/O Line capacitance CL – 0.25 – pF VR = 0 V, f = 825 MHz, I/O to GND – 0.13 – pF VR = 0 V, f = 825 MHz, I/O to I/O Capacitance variation between I/O and GND ∆Ci/o-GND – Capacitance variation between I/O ∆Ci/o-i/o Final Data Sheet 0.02 – pF VR = 0 V, f = 1 MHz, I/O to GND – 0.01 – pF VR = 0 V, f = 1 MHz, I/O to I/O 6 Revision 1.2, 2013-02-07 ESD5V5U5ULC Characteristics Table 5 ESD Characteristics at TA = 25 °C, unless otherwise specified Parameter Reverse clamping voltage1) Symbol VCL Values Unit Note / Test Condition Min. Typ. Max. – 9 – V IPP = 1 A, tp = 8/20 μs, I/O pin to GND – 12 – V IPP = 3 A, tp = 8/20 μs, I/O pin to GND Reverse clamping voltage2)[2] VCL – 8.9 – V IPP = 16 A, tp = 100 ns, I/O pin to GND – 11.5 – V IPP = 30 A, tp = 100 ns, I/O pin to GND Forward clamping voltage1) VFC – 1.75 – V IPP = 1 A, tp = 8/20 μs, GND pin to I/O – 2.5 – V IPP = 3 A,tp = 8/20 μs, GND pin to I/O Forward clamping voltage2)[2] VFC – 5.4 – V IPP = 16 A, tp = 100 ns, GND pin to I/O – 9.2 – V IPP = 30 A, tp = 100 ns, GND pin to I/O Dynamic resistance I/O to GND2)[2] RDYN, I/O – 0.2 – Ω 0.3 – Ω to GND RDYN, Dynamic resistance 2) GND to I/O [2] GND to I/O 1) IPP according to IEC61000-4-5 – 2) Please refer to Application Note AN210[2]. TLP parameter: Z0 = 50 Ω , tp = 100ns, tr = 300ps, averaging window: t1 = 30 ns to t2 = 60 ns, extraction of dynamic resistance using least squares fit of TLP charactertistic between IPP1 = 10 A and IPP2 = 40 A. Final Data Sheet 7 Revision 1.2, 2013-02-07 ESD5V5U5ULC Characteristics 2.2 Typical Characteristics at TA = 25 °C, unless otherwise specified 0.6 0.5 CL [pF] 0.4 0.3 0.2 0.1 0 Figure 3 0 0.5 1 1.5 2 2.5 VR [V] 3 3.5 4 4.5 5 Line capacitance CL = f(VR) at f = 825 MHz 0.6 0.5 CL [pF] 0.4 I/O to GND 0.3 0.2 I/O to I/O 0.1 0 6 10 Figure 4 7 8 10 10 f [Hz] 9 10 10 10 Line capacitance CL = f(f), VR = 0 V Final Data Sheet 8 Revision 1.2, 2013-02-07 ESD5V5U5ULC Characteristics 0 2 -|S21| [dB] -5 -10 -15 -20 5 10 6 10 7 10 10 8 9 10 10 10 f [Hz] Figure 5 Insertion loss IL = f(f), VR = 0 V 100 10 -1 10 -2 10 -3 IF [A] 10-4 10 -5 10-6 10 -7 10 -8 10-9 Figure 6 0 0.5 VF [V] 1 Forward characteristic, IF = f(VF), current forced Final Data Sheet 9 Revision 1.2, 2013-02-07 ESD5V5U5ULC Characteristics IR [A] 10-7 10 -8 10 -9 10-10 10-11 10-12 Figure 7 -50 -25 0 25 50 TA [°C] 75 100 125 150 Reverse current IR = f(TA), VR = 5.5 V (typical) 10 -3 IR [A] 10-4 10 -5 10 -6 10 -7 10 -8 10 -9 10 -10 10-11 10-12 Figure 8 0 5 VR [V] 10 Reverse characteristic, IR = (VR), voltage forced Final Data Sheet 10 Revision 1.2, 2013-02-07 ESD5V5U5ULC Characteristics 50 30 ESD5V5U5ULC RDYN 25 20 ITLP [A] 40 RDYN=0.2Ω 30 15 20 10 10 5 0 5 10 15 20 25 Equivalent VIEC [kV] 60 0 VTLP [V] TLP characteristic I/O to GND Note: [2] 60 50 30 ESD5V5U5ULC RDYN 25 20 ITLP [A] 40 RDYN=0.3Ω 30 15 20 10 10 5 0 5 10 15 20 25 Equivalent VIEC [kV] Figure 9 0 VTLP [V] Figure 10 TLP characteristic GND to I/O Note: [2] Note: TLP parameter: Z0 = 50 Ω, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns, extraction of dynamic resistance using least squares fit of TLP charactertistic between IPP1 = 10 A and IPP2 = 40 A. The equivalent stress level VIEC according IEC 61000-4-2 (R = 330 Ω , C = 150 pF) is calculated at the broad peak of the IEC waveform at t = 30 ns with 2 A / kV Final Data Sheet 11 Revision 1.2, 2013-02-07 ESD5V5U5ULC Application Information 3 Application Information RX1 Line-pair #4 RJ45 Ethernet connector Line-pair #3 Quad Transformer Line-pair #2 HOST Gigabit Ethernet Transceiver (PHY) Line-pair #1 E S D5V 5U5ULC_E thernet_application .vs d 1:1 primary ESD current 1:1 secondary Secondary ESD/surge ESD current protection 75 Ohm Res common 2nF cap Res Device Gigabit Ethernet Transceiver (PHY) Quad Transformer Ethernet cable Twisted Pair TX1 RJ45 Ethernet connector RX1 Figure 11 Line-pair #4 secondary Secondary ESD/surge ESD current protection Line-pair #3 1:1 TX1 Line-pair #2 Line-pair #1 1:1 primary ESD current 75 Ohm Res common 2nF cap Res Ethernet E S D5V 5U5ULC_US B20_applic ation .v s d Host controller D1+ Data #1 IN / OUT Device controller TVS ESD diodes array D+ D+ D1- D1+ Data #1 IN / OUT D1D- USB2.0 Host1 LS/FS/HS Vcc DUSB2.0 Device1 LS/FS/HS GND USB2.0 cable#1 Vcc Vcc USBConnectors USB2.0 Host2 LS/FS/HS Data #2 IN / OUT D2+ D2- USB2.0 Device2 LS/FS/HS USB2.0 cable#2 GND D+ Vcc D- D+ D- D2+ D2- Data #2 IN / OUT TVS ESD diodes array Figure 12 USB2.0 Final Data Sheet 12 Revision 1.2, 2013-02-07 ESD5V5U5ULC Ordering Information Scheme (Examples) 4 ESD Ordering Information Scheme (Examples) 0P1 RF - XX YY Package XX = Pin number (i.e.: 02 = 2 pins; 03 = 3 pins) YY = Package family: LS = TSSLP LRH = TSLP For Radio Frequency Applications Line Capacitance CL in pF: (i.e.: 0P1 = 0.1pF) ESD 5V3 U n U - XX YY Package or Application XX = Pin number (i.e.: 02 = 2 pins; 03 = 3 pins) YY = Package family: LS = TSSLP LRH = TSLP S = SOT363 U = SC74 XX = Application family: LC = Low Clamp HDMI Uni- / Bi-directional or Rail to Rail protection Number of protected lines (i.e.: 1 = 1 line; 4 = 4 lines) Capacitance: Standard (>10pF), Low (<10pF), Ultra-low (<1pF) Maximum working voltage VRWM in V: (i.e.: 5V3 = 5.3V) Figure 13 Ordering information scheme Final Data Sheet 13 Revision 1.2, 2013-02-07 ESD5V5U5ULC Package Information 5 Package Information 5.1 PG-SC74 (mm) 2.9 ±0.2 (2.25) B 1.1 MAX. 4 1 2 3 0.35 +0.1 -0.05 Pin 1 marking 0.2 1.6 ±0.1 5 2.5 ±0.1 6 0.25 ±0.1 0.15 +0.1 -0.06 (0.35) A B 6x M 0.1 MAX. 0.95 0.2 1.9 M A SC74-PO V04 Figure 14 PG-SC74: Package overview 2.9 1.9 0.5 0.95 SC74-FPR V04 Figure 15 PG-SC74: Footprint 0.2 2.7 8 4 Pin 1 marking Figure 16 PG-SC74: Packing Figure 17 PG-SC74: Marking (example) Final Data Sheet 3.15 1.15 SC74-TP 14 Revision 1.2, 2013-02-07 ESD5V5U5ULC References References [1] On-chip ESD protection for integrated circuits, Albert Z. H. Wang, ISBN:0-7923-7647-1 [2] Infineon Technologie AG - Application Note AN210: Effective ESD Protection Design at System Level Using VF-TLP Characterization Methodology Final Data Sheet 15 Revision 1.2, 2013-02-07 w w w . i n f i n e o n . c o m Published by Infineon Technologies AG