TVS Diodes Transient Voltage Suppressor Diodes ESD102-U2-099EL 2-Line Ultra-low Capacitance ESD / Transient Protection Diodes ESD102-U2-099EL Data Sheet Revision 1.1, 2013-05-15 Final Power Management & Multimarket Edition 2013-05-15 Published by Infineon Technologies AG 81726 Munich, Germany © 2013 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. 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ESD102-U2-099EL Revision History: Revision 1.0, 2013-03-21 Page or Item Subjects (major changes since previous revision) Revision 1.1, 2013-05-15 Trademarks of Infineon Technologies AG AURIX™, BlueMoon™, COMNEON™, C166™, CROSSAVE™, CanPAK™, CIPOS™, CoolMOS™, CoolSET™, CORECONTROL™, DAVE™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, EUPEC™, FCOS™, HITFET™, HybridPACK™, ISOFACE™, I²RF™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OmniTune™, OptiMOS™, ORIGA™, PROFET™, PRO-SIL™, PRIMARION™, PrimePACK™, RASIC™, ReverSave™, SatRIC™, SIEGET™, SINDRION™, SMARTi™, SmartLEWIS™, TEMPFET™, thinQ!™, TriCore™, TRENCHSTOP™, X-GOLD™, XMM™, X-PMU™, XPOSYS™. Other Trademarks Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, PRIMECELL™, REALVIEW™, THUMB™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™, FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG. FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. Mifare™ of NXP. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Sattelite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited. Last Trademarks Update 2010-06-09 Final Data Sheet 3 Revision 1.1, 2013-05-15 ESD102-U2-099EL 2-Line Ultra-low Capacitance ESD / Transient Protection Diodes 1 2-Line Ultra-low Capacitance ESD / Transient Protection Diodes 1.1 Features • • • • • • • ESD / transient protection of high speed data lines exceeding: – IEC61000-4-2 (ESD): ±20 kV (air / contact) – IEC61000-4-4 (EFT): ±2.5 kV / 50 A (5/50ns) – IEC61000-4-5 (Surge): ±3 A (8/20μs) Maximum working voltage: VRWM = 3.3 V Ultra low capacitance CL = 0.4 pF (typ.) I/O to GND, 0.2 pF (typ.) I/O to I/O Very low clamping voltage: VCL = 8 V (typ.) at IPP = 16 A Very low dynamic resistance: RDYN = 0.19 Ω (typ.) TSLP-4-10 package with pad pitch 0.4 mm, smallest 2 line package Pb-free and halogen free package (RoHS compliant) 1.2 • • • Application Examples USB 3.0, 10/100/1000 Ethernet, Firewire DVI, HDMI, S-ATA, DisplayPort Mobile HDMI Link, MDDI, MIPI, etc. 1.3 Product Description ESD102-U2-099EL TSLP-4-x Pin 1 A1 A2 B1 B2 Pin 1 Pin 4 A1 A2 B1 Pin 2 B2 Pin 3 b) Schematic diagram a) Pin configuration PG-TSLP-4-x_Dual_Diode_PinConf_and_SchematicDiag.vsd Figure 1 Pin Configuration and Schematic Diagram Table 1 Ordering Information Type Package Configuration Marking code ESD102-U2-099EL TSLP-4-10 2 Lines anti-parallel, uni-directional B Final Data Sheet 4 Revision 1.1, 2013-05-15 ESD102-U2-099EL Characteristics 2 Characteristics Table 2 Maximum Rating at TA = 25 °C, unless otherwise specified Parameter Symbol Values Unit Min. Typ. Max. VESD -20 – 20 kV IPP -3 – 3 A Operating temperature TOP -40 – 125 °C Storage temperature 1) VESD according to IEC61000-4-2 2) IPP according to IEC61000-4-5 Tstg -65 – 150 °C ESD air / contact discharge 1) Peak pulse current (tp = 8/20 μs) 2.1 2) Electrical Characteristics at TA = 25 °C, unless otherwise specified VF Forward voltage IF Forward current VR IR IF RDYN V Trig I PP Reverse voltage VCL RDYN Reverse current VHold V RWM VHold VTrig VR VRWM VCL VFC VF Dynamic resistance Triggering reverse voltage Clamping voltage Holding reverse voltage Reverse working voltage maximum VFC Forward clamping voltage ITrig Triggering reverse current ITrig IHold Holding reverse current IHold IPP IRWM IRWM RDYN Peak pulse current Reverse working current maximum -I PP IR Diode_Charac teris tic _Curv e_with _s napbac k_Uni-direc tional .v s d Figure 2 Definitions of electrical characteristics[1] Table 3 DC Characteristics at TA = 25 °C, unless otherwise specified Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Reverse working voltage VRWM – – 3.3 V I/O to GND Reverse current – 1 50 nA VR = 3.3 V, I/O to GND Final Data Sheet IR 5 Revision 1.1, 2013-05-15 ESD102-U2-099EL Characteristics Table 4 RF Characteristics at TA = 25 °C, unless otherwise specified Parameter Symbol 1) Line capacitance CL Values Unit Note / Test Condition Min. Typ. Max. – 0.4 0.65 pF VR = 0 V, f = 1 MHz, I/O to GND – 0.2 0.35 pF VR = 0 V, f = 1 MHz, I/O to I/O Channel capacitance matching between I/O to GND ∆Ci/o-GND – Channel capacitance matching between I/O to I/O ∆Ci/o-i/o – 0.01 – pF VR = 0 V, f = 1 MHz, I/O to GND 0.005 – pF VR = 0 V, f = 1 MHz, I/O to I/O 1) Total capacitance line to ground Table 5 ESD Characteristics at TA = 25 °C, unless otherwise specified Parameter Symbol 1) Clamping voltage [2] Forward clamping voltage1) [2] Dynamic resistance1) [2] VCL VFC RDYN Values Unit Note / Test Condition Min. Typ. Max. – 8 – V ITLP = 16 A, from I/O to GND – 11 – V ITLP = 30 A, from I/O to GND – 6 – V ITLP = 16 A, from GND to I/O – 9 – V ITLP = 30 A, from GND to I/O – 0.19 – Ω I/O to GND 0.23 – Ω GND to I/O 1) Please refer to Application Note AN210. TLP parameter: Z0 = 50 Ω , tp = 100ns, tr = 300ps, averaging window: t1 = 30 ns to t2 = 60 ns, extraction of dynamic resistance using least squares fit of TLP characteristic between ITLP1 = 10 A and ITLP2 = 40 A. – Final Data Sheet 6 Revision 1.1, 2013-05-15 ESD102-U2-099EL Typical Characteristics at TA = 25 °C, unless otherwise specified Typical Characteristics at TA = 25 °C, unless otherwise specified 10 -7 10 -8 10-9 IR [A] 3 10-10 10 -11 10-12 1 2 VR [V] 3 4 Reverse current, IR = (VR) 10 -6 10 -7 10 -8 IR [A] Figure 3 0 10-9 25 50 75 100 125 150 TA [°C] Figure 4 Reverse current: IR = f(TA), VR = 3.3 V Final Data Sheet 7 Revision 1.1, 2013-05-15 ESD102-U2-099EL Typical Characteristics at TA = 25 °C, unless otherwise specified 0.8 0.7 CL [pF] 0.6 0.5 0.4 0.3 0.2 Figure 5 0 0.5 1 1.5 2 VR [V] 2.5 3 3.5 Line capacitance: CL = f(VR), f = 1MHz, from I/O to GND Final Data Sheet 8 Revision 1.1, 2013-05-15 ESD102-U2-099EL Typical Characteristics at TA = 25 °C, unless otherwise specified 50 25 ESD102-U2-099EL RDYN 40 20 30 15 20 10 10 5 0 0 -10 -5 -20 -10 Equivalent VIEC [kV] ITLP [A] RDYN = 0.19 Ω RDYN = 0.23 Ω -30 -15 -40 -20 -50 -25 -20 -15 -10 -5 0 5 10 15 20 -25 25 VTLP [V] Figure 6 Clamping voltage VTLP = f(ITLP)[2] Note: TLP parameter: Z0 = 50 Ω, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns, extraction of dynamic resistance using least squares fit of TLP characteristic between ITLP1 = 10 A and ITLP2 = 40 A. The equivalent stress level VIEC according IEC 61000-4-2 (R = 330 Ω, C = 150 pF) is calculated at the broad peak of the IEC waveform at t = 30 ns with 2 A / kV Final Data Sheet 9 Revision 1.1, 2013-05-15 ESD102-U2-099EL Typical Characteristics at TA = 25 °C, unless otherwise specified 5 ESD102-U2-099EL RDYN 4 3 RDYN = 0.70 Ω 2 IPP [A] 1 0 -1 -2 RDYN = 0.44 Ω -3 -4 -5 -10 Figure 7 -8 -6 -4 -2 0 VCL [V] 2 4 6 8 10 Pulse current (IEC61000-4-5) versus clamping voltage: IPP = f(VCL) Final Data Sheet 10 Revision 1.1, 2013-05-15 ESD102-U2-099EL Typical Characteristics at TA = 25 °C, unless otherwise specified 80 Scope: 6 GHz, 20 GS/s 60 VCL [V] VCL-max-peak = 81 [V] VCL-30ns-peak = 7 [V] 40 20 0 -20 -100 Figure 8 0 100 200 300 400 tp [ns] 500 600 700 800 900 IEC61000-4-2 VCL = f(t), 8 kV positive pulse from pin 1 to pin 2 20 Scope: 6 GHz, 20 GS/s 0 VCL [V] -20 VCL-max-peak = -72 [V] -40 VCL-30ns-peak = -3 [V] -60 -80 -100 Figure 9 0 100 200 300 400 tp [ns] 500 600 700 800 900 IEC61000-4-2 VCL = f(t), 8 kV negative pulse from pin 1 to pin 2 Final Data Sheet 11 Revision 1.1, 2013-05-15 ESD102-U2-099EL Typical Characteristics at TA = 25 °C, unless otherwise specified 100 Scope: 6 GHz, 20 GS/s VCL [V] 80 VCL-max-peak = 104 [V] VCL-30ns-peak = 9 [V] 60 40 20 0 -20 -100 Figure 10 0 100 200 300 400 tp [ns] 500 600 700 800 900 IEC61000-4-2 VCL = f(t), 15 kV positive pulse from pin 1 to pin 2 20 Scope: 6 GHz, 20 GS/s 0 VCL [V] -20 -40 VCL-max-peak = -98 [V] VCL-30ns-peak = -7 [V] -60 -80 -100 -100 Figure 11 0 100 200 300 400 tp [ns] 500 600 700 800 900 IEC61000-4-2 VCL = f(t), 15 kV negative pulse from pin 1 to pin 2 Final Data Sheet 12 Revision 1.1, 2013-05-15 ESD102-U2-099EL Package Information 4 Package Information 4.1 TSLP-4-10 (mm) +0.1 0.31-0.2 0.05 MAX. 0.75 ±0.035 0.25 ±0.035 1) 2 0.4 3 4 1 0.75 ±0.035 Bottom view 0.25 ±0.035 1) Top view 0.4 Pin 1 marking 1) Dimension applies to plated terminals Figure 12 TSLP-4-10-PO V01 TSLP-4-10: Package outline (dimension in mm) 0.4 0.4 0.25 TSLP-4-10-FP V01 Figure 13 TSLP-4-10: Footprint (dimension in mm) 0.92 Pin 1 marking 8 0.4 2 0.92 TSLP-4-10-TP V01 Figure 14 TSLP-4-10: Packing dimension in mm) Pin 1 marking 1 Type code TSLP-4-10-MK V01 Figure 15 TSLP-4-10: Marking (example) Final Data Sheet 13 Revision 1.1, 2013-05-15 ESD102-U2-099EL References References [1] On-chip ESD protection for integrated circuits, Albert Z. H. Wang, ISBN:0-7923-7647-1 [2] Infineon Technologie AG - Application Note AN210: Effective ESD Protection Design at System Level Using VF-TLP Characterization Methodology [3] Infineon Technologie AG - Application Note AN240: Effective ESD Protection for USB3.0, combined with perfect Signal Intergrity. Final Data Sheet 14 Revision 1.1, 2013-05-15 w w w . i n f i n e o n . c o m Published by Infineon Technologies AG