For Audio Equipment MN662724RPE Signal Processing LSI for CD Players Overview The MN662724RPE is a CD signal processing LSI that, on a single chip, combines an optics servo for the CD player (focus, tracking, and traverse servos), digital signal processing (EFM demodulation and error correction), and digital servo processing for the spindle motor. Features (Optics servo) Focus, tracking, and traverse servos Automatic adjustment functions for FO/TR gain, FO/TR offset, and FO/TR balance Built-in D/A converter for drive voltage output Built-in dropout countermeasures Anti-shock functions Built-in track cross counter (Digital signal processing) Built-in DSL and PLL Frame synchronization detection, holding, and insertion Subcode data processing Q data CRC check Built-in Q data register CIRC error detection and correction C1 decoder: duplex error correction C2 decoder: triplex error correction Built-in 16-K bits of RAM for de-interleaving Audio data interpolation Average, hold of previous values Soft muting Digital attenuation (256 levels) Software attenuation (256 levels) Auto cue detection function Digital audio interface (EIAJ format) Two audio data serial interfaces: One switchable between bit rates of 64 fs and 48 fs; the other fixed at 48 f s. (Spindle motor servo) CLV digital servo Switchable servo gain (Other) Built-in playback pitch control function (normal speed only)(±13%) Built-in support for jitter-free disc rotation synchronization playback Oscillator shutdown mode Power management mode Operating voltage 4.5 to 5.5V Applications CD Players MN662724RPE For Audio Equipment 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VDD X2 X1 VSS SBCK SUBC TOFS PCK/DSLB EFM/CK384 AVSS2 AVDD2 VCOF PLLF DSLF DRF IREF ARF WVEL PLAY PLLF2 Pin Assignment 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 BCLK LRCK SRDATA DVDD1 DVSS1 TX MCLK MDATA MLD SENSE FLOCK TLOCK BLKCK SQCK SUBQ DMUTE STAT RST SMCK PMCK BYTCK/TRVSTOP CLDCK FCLK IPFLAG FLAG CLVS CRC DEMPH FLAG6/RESY SDAT48 TEST AVDD1 LRCK48 AVSS1 BCLK48 RSEL CSEL PSEL MSEL SSEL (TOP VIEW) QFS080-P-1414 LDON BDO RFDET TRCRS OFT VDET RFENV TE FE TBAL FBAL VREF FOD TRD KICK ECS ECM PC TVD TRV For Audio Equipment MN662724RPE Block Diagram 66 67 13 62 56 55 PSEL CLV SERVO 23 D/A CONVERTER OUTPUT PORT SERVO CPU MICROCOMPUTER INTERFACE TIMING GENERATOR VCO PITCH CONTROL 19 63 20 77 79 59 58 ECM PC LRCK LRCK48 SRDATA SDAT48 BCLK BCLK48 DMUTE 61 25 22 27 28 31 30 12 11 42 40 54 BYTCK/TRVSTOP ECS TVD TRD FOD TBAL FBAL TLOCK FLOCK PLAY LDON TOFS 43 WVEL 10 SENSE 17 36 OFT 38 SERVO TIMING GENERATOR RFDET BDO 39 35 VDET 37 INPUT PORT TRCRS 32 FE 33 TE 34 RFENV A/D CONVERTER 60 57 4 5 18 71 STAT 49 VDD VSS DVDD1 DVSS1 RST TEST SMCK FCLK PMCK CSEL MSEL X2 X1 2 73 3 70 1 75 16 TX 21 TRV 26 KICK 29 VREF 78 9 MLD 7 MCLK 8 MDATA VCOF 6 24 INTERPOLATION SOFT MUTING DIGITAL ATTENUATION PEAK DETECT AUTO CUE CIRC ERROR CORRECTION DEINTERLEAVE EFM DEMODULATION SYNC INTERPOLATION SUBCODE DEMODULATION SUBCODE BUFFER 16K SRAM DIGITAL AUDIO INTERFACE 65 FLAG 64 IPFLAG VCO 68 DEMPH 69 FLAG6/RESY 80 SSEL 14 SQCK 15 SUBQ 51 AVSS2 50 AVDD2 53 PCK/DSLB 52 EFM/CK384 48 PLLF 41 PLLF2 47 DSLF 45 IREF 46 DRF 44 ARF 76 RSEL 74 AVSS1 72 AVDD1 DSL•PLL CLVS CRC BLKCK CLDCK SBCK SUBC MN662724RPE For Audio Equipment Pin Descriptions Pin No. 1 Symbol BCLK I/O O Function Description SRDATA bit clock output. 2 LRCK O Left/right channel discrimination signal output. 3 SRDATA O Serial data output. 4 DV DD1 I Power supply for digital circuits. 5 DVSS1 I Ground for digital circuits. 6 TX O Digital audio interface output signal. 7 MCLK I Microcomputer command clock input. (Data is latched at rising edge.) 8 MDATA I Microcomputer command data input. 9 MLD I Microcomputer command load signal input. 10 SENSE O Sense signal output. (OFT, FESL, NACEND, NAJEND, SFG, and NWTEND) 11 FLOCK O Focus servo pull-in signal. "L" level: pull-in state. 12 TLOCK O Tracking servo pull-in signal. "L" level: pull-in state. 13 BLKCK O Subcode block clock signal (fBLKCK=75Hz) 14 SQCK I External clock input for subcode Q register 15 SUBQ O Subcode Q data output 16 DMUTE I Muting input. (Effective only for an output bit rate of 64 fs) "H" level: muting. 17 STAT O Status signal. "L" level: load. (CRC, CUE, CLVS, TTSTOP, FCLV, SQOK, FLAG6, SENSE, FLOCK, and TLOCK) 18 RST I 19 SMCK O 20 PMCK O Reset input. "L" level: reset. If MSEL is "H" level, 8.4672 MHz clock signal is outputted. If MSEL is "L" level, 4.2336 MHz clock signal is outputted. 88.2kHz clock signal output. 21 TRV O Traverse forced feed output. 22 TVD O Traverse drive output. (tristate) 23 PC O Spindle motor ON signal. 24 ECM O Spindle motor drive signal (forced mode output). (tristate) 25 ECS O Spindle motor drive signal (servo error signal output) 26 KICK O Kick pulse output. 27 TRD O Tracking drive output. 28 FOD O Focus drive output. 29 VREF I Reference voltage for D/A output (TVD, ECS, TRD, FOD, FBAL, TBAL, "L" level: ON (default). (tristate) and TOFS). 30 FBAL O Focus balance adjustment output. 31 TBAL O Tracking balance adjustment output. 32 FE I Focus error signal input. (analog input) 33 TE I Tracking error signal input. (analog input) 34 RFENV I RF envelope signal input. (analog input) 35 VDET I Vibration detection signal input. "H" level: vibration detected. 36 OFT I Offtrack signal input. "H" level: offtrack. 37 TRCRS I Track cross signal input. (analog input) For Audio Equipment MN662724RPE Pins Descriptions (continued) Pin No. 38 Symbol RFDET I/O I 39 BDO I 40 41 LDON PLLF2 O I/O Function Description RF detection signal input. "L" level: detected. Dropout signal input. "H" level: dropout Laser ON signal output. "H" level: ON. PLL loop-filter characteristic switching pin. 42 PLAY O Play signal output. "H" level: play. 43 WVEL O Double-speed status signal output. "H" level: double-speed. 44 ARF I RF signal input. 45 IREF I Reference current input pin DSL bias pin. 46 DRF I 47 DSLF I/O DSL loop-filter pin. 48 PLLF I/O PLL loop-filter pin. 49 VCOF I/O VCO loop-filter pin. 50 AV DD2 I Power supply for analog circuits (DSL, PLL, D/A converter output, and A/D converter). 51 AV SS2 I Ground for analog circuits (DSL, PLL, D/A converter output, and A/D converter). 52 EFM O EFM signal output. or CK384 • EFM output. • Crystal oscillator 16.9344 MHz output. • 384 fs output from signal processing block. (During variable-pitch operation, this is the VCO clock.) Commands permit switching among the above three outputs. 53 PCK O Clock for PLL or DSL balance output. f PCK=4.3218MHz or DSLB 54 TOFS O Tracking offset adjustment output. 55 SUBC O Subcode serial output. 56 SBCK I Clock input for subcode serial output. 57 VSS I Ground for oscillator circuit. 58 X1 I Crystal oscillator circuit input pin. f=16.9344MHz, 33.8688MHz 59 X2 O Crystal oscillator circuit output pin. f=16.9344MHz, 33.8688MHz 60 VDD I Oscillator circuit power supply. BYTCK or O 61 TRVSTOP During default operation, byte clock signal output. During command execution, traverse stop signal output. "H" level: stop mode. 62 CLDCK O Subcode frame clock signal output pin. (f CLDCK=7.35kHz) 63 FCLK O Crystal frame clock signal output. (f FCLK=7.35kHz) 64 IPFLAG O Interpolation flag signal output. 65 FLAG O Flag signal output. 66 CLVS O Spindle servo phase synchronization signal output. "H" level: CLV. "H" level: interpolation. "L" level: rough servo. 67 CRC O Subcode CRC check result output. "H" level: OK. "L" level: no good. 68 DEMPH O De-emphasis detection signal output. "H" level: on. MN662724RPE For Audio Equipment Pin Descriptions (continued) Pin No. 69 Symbol FLAG6 I/O O or RESY Function description During default operation, FLAG6 output, that is the resetting signal for the address of RAM used to de-interleave error correction data. "L" level: address reset. During command execution, RESY output, that is the frame resynchronization signal. "H" level: synchronized. 70 SDAT48 O "L" level: out of sync. Serial data output for bit rate 48 fs. 71 TEST I Test pin. 72 AV DD1 I Power supply for digital circuits. Keep this at "H" level. 73 LRCK48 O Left/right channel discrimination signal output for bit rate 48 fs. 74 AVSS1 I Ground for digital circuits. 75 BCLK48 O Bit clock output for bit rate 48 f s. 76 RSEL I RF signal polarity selection pin. 77 CSEL I Crystal oscillator frequency specification pin. 78 PSEL I Test pin. 79 MSEL I SMCK pin output. "H" level: bright level is "H." "L" level: bright level is "L." "H" level: 33.8688 MHz. "L" level: 16.9344 MHz Keep this at "L" level. SMCK frequency selection pin. "H" level: 8.4672 MHz. "L" level: 4.2336 MHz. 80 SSEL I SUBQ pin output mode selection pin. "H" level: Buffered Q code mode. "L" level: CLDCK synchronization mode. For Audio Equipment MN662724RPE Package Dimensions (Unit: mm) QFS080-P-1414 16.2±0.2 14.0±0.2 60 41 40 80 16.2±0.2 14.0±0.2 0.825 61 21 0.15 SEATING PLANE 0 to 10° 1.1±0.1 0.15 +0.10 -0.05 +0.10 0.3 -0.05 2.1±0.3 0.65 2.0±0.2 20 0.1±0.1 1 0.55±0.1