IP4369CX4 ESD protection for high-speed interfaces Rev. 1 — 1 October 2012 Product data sheet 1. Product profile 1.1 General description The device is designed to protect high-speed interfaces such as High-Definition Multimedia Interface (HDMI), DisplayPort, USB, external Serial Advanced Technology Attachment (eSATA) and Low Voltage Differential Signaling (LVDS) interfaces against ElectroStatic Discharge (ESD). The device includes high-level ESD protection diodes structure for high-speed signal lines in a 4-channel 0.4 mm pitch single Wafer-Level Chip-Scale Package (WLCSP). These features make the device ideal for use in applications requiring component miniaturization such as mobile phone handsets and other portable electronic devices. All signal lines are protected by a special diode configuration offering ultra low line capacitance of 0.8 pF (typical). These diodes provide protection to downstream components from ESD voltages up to 8 kV contact according to IEC 61000-4-2, level 4. 1.2 Features and benefits Pb-free, Restriction of Hazardous Substances (RoHS) compliant and free of halogen and antimony (Dark Green compliant) System ESD protection for USB 2.0, USB On-The-Go (USB OTG), Ethernet and Digital Visual Interface (DVI) All signal lines with integrated rail-to-rail clamping diodes structure for downstream ESD protection of 8 kV according to IEC 61000-4-2, level 4 2 2 solder ball WLCSP with 0.4 mm pitch and height < 500 m Signal lines with 0.05 pF matching capacitance between signal pairs Line capacitance of only 0.8 pF for each channel 1.3 Applications The device is designed for high-speed receiver and transmitter port protection: Portable devices Mobile handsets Wireless data systems Digital cameras IP4369CX4 NXP Semiconductors ESD protection for high-speed interfaces 2. Pinning information Table 1. Pin Pinning Description Simplified outline Graphic symbol A1 and A2 ESD protection bump A1 index area B1 and B2 ground 1 2 A2 A1 A B1 B2 018aaa224 B 008aaa236 transparent top view, solder balls facing down 3. Ordering information Table 2. Ordering information Type number Package Name IP4369CX4 Description Version WLCSP4 wafer level chip-size package; 4 bumps (2 2) IP4369CX4 4. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VI input voltage VESD electrostatic discharge voltage Tstg storage temperature Treflow(peak) peak reflow temperature Tamb ambient temperature [1] IP4369CX4 Product data sheet Conditions IEC 61000-4-2, level 4; contact discharge tp 10 s [1] Min Max Unit 0.5 +5.5 V - 8 kV 55 +150 C - +260 C 30 +85 C Pins A1 and A2 to ground (B1 and B2). All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 October 2012 © NXP B.V. 2012. All rights reserved. 2 of 14 IP4369CX4 NXP Semiconductors ESD protection for high-speed interfaces 5. Characteristics Table 4. Characteristics Tamb = 25 C unless otherwise specified. Symbol Parameter Cline Conditions line capacitance C(I/O-I/O) input/output to input/output capacitance Min Typ Max Unit per pin; pins A1 and A2 to GDN; Vbias = 0 V; f = 1 MHz [1] - 0.8 1 pF GND not connected; Vbias = 0 V; f = 1 MHz [1] - 0.4 - pF - - 100 nA IRM reverse leakage current Vbias = 3 V VBR breakdown voltage Itest = 1 mA VF forward voltage Rdyn dynamic resistance negative transient positive transient negative transient V V - 0.24 - - 0.21 - - 0.21 - - 0.16 - ICL = 4 A [3] - 4 - V ICL = 5 A [3] - 3 - V [1] This parameter is guaranteed by design. [2] 100 ns Transmission Line Pulse (TLP); 50 ; pulser at 80 ns. [3] According to IEC 61000-4-5 (8/20 s). 018aaa225 5 10 - [3] surge clamping voltage 0.7 [2] TLP positive transient VCL 6 - 018aaa226 10 S21 (dB) S21 (dB) -10 0 -30 -50 -5 -70 -10 10-1 Fig 1. 1 10 102 Mixed-mode differential insertion loss; typical values IP4369CX4 Product data sheet -90 10-1 103 104 f (MHz) Fig 2. 1 10 102 103 104 f (MHz) Mixed-mode differential crosstalk, typical values All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 October 2012 © NXP B.V. 2012. All rights reserved. 3 of 14 IP4369CX4 NXP Semiconductors ESD protection for high-speed interfaces 018aaa227 1.2 a 018aaa228 1.2 a 1.1 1.1 1.0 1.0 0.9 0.9 0.8 0 2 4 0.8 10-2 6 10-1 1 VI (V) C line a = --------------------------------------C line V = 0V C line a = -------------------------------------C line f = 10MHz bias Fig 3. 10 f (GHz) Relative capacitance as a function of input voltage; typical values Fig 4. 018aaa229 3.5 Relative capacitance as a function of frequency; typical values 018aaa230 2.5 VO (mV) VI (V) 2.0 2.5 1.5 1.5 1.0 0.5 0.5 -0.5 -10 0 10 0.0 -10 20 t (ns) Fig 5. 0 10 20 t (ns) Input voltage for crosstalk measurements; channel 1; typical values Fig 6. Output voltage for crosstalk measurements; channel 2; typical values Figure 5 and 6 show time-domain crosstalk from channel 1 to channel 2. Generator impedance on channel 1 is 50 , probe impedance on channel 2 is 1 M. IP4369CX4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 October 2012 © NXP B.V. 2012. All rights reserved. 4 of 14 IP4369CX4 NXP Semiconductors ESD protection for high-speed interfaces 018aaa231 Data rate: 480 Mbit/s (USB 2.0 High-speed) Vertical scale = 200 mV/div Horizontal scale = 260 ps/div Fig 7. USB 2.0 eye diagram with IP4369CX4 018aaa232 Data rate: 480 Mbit/s (USB 2.0 High-speed) Vertical scale = 200 mV/div Horizontal scale = 260 ps/div Fig 8. IP4369CX4 Product data sheet USB 2.0 eye diagram without IP4369CX4 All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 October 2012 © NXP B.V. 2012. All rights reserved. 5 of 14 IP4369CX4 NXP Semiconductors ESD protection for high-speed interfaces 018aaa233 14 ICL (A) 12 018aaa234 0 ICL (A) -2 10 -4 8 -6 6 -8 4 -10 2 -12 -14 0 0 2 4 6 8 10 -6 -4 -2 VCL (V) tp = 100 ns; Transmission Line Pulse (TLP) Fig 9. 0 VCL (V) tp = 100 ns; Transmission Line Pulse (TLP) Dynamic resistance with positive clamping Fig 10. Dynamic resistance with negative clamping The device uses an advanced clamping structure showing a negative dynamic resistance. This snap-back behavior strongly reduces the clamping voltage to the system behind the ESD protection during an ESD event. Do not connect unlimited DC current sources to the data lines to avoid keeping the ESD protection device in snap-back state after exceeding breakdown voltage (due to an ESD pulse for instance). 018aaa235 4 VCL (V) (1) 018aaa236 3 VCL (V) 3 (2) 2 (3) (1) 2 (2) (3) 1 1 0 0.0 0 1.5 3.0 4.5 0 2 4 ICL (A) IEC 61000-4-5 IEC 61000-4-5 (1) Tamb = 25 C; y = 0.21x + 2.86 (1) Tamb = 25 C; y = 0.16x + 1.52 (2) Tamb = 75 C (2) Tamb = 75 C (3) Tamb = 125 C (3) Tamb = 125 C Fig 11. Surge pulse response test; positive transient, typical values IP4369CX4 Product data sheet 6 ICL (A) Fig 12. Surge pulse response test; negative transient, typical values All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 October 2012 © NXP B.V. 2012. All rights reserved. 6 of 14 IP4369CX4 NXP Semiconductors ESD protection for high-speed interfaces 018aaa237 40 VCL (V) 20 (1) 0 (2) -20 -40 -50 0 50 100 150 200 250 t (ns) 300 (1) +8 kV (2) 8 kV Fig 13. ESD pulse transient response; IEC 61000-4-2; contact discharge; typical values 018aaa238 10-3 IRM (mA) 018aaa239 10 IPP (A) 10-4 8 10-5 6 10-6 4 10-7 2 10-8 0 0 50 100 150 1 Tamb (°C) 10 102 103 tp (µs) Vbias = 3 V Fig 14. Reverse leakage current as a function of ambient temperature; typical values IP4369CX4 Product data sheet Fig 15. Peak pulse current as a function of pulse duration; rectangular pulses; typical values All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 October 2012 © NXP B.V. 2012. All rights reserved. 7 of 14 IP4369CX4 NXP Semiconductors ESD protection for high-speed interfaces 6. Package outline WLCSP4: wafer level chip-size package; 4 bumps (2 x 2) D bump A1 index area A2 E A A1 detail X e b B e A 1 2 X European projection wlcsp4_2x2_po Fig 16. Package outline IP4369CX4 (WLCSP4) Table 5. Package outline dimensions of IP4369CX4 (WLCSP4) Symbol Min Typ Max Unit A 0.44 0.47 0.50 mm A1 0.18 0.20 0.22 mm A2 0.26 0.27 0.28 mm b 0.21 0.26 0.31 mm D 0.71 0.76 0.81 mm E 0.71 0.76 0.81 mm e 0.35 0.40 0.45 mm IP4369CX4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 October 2012 © NXP B.V. 2012. All rights reserved. 8 of 14 IP4369CX4 NXP Semiconductors ESD protection for high-speed interfaces 7. Design and assembly recommendations 7.1 PCB design guidelines For optimum performance, use a Non-Solder Mask Defined (NSMD), also known as a copper-defined design, incorporating laser-drilled micro-vias connecting the ground pads to a buried ground-plane layer. This results in the lowest possible ground inductance and provides the best high frequency and ESD performance. Refer to Table 6 for the recommended Printed-Circuit Board (PCB) design parameters. Table 6. Recommended PCB design parameters Parameter Value or specification PCB pad diameter 250 m Micro-via diameter 100 m (0.004 inch) Solder mask aperture diameter 325 m Copper thickness 20 m to 40 m Copper finish AuNi PCB material FR4 7.2 PCB assembly guidelines for Pb-free soldering Table 7. Assembly recommendations Parameter Value or specification Solder screen aperture diameter 290 m Solder screen thickness 100 m (0.004 inch) Solder paste: Pb-free SnAg (3 % to 4 %) Cu (0.5 % to 0.9 %) Solder to flux ratio 50 : 50 Solder reflow profile see Figure 17 T (°C) Treflow(peak) 250 230 cooling rate 217 preheat t1 t2 t3 t4 t (s) t5 001aai943 The device is capable of withstanding at least three reflows of this profile. Fig 17. Pb-free solder reflow profile IP4369CX4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 October 2012 © NXP B.V. 2012. All rights reserved. 9 of 14 IP4369CX4 NXP Semiconductors ESD protection for high-speed interfaces Table 8. Symbol Characteristics Parameter Conditions Treflow(peak) peak reflow temperature Product data sheet Typ Max Unit 230 - 260 C t1 time 1 soak time 60 - 180 s t2 time 2 time during T 250 C - - 30 s t3 time 3 time during T 230 C 10 - 50 s t4 time 4 time during T > 217 C 30 - 150 s t5 time 5 - - 540 s dT/dt rate of change of temperature cooling rate - - 6 C/s 2.5 - 4.0 C/s pre-heat IP4369CX4 Min All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 October 2012 © NXP B.V. 2012. All rights reserved. 10 of 14 IP4369CX4 NXP Semiconductors ESD protection for high-speed interfaces 8. Revision history Table 9. Revision history Document ID Release date Data sheet status Change notice Supersedes IP4369CX4 v.1 20121001 Product data sheet - - IP4369CX4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 October 2012 © NXP B.V. 2012. All rights reserved. 11 of 14 IP4369CX4 NXP Semiconductors ESD protection for high-speed interfaces 9. Legal information 9.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 9.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 9.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. IP4369CX4 Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 October 2012 © NXP B.V. 2012. All rights reserved. 12 of 14 IP4369CX4 NXP Semiconductors ESD protection for high-speed interfaces Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 9.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 10. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] IP4369CX4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 October 2012 © NXP B.V. 2012. All rights reserved. 13 of 14 IP4369CX4 NXP Semiconductors ESD protection for high-speed interfaces 11. Contents 1 1.1 1.2 1.3 2 3 4 5 6 7 7.1 7.2 8 9 9.1 9.2 9.3 9.4 10 11 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8 Design and assembly recommendations . . . . 9 PCB design guidelines . . . . . . . . . . . . . . . . . . . 9 PCB assembly guidelines for Pb-free soldering 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Contact information. . . . . . . . . . . . . . . . . . . . . 13 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 1 October 2012 Document identifier: IP4369CX4