CH www.vishay.com Vishay Sfernice High Frequency 50 GHz Thin Film Chip Resistor FEATURES • Operating frequency 50 GHz • Thin film microwave resistors • SMD wraparound or flip chip resistor • Small size, down to 20 mils by 16 mils • Edged trimmed block resistors • Pure alumina substrate (99.5 %) • Ohmic range: 10R to 500R • Design kits available • Small internal reactance (LC down to 1 × 10-24) • Tolerance 1 %, 2 %, 5 %, 10 % • TCR: 100 ppm/°C in (-55 °C, +155 °C) temperature range • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 Those miniaturized components are designed in such a way that their internal reactance is very small. When correctly mounted and utilized, they function as almost pure resistors on a very large range of frequency, up to 50 GHz. STANDARD ELECTRICAL SPECIFICATIONS RESISTANCE RANGE LIMITING ELEMENT VOLTAGE V RATED POWER Pn W TOLERANCE ±% TEMPERATURE COEFFICIENT ± ppm/°C MODEL SIZE CH02016 02016 10 to 500 0.030 30 2, 5, 10 100 CH0402 0402 10 to 500 0.050 37 1, 2, 5, 10 100 CH0603 0603 10 to 500 0.125 50 1. 2, 5, 10 100 DIMENSIONS in millimeters (inches) A (1) A D D D A D C C (F) D D E (P) B C (N) and (G) E DIMENSIONS CASE SIZE MAX. TOL. + 0.1 (+ 0.004) MIN. TOL. - 0.1 (- 0.004) A (1) B C MAX. TOL. + 0.1 (+ 0.004) MIN. TOL. - 0.1 (- 0.004) MAX. TOL. + 0.1 (+ 0.004) MIN. TOL. - 0.1 (- 0.004) MAX. TOL. + 0.127 (+ 0.005) MIN. TOL. - 0.127 (- 0.005) MIN. MAX. D/E 02016 0.48 (0.020) 0.39 (0.016) 0.42 (0.02) (2) 0.11 (0.004) 0.15 (0.008) 0402 1.00 (0.040) 0.6 (0.023) 0.5 (0.02) 0.15 (0.006) 0.35 (0.014) 0603 1.52 (0.060) 0.75 (0.030) 0.5 (0.02) 0.25 (0.010) 0.51 (0.020) Notes (1) For CH0402 and CH0603 with P termination, A dimension is increased by 0.2 mm (2) + or - 0.07 mm Revision: 04-Apr-16 Document Number: 53014 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 CH www.vishay.com Vishay Sfernice LAND PATTERN FLIP CHIP TERMINATIONS in millimeters Gmin. Xmax. Zmax. CHIP SIZE Zmax. Xmax. Gmin. 02016 0.53 0.44 0.15 0402 1.4 0.650 0.4 0603 1.71 0.9 0.760 Note • Suggested land pattern: According to IPC-7351 Dimension and tolerance of land pattern shall be defined by PCB designer; PCB can be designed according to IPC-7351A “Generic Requirements for Surface Mount Design and Land Pattern Standard” Example of land pattern: Fabrication allowance, assembly location and min. or max. level density board are not included in the exemple bellow. According to IPC-7351A “Generic Requirements for Surface Mount Design and Land Pattern Standard”: 2 2 2 2 2 2 2 2 2 Zmax. = Amin. + 2JT + C A + F + P with C: “Unilateral profile tolerance for the component”; Gmin. = Fmax. + 2JH - C F + F + P F: ”Unilateral profile tolerance for the board land pattern”; Xmax. = Bmin. + 2JS + C B + F + P and P: “Diameter of true position placement accuracy to the center of land pattern”. JH For rectangular component suggest: JS COMPONENT Flip-Chip mounting, we JT (TOE) 0 mm JH (HELL) 0 mm JS (SDE) 0 mm JT Land Pattern Footprint WRAPAROUND TERMINATIONS in millimeters X m ax . Gmin. Zmax. CHIP SIZE Zmax. Gmin. Xmax. 0402 1.55 0.15 0.73 0603 2.37 0.35 0.98 10 R < 50 50 R < 100 100 R 500 5 %, 10 % 2 %, 5 %, 10 % 1 %, 2 %, 5 %, 10 % (1) TOLERANCE VS. OHMIC VALUES Ohmic range Tolerance Note (1) 1 % tolerance not applicable for case 02016. Revision: 04-Apr-16 Document Number: 53014 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 CH www.vishay.com Vishay Sfernice PREFERRED MODELS AND VALUES Vishay Sfernice highly recommend to use the smallest sizes and flip chip version to get the best performances. Recommended Values: 10R/18R/25R/50R/75R/100R/150R/180R/200R/250R/330R/500R Those values are available with a MOQ of 100 pieces. Other values can be ordered upon request, but higher MOQ will apply: 1000 pieces for CH02016, 500 pieces for CH0402, 50 pieces for CH0603. Recommended terminations: F Recommended tolerance: 2% Design kits are available Ex Stock in CH02016 and CH0402 sizes. There are 20 pieces per recommended value. F termination. 5 % tolerance. Those kits are packaged in pieces of tape and delivered in ESD bags. PACKAGING Standard packaging is waffle pack for sizes 0402 and 0603 and plastic tape and reel (low conductivity) for size 02016. Paper tape and reel is available for size 0402 and either paper tape and reel or plastic tape and reel (low conductivity) for size 0603. Depending on the type of terminations, parts will be packed differently: One face: • Gold terminations: Active face up • Tin/silver termination: Active face down Note • Please refer to Vishay Sfernice Application Note “Guidelines for Vishay Sfernice Resistive and Inductive Products” for soldering recommendation (document number 52029, 3. Guidelines for Surface Mounting Components (SMD), profile number 3 applies NUMBER OF PIECES PER PACKAGE SIZE 02016 0402 0603 MOQ See MOQ mentioned on preferred models and values WAFFLE PACK 2" X 2" TAPE AND REEL TAPE WIDTH Min. Max. 100 5000 484 100 8 mm 100 PACKAGING RULES Waffle Pack Tape and Reel Can be filled up to maximum quantity indicated in the table here above, taking into account the minimum order quantity. When quantity ordered exceeds maximum quantity of a single waffle pack, the waffle packs are stacked up on the top of each other and closed by one single cover. To get “not stacked up” waffle pack in case of ordered quantity > maximum number of pieces per package: Please consult Vishay Sfernice for specific ordering code. See Part Numbering information to get the quantity desired by tape. Revision: 04-Apr-16 Document Number: 53014 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 CH www.vishay.com Vishay Sfernice GLOBAL PART NUMBER INFORMATION New Global Part Numbering: CH0402-50RJF (preferred part number format) C H 0 4 0 2 - 5 0 R J F T 9 9 9 GLOBAL MODEL SIZE OHMIC VALUE TOLERANCE TERMINATION PACKAGING OPTION CH 02016 0402 0603 10R to 500R F=1% G=2% J=5% K = 10 % F (Flip Chip): SnAg over nickel barrier N (W/A): SnAg over nickel barrier (except 02016) P (one face): (1) Gold bonding pads G (W/A): Gold (except 02016) For more information see Codification of Packaging table From 1 to 3 digits. Leave blank if no option. Historical Part Number example: CH02016-100RGFPT1K (tapes of 1K pieces) CH0402-50RJF (waffle pack) Notes • Historical part numbers are not recommended but can still be used for ordering. (1) Gold termination for application in hermetic package. CODIFICATION OF PACKAGING WAFFLE PACK (standard packaging for CH0402 and CH0603) W 100 min., 1 mult PLASTIC TAPE (standard packaging for CH02016 and CH0603) T 100 min., 1 mult TA 100 min., 100 mult TB 250 min., 250 mult TC 500 min., 500 mult TD 1000 min., 1000 mult TE 2500 min., 2500 mult TF Full tape (qunatity depending on size of chips) PAPER TAPE (standard packaging for CH0402 - available for CH0603) PT 100 min., 1 mult PA 100 min., 100 mult PB 250 min., 250 mult PC 500 min., 500 mult PD 1000 min., 1000 mult PE 2500 min., 2500 mult PF Full tape (quantity depending on size of chips) TYPICAL HIGH FREQUENCY PERFORMANCE ELECTRICAL MODEL Z C Z0 Z0 Lc Lc L C L R Z Lc Cg Cg R Internal shunt capacitance Internal inductance Resistance Internal impedance (R, L, C) External connection inductance External capacitance to ground Revision: 04-Apr-16 Document Number: 53014 4 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 CH www.vishay.com Vishay Sfernice The complex impedance of the chip resistor is given by the following equations: 2 2 2 R + j L – R C – L C Z = ------------------------------------------------------------------------------------2 2 2 4 1 + C R C – 2L + L C Z 1 -------- = ------------------------------------------------------------------------------------------ x 2 2 2 4 R 1 + C R C – 2L + L C 2 2 2 L – R C – L C 1 + -----------------------------------------------------------R 2 2 2 2 – 1 L – R C – L C = tan -----------------------------------------------------------R Notes • =2xxf • f: Frequency L The chip resistor itself is purely resistive when R = ---- . The smaller the L x C product the greater the frequency range over C which the resistor looks approximately resistive. Z This can be seen on the graphs showing the ratio -------- versus frequency. R R, L and C are relevant to the chip resistor itself. Lc and Cg also depends on the way the chip resistor is mounted. It is important to notice that after assembly the external reactance of Lc and Cg will be combined to internal reactance of L and C. This combination can upgrade or downgrade the HF behavior of the component. This is why we are displaying two sets of data: Z • -------- versus frequency curves which aims to show at a glance the intrinsic HF performance of a given chip resistor R • S-parameters versus frequency curves relevant to chip resistor when assembled on ideal Z0 impedance transmission line These lines are terminated with adapted source and load impedance respectively Zs and Zl with Z0 = ZL = Zs (for others configurations please consult us). Equivalent circuit for S-parameters: Z total C ZS G Z0 Z0 Cg Lc Lc L Cg ZL R S-parameters are computed taking into account all the resistive, inductive and capacitive elements (Z total) and Z0 = ZL = Zs = R. Revision: 04-Apr-16 Document Number: 53014 5 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 CH www.vishay.com Vishay Sfernice INTERNAL IMPEDANCE CURVES 1.1 10 Ω 25 Ω 50 Ω 75 Ω 1.0 0.9 100 Ω 0.8 150 Ω IZI/R 0.7 200 Ω 0.6 250 Ω 0.5 0.4 500 Ω 0.3 0.2 0.1 0.1 1 10 100 f (GHz) Internal impedance curve for 02016 size (F and P terminations) 1.1 10 Ω 25 Ω 1.0 50 Ω 0.9 75 Ω 0.8 100 Ω IZI/R 0.7 150 Ω 0.6 200 Ω 0.5 250 Ω 0.4 0.3 500 Ω 0.2 0.1 0.1 1 10 100 f (GHz) Internal impedance curve for 0402 size (F and P terminations) Revision: 04-Apr-16 Document Number: 53014 6 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 CH www.vishay.com Vishay Sfernice INTERNAL IMPEDANCE CURVES 1.1 10 Ω 25 Ω 50 Ω 75 Ω 1.0 0.9 0.8 100 Ω IZI/R 0.7 0.6 0.5 150 Ω 0.4 200 Ω 0.3 250 Ω 0.2 500 Ω 0.1 0.1 1 10 100 f (GHz) Internal impedance curve for 0402 size (N and G terminations) 1.1 10 Ω 25 Ω 1.0 50 Ω 0.9 0.8 75 Ω IZI/R 0.7 100 Ω 0.6 0.5 150 Ω 0.4 200 Ω 250 Ω 0.3 0.2 500 Ω 0.1 0.1 1 10 100 f (GHz) Internal impedance curve for 0603 size (F and P terminations) Revision: 04-Apr-16 Document Number: 53014 7 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 CH www.vishay.com Vishay Sfernice INTERNAL IMPEDANCE CURVES 1.1 10 Ω 25 Ω 50 Ω 1.0 75 Ω 0.9 0.8 IZI/R 0.7 100 Ω 0.6 0.5 150 Ω 0.4 200 Ω 0.3 250 Ω 0.2 500 Ω 0.1 0.1 1 10 100 f (GHz) Internal impedance curve for 0603 size (N and G terminations) S-PARAMETER CH02016 (F and P Terminations) -2 -2 -3 -3 S21 S21 -4 Magnitude (dB) Magnitude (dB) -4 -5 -6 -7 -8 -5 -6 -7 S11 -8 -9 -9 S11 - 10 0.1 1 10 100 - 10 0.1 1 10 f (GHz) f (GHz) CH02016 flip chip (Z0 = ZI = Zs = R = 50 Ω) CH02016 flip chip (Z0 = ZI = Zs = R = 100 Ω) Revision: 04-Apr-16 100 Document Number: 53014 8 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 CH www.vishay.com Vishay Sfernice S-PARAMETER CH0402 (F and P Terminations) -2 -2 -3 -3 S21 -4 S21 -5 -6 -7 S11 Magnitude (dB) Magnitude (dB) -4 -5 -6 -7 -8 -8 -9 -9 - 10 0.1 1 10 100 - 10 0.1 S11 1 10 f (GHz) f (GHz) CH0402 flip chip (Z0 = ZI = Zs = R = 50 Ω) CH0402 flip chip (Z0 = ZI = Zs = R = 100 Ω) 100 CH0402 (N and G Terminations) -2 -2 -3 -3 -4 -4 S21 Magnitude (dB) Magnitude (dB) S21 -5 -6 S11 -7 -5 -6 -7 S11 -8 -8 -9 -9 - 10 0.1 1 10 100 - 10 0.1 1 10 f (GHz) f (GHz) CH0402 wraparound (Z0 = ZI = Zs = R = 50 Ω) CH0402 wraparound (Z0 = ZI = Zs = R = 100 Ω) 100 CH0603 (F and P Terminations) -2 -2 -3 -3 -4 -4 -5 S21 -6 -7 Magnitude (dB) Magnitude (dB) S11 S21 -5 -6 -7 -8 -8 -9 -9 - 10 0.1 1 10 100 - 10 0.1 S11 1 10 f (GHz) f (GHz) CH0603 flip chip (Z0 = ZI = Zs = R = 50 Ω) CH0603 flip chip (Z0 = ZI = Zs = R = 100 Ω) Revision: 04-Apr-16 100 Document Number: 53014 9 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 CH www.vishay.com Vishay Sfernice S-PARAMETER CH0603 (N and G Terminations) -2 -2 -3 -3 -4 -4 Magnitude (dB) Magnitude (dB) S11 -5 -6 -7 -8 -5 S21 -6 S11 -7 -8 S21 -9 - 10 0.1 1 10 100 -9 - 10 0.1 1 10 f (GHz) f (GHz) CH0603 wraparound (Z0 = ZI = Zs = R = 50 Ω) CH0603 wraparound (Z0 = ZI = Zs = R = 100 Ω) Revision: 04-Apr-16 100 Document Number: 53014 10 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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