PHN203 Dual N-channel TrenchMOS logic level FET Rev. 05 — 27 April 2010 Product data sheet 1. Product profile 1.1 General description Dual logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only. 1.2 Features and benefits Suitable for high frequency applications due to fast switching characteristics Suitable for logic level gate drive sources 1.3 Applications DC-to-DC converters Lithium-ion battery applications 1.4 Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 150 °C - - 30 V ID drain current Tamb = 25 °C; pulsed; see Figure 1; see Figure 3 [1] - - 6.3 A Ptot total power dissipation Tamb = 25 °C; pulsed; see Figure 2 [1] - - 2 W - 24 30 mΩ - 3 - nC Static characteristics RDSon drain-source on-state resistance VGS = 10 V; ID = 7 A; Tj = 25 °C; see Figure 9; see Figure 10 Dynamic characteristics QGD [1] gate-drain charge VGS = 10 V; ID = 7 A; VDS = 15 V; Tj = 25 °C; see Figure 11 Single device conducting. PHN203 NXP Semiconductors Dual N-channel TrenchMOS logic level FET 2. Pinning information Table 2. Pinning information Pin Symbol Description 1 S1 source1 2 G1 gate1 3 S2 source2 4 G2 gate2 5 D2 drain2 6 D2 drain2 7 D1 drain1 8 D1 drain1 Simplified outline Graphic symbol 8 5 1 4 D2 D2 D1 D1 SOT96-1 (SO8) S1 S2 G1 G2 mbk725 3. Ordering information Table 3. Ordering information Type number Package PHN203 Name Description Version SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 4. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 150 °C - - 30 V VDGR drain-gate voltage Tj ≤ 150 °C; Tj ≥ 25 °C; RGS = 20 kΩ - - 30 V VGS gate-source voltage drain current ID -20 - 20 V Tamb = 70 °C; pulsed; see Figure 1 [1] - - 5 A Tamb = 25 °C; pulsed; see Figure 1; see Figure 3 [1] - - 6.3 A - - 18 A IDM peak drain current tp ≤ 10 µs; pulsed; Tamb = 25 °C; see Figure 3 [1] Ptot total power dissipation Tamb = 25 °C; pulsed; see Figure 2 [1] - - 2 W Tstg storage temperature -55 - 150 °C Tj junction temperature -55 - 150 °C Source-drain diode IS source current Tamb = 25 °C; pulsed [1] - - 2 A ISM peak source current tp ≤ 10 µs; pulsed; Tamb = 25 °C [1] - - 4.1 A - - 37.8 mJ Avalanche ruggedness EDS(AL)S [1] non-repetitive drain-source avalanche energy VGS = 10 V; Tj(init) = 25 °C; ID = 8.7 A; Vsup ≤ 30 V; unclamped; tp = 0.2 ms; RGS = 50 Ω Single device conducting. PHN203 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 27 April 2010 © NXP B.V. 2010. All rights reserved. 2 of 13 PHN203 NXP Semiconductors Dual N-channel TrenchMOS logic level FET 03aa19 120 Ider (%) Pder (%) 80 80 40 40 0 0 0 Fig 1. 03aa11 120 50 100 150 200 Tamb (°C) 0 Normalized continuous drain current as a function of ambient temperature Fig 2. 50 100 Normalized total power dissipation as a function of ambient temperature 03an69 102 ID (A) 150 200 Tamb (°C) Limit RDSon = VDS / ID tp = 10 μs 10 1 ms 1 100 ms DC 1s 10−1 10 s 10−2 10−1 1 102 10 VDS (V) Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage PHN203 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 27 April 2010 © NXP B.V. 2010. All rights reserved. 3 of 13 PHN203 NXP Semiconductors Dual N-channel TrenchMOS logic level FET 5. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Conditions Rth(j-sp) thermal resistance from junction to solder point Rth(j-a) thermal resistance from junction to ambient mounted on a printed-circuit board; minimum footprint; see Figure 4 Min Typ Max Unit - - - K/W - - 62.5 K/W 03an68 103 Zth(j-a) (K/W) 102 δ = 0.5 0.2 10 0.1 0.05 0.02 1 single pulse 10−1 10−5 10−4 10−3 10−2 10−1 1 10 tp (s) Fig 4. Transient thermal impedance from junction to ambient as a function of pulse duration PHN203 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 27 April 2010 © NXP B.V. 2010. All rights reserved. 4 of 13 PHN203 NXP Semiconductors Dual N-channel TrenchMOS logic level FET 6. Characteristics Table 6. Characteristics Symbol Parameter Conditions Min Typ Max Unit Static characteristics V(BR)DSS drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = -55 °C 27 - - V ID = 250 µA; VGS = 0 V; Tj = 25 °C 30 - - V VGS(th) gate-source threshold voltage ID = 1 mA; VDS = VGS; Tj = -55 °C; see Figure 8 - - 2.2 V ID = 1 mA; VDS = VGS; Tj = 150 °C; see Figure 8 0.6 - - V ID = 1 mA; VDS = VGS; Tj = 25 °C; see Figure 8 1 1.5 2 V 1 µA IDSS drain leakage current VDS = 24 V; VGS = 0 V; Tj = 25 °C - - VDS = 24 V; VGS = 0 V; Tj = 150 °C - - 10 µA IGSS gate leakage current VGS = 20 V; VDS = 0 V; Tj = 25 °C - 10 100 nA VGS = -20 V; VDS = 0 V; Tj = 25 °C - 10 100 nA VGS = 10 V; ID = 7 A; Tj = 25 °C; see Figure 9; see Figure 10 - 24 30 mΩ VGS = 4.5 V; ID = 3.5 A; Tj = 25 °C; see Figure 9; see Figure 10 - 30 55 mΩ VGS = 10 V; ID = 7 A; Tj = 150 °C; see Figure 9; see Figure 10 - 40.8 51 mΩ ID = 7 A; VDS = 15 V; VGS = 10 V; Tj = 25 °C; see Figure 11 - 14.6 - nC - 2 - nC - 3 - nC - 560 - pF - 125 - pF RDSon drain-source on-state resistance Dynamic characteristics QG(tot) total gate charge QGS gate-source charge QGD gate-drain charge Ciss input capacitance Coss output capacitance VDS = 20 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C; see Figure 12 Crss reverse transfer capacitance VDS 20 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C; see Figure 12 - 85 - pF td(on) turn-on delay time - 5 - ns tr rise time VDS = 25 V; RL = 25 Ω; VGS = 10 V; RG(ext) = 6 Ω; Tj = 25 °C - 6 - ns td(off) turn-off delay time - 21 - ns tf fall time - 11 - ns Source-drain diode VSD source-drain voltage IS = 1.25 A; VGS = 0 V; Tj = 25 °C; see Figure 13 - 0.75 1 V trr reverse recovery time IS = 2 A; dIS/dt = -100 A/µs; VGS = 0 V; VDS = 25 V; Tj = 25 °C - 30 - ns PHN203 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 27 April 2010 © NXP B.V. 2010. All rights reserved. 5 of 13 PHN203 NXP Semiconductors Dual N-channel TrenchMOS logic level FET 03ao26 30 ID (A) VDS > I D x R DSon ID (A) 3.6 V 3.4 V 20 03ae49 30 10 V 6 V 4.5 V 4 V Tj = 25 °C 20 3.2 V 3V 10 10 2.8 V 150 °C T j = 25 °C 2.6 V VGS = 2.4 V 0 0 0 0.5 1 1.5 0 1 2 3 VGS (V) VDS (V) Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical value Fig 6. 03aa36 10-1 ID (A) Transfer characteristics: drain current as a function of gate-source voltage; typical values 03aa33 2.5 VGS(th) (V) 10-2 2 10-3 1.5 typ 10-4 1 min 10-5 0.5 min typ 0 1 2 VGS (V) Product data sheet 0 -60 3 Sub-threshold drain current as a function of gate-source voltage PHN203 max max 10-6 Fig 7. 4 Fig 8. 0 60 120 Tj (°C) 180 Gate-source threshold voltage as a function of junction temperature All information provided in this document is subject to legal disclaimers. Rev. 05 — 27 April 2010 © NXP B.V. 2010. All rights reserved. 6 of 13 PHN203 NXP Semiconductors Dual N-channel TrenchMOS logic level FET 03ao27 80 Tj = 25 °C RDSon (mΩ) VGS = 3.2 V a 3.4 V 60 03ad57 2 1.5 3.6 V 4V 40 1 4.5 V 6V 10 V 0.5 20 0 0 10 20 0 −60 30 0 60 120 ID (A) Fig 9. Drain-source on-state resistance as a function of drain current; typical values 03ae53 10 VGS Tj (°C) 180 Fig 10. Normalized drain-source on-state resistance factor as a function of junction temperature 03ae52 103 ID = 7 A (V) Tj = 25 °C 8 Ciss C (pF) VDD = 15 V 6 Coss 102 Crss 4 2 0 0 5 10 15 Q G (nC) Fig 11. Gate-source voltage as a function of gate charge; typical values PHN203 Product data sheet 10 10−1 1 10 VDS (V) 102 Fig 12. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values All information provided in this document is subject to legal disclaimers. Rev. 05 — 27 April 2010 © NXP B.V. 2010. All rights reserved. 7 of 13 PHN203 NXP Semiconductors Dual N-channel TrenchMOS logic level FET 03ae51 30 VGS = 0 V IS (A) 20 10 150 °C Tj = 25 °C 0 0 0.3 0.6 0.9 1.2 VSD (V) Fig 13. Source current as a function of source-drain voltage; typical values PHN203 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 27 April 2010 © NXP B.V. 2010. All rights reserved. 8 of 13 PHN203 NXP Semiconductors Dual N-channel TrenchMOS logic level FET 7. Package outline SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE v M A Z 5 8 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.014 0.0075 0.20 0.19 0.16 0.15 0.05 0.01 0.01 0.004 0.028 0.012 inches 0.244 0.039 0.028 0.041 0.228 0.016 0.024 θ o 8 o 0 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT96-1 076E03 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 14. Package outline SOT96-1 (SO8) PHN203 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 27 April 2010 © NXP B.V. 2010. All rights reserved. 9 of 13 PHN203 NXP Semiconductors Dual N-channel TrenchMOS logic level FET 8. Revision history Table 7. Revision history Document ID Release date Data sheet status Change notice Supersedes PHN203 _5 20100427 Product data sheet - PHN203 _4 Modifications: • Various changes to content. PHN203 _4 20091208 Product data sheet - PHN203-03 PHN203 -03 20040126 Product data - PHN203 _2 PHN203_2 19990101 Product specification - PHN203 _1 PHN203 _1 19980204 Objective specification - - PHN203 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 27 April 2010 © NXP B.V. 2010. All rights reserved. 10 of 13 PHN203 NXP Semiconductors Dual N-channel TrenchMOS logic level FET 9. Legal information 9.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 9.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 9.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. PHN203 Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer’s third party customer(s) (hereinafter both referred to as “Application”). It is customer’s sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. All information provided in this document is subject to legal disclaimers. Rev. 05 — 27 April 2010 © NXP B.V. 2010. All rights reserved. 11 of 13 PHN203 NXP Semiconductors Dual N-channel TrenchMOS logic level FET Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 9.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV, FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE, ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse, QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET, TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V. HD Radio and HD Radio logo — are trademarks of iBiquity Digital Corporation. 10. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] PHN203 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 27 April 2010 © NXP B.V. 2010. All rights reserved. 12 of 13 PHN203 NXP Semiconductors Dual N-channel TrenchMOS logic level FET 11. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2 Thermal characteristics . . . . . . . . . . . . . . . . . . .4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . .10 Legal information. . . . . . . . . . . . . . . . . . . . . . . . 11 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Contact information. . . . . . . . . . . . . . . . . . . . . .12 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 27 April 2010 Document identifier: PHN203