LF PA K 33 PSMN040-100MSE N-channel 100 V 36.6 mΩ standard level MOSFET in LFPAK33 designed specifically for high power PoE applications 26 March 2013 Product data sheet 1. General description New standards and proprietary approaches are enabling Power-over-Ethernet (PoE) systems capable of delivering up to 90W to each powered device (PD). Such solutions place increased demands on the power sourcing equipment (PSE) in terms of “soft-start”, thermal management and power density requirements. 2. Features and benefits • • • • Enhanced forward biased safe operating area for superior linear mode operation Low Rdson for low conduction losses Ultra reliable LFPAK33 package for superior thermal and ruggedness performance Very low IDSS 3. Applications • • High power PoE applications (60W and higher) IEEE802.3at and proprietary solutions 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - - 100 V ID drain current Tj = 25 °C; VGS = 10 V; Fig. 1 - - 30 A Ptot total power dissipation Tmb = 25 °C; Fig. 2 - - 91 W VGS = 10 V; ID = 10 A; Tj = 25 °C; - 29.4 36.6 mΩ Static characteristics RDSon drain-source on-state resistance Fig. 13 Dynamic characteristics QGD gate-drain charge VGS = 10 V; ID = 10 A; VDS = 50 V; - 10.7 - nC QG(tot) total gate charge Tj = 25 °C; Fig. 14; Fig. 15 - 30 - nC VGS = 10 V; Tj(init) = 25 °C; ID = 30 A; - - 54 mJ Avalanche Ruggedness EDS(AL)S non-repetitive drainsource avalanche energy Vsup ≤ 100 V; RGS = 50 Ω; unclamped; Fig. 3 Scan or click this QR code to view the latest information for this product PSMN040-100MSE NXP Semiconductors N-channel 100 V 36.6 mΩ standard level MOSFET in LFPAK33 designed specifically for high power PoE applications 5. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline 1 S source 2 S source 3 S source 4 G gate mb D mounting base; connected to drain Graphic symbol D G S mbb076 1 2 3 4 LFPAK33 (SOT1210) 6. Ordering information Table 3. Ordering information Type number Package PSMN040-100MSE Name Description Version LFPAK33 Plastic single ended surface mounted package (LFPAK33); 4 leads SOT1210 7. Marking Table 4. Marking codes Type number Marking code PSMN040-100MSE M40E10 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - 100 V VDGR drain-gate voltage Tj ≥ 25 °C; Tj ≤ 175 °C; RGS = 20 kΩ - 100 V VGS gate-source voltage -20 20 V ID drain current VGS = 10 V; Tj = 25 °C; Fig. 1 - 30 A VGS = 10 V; Tmb = 100 °C; Fig. 1 - 21 A IDM peak drain current pulsed; tp ≤ 10 µs; Tmb = 25 °C; Fig. 4 - 121 A Ptot total power dissipation Tmb = 25 °C; Fig. 2 - 91 W Tstg storage temperature -55 175 °C PSMN040-100MSE Product data sheet All information provided in this document is subject to legal disclaimers. 26 March 2013 © NXP B.V. 2013. All rights reserved 2 / 13 PSMN040-100MSE NXP Semiconductors N-channel 100 V 36.6 mΩ standard level MOSFET in LFPAK33 designed specifically for high power PoE applications Symbol Parameter Tj Tsld(M) Conditions Min Max Unit junction temperature -55 175 °C peak soldering temperature - 260 °C - 70 A Source-drain diode IS source current Tmb = 25 °C ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 121 A VGS = 10 V; Tj(init) = 25 °C; ID = 30 A; - 54 mJ [1] Avalanche Ruggedness EDS(AL)S non-repetitive drain-source avalanche energy Vsup ≤ 100 V; RGS = 50 Ω; unclamped; Fig. 3 [1] ID (A) Continuous current is limited by package. 003aak532 40 03aa16 120 Pder (%) 30 80 20 40 10 0 Fig. 1. 0 25 50 75 100 125 150 175 Tj (°C) Continuous drain current as a function of mounting base temperature PSMN040-100MSE Product data sheet 0 200 Fig. 2. 0 100 150 Tmb (°C) 200 Normalized total power dissipation as a function of mounting base temperature All information provided in this document is subject to legal disclaimers. 26 March 2013 50 © NXP B.V. 2013. All rights reserved 3 / 13 PSMN040-100MSE NXP Semiconductors N-channel 100 V 36.6 mΩ standard level MOSFET in LFPAK33 designed specifically for high power PoE applications IAL (A) 003aak533 102 (1) 10 (2) 1 10-3 Fig. 3. 10-2 10-1 1 tAL (ms) 10 Single pulse avalanche rating; avalanche current as a function of avalanche time ID (A) 003aak534 103 102 Limit RDSon = VDS / ID tp = 10 us 100 us 10 10-1 Fig. 4. 1 ms 10 ms 100 ms DC 1 1 102 10 VDS (V) 103 Safe operating area; continuous and peak drain currents as a function of drain-source voltage 9. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from junction to mounting base Fig. 5 - 1.44 1.65 K/W PSMN040-100MSE Product data sheet All information provided in this document is subject to legal disclaimers. 26 March 2013 © NXP B.V. 2013. All rights reserved 4 / 13 PSMN040-100MSE NXP Semiconductors N-channel 100 V 36.6 mΩ standard level MOSFET in LFPAK33 designed specifically for high power PoE applications 003aak535 10 Zth(j-mb) (K/W) 1 δ = 0.5 0.2 0.1 10-1 P 0.05 δ= tp T 0.02 single shot 10-2 10-6 Fig. 5. 10-5 tp 10-4 10-3 10-2 10-1 t T tp (s) 1 Transient thermal impedance from junction to mounting base as a function of pulse duration 10. Characteristics Table 7. Characteristics Symbol Parameter Conditions Min Typ Max Unit drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = 25 °C 100 - - V ID = 250 µA; VGS = 0 V; Tj = -55 °C 90 - - V gate-source threshold voltage ID = 1 mA; VDS = VGS; Tj = 25 °C; 2.3 3.3 4 V - - 4.6 V 1 - - V VDS = 100 V; VGS = 0 V; Tj = 25 °C - 0.05 1 µA VDS = 100 V; VGS = 0 V; Tj = 175 °C - - 500 µA VGS = -20 V; VDS = 0 V; Tj = 25 °C - 10 100 nA VGS = 20 V; VDS = 0 V; Tj = 25 °C - 10 100 nA VGS = 10 V; ID = 10 A; Tj = 100 °C; - - 66 mΩ - - 99 mΩ - 29.4 36.6 mΩ - 1.65 - Ω Static characteristics V(BR)DSS VGS(th) Fig. 10; Fig. 11 ID = 1 mA; VDS = VGS; Tj = -55 °C; Fig. 10 ID = 1 mA; VDS = VGS; Tj = 175 °C; Fig. 10 IDSS IGSS RDSon drain leakage current gate leakage current drain-source on-state resistance Fig. 12; Fig. 13 VGS = 10 V; ID = 10 A; Tj = 175 °C; Fig. 12; Fig. 13 VGS = 10 V; ID = 10 A; Tj = 25 °C; Fig. 13 RG gate resistance PSMN040-100MSE Product data sheet f = 10 MHz All information provided in this document is subject to legal disclaimers. 26 March 2013 © NXP B.V. 2013. All rights reserved 5 / 13 PSMN040-100MSE NXP Semiconductors N-channel 100 V 36.6 mΩ standard level MOSFET in LFPAK33 designed specifically for high power PoE applications Symbol Parameter Conditions Min Typ Max Unit ID = 10 A; VDS = 50 V; VGS = 10 V; - 30 - nC - 24 - nC Dynamic characteristics QG(tot) total gate charge Tj = 25 °C; Fig. 14; Fig. 15 ID = 0 A; VDS = 0 V; VGS = 10 V; Tj = 25 °C QGS gate-source charge ID = 10 A; VDS = 50 V; VGS = 10 V; - 7.6 - nC QGS(th) pre-threshold gatesource charge Tj = 25 °C; Fig. 14; Fig. 15 - 4.5 - nC QGS(th-pl) post-threshold gatesource charge - 3.1 - nC QGD gate-drain charge - 10.7 - nC VGS(pl) gate-source plateau voltage ID = 10 A; VDS = 50 V; Tj = 25 °C; - 5.6 - V Ciss input capacitance VDS = 50 V; VGS = 0 V; f = 1 MHz; - 1470 - pF Coss output capacitance Tj = 25 °C; Fig. 16 - 110 - pF Crss reverse transfer capacitance - 80 - pF td(on) turn-on delay time VDS = 50 V; RL = 5 Ω; VGS = 10 V; - 8.3 - ns tr rise time RG(ext) = 5 Ω; Tj = 25 °C - 14.1 - ns td(off) turn-off delay time - 18.7 - ns tf fall time - 13 - ns Fig. 14; Fig. 15 Source-drain diode VSD source-drain voltage IS = 20 A; VGS = 0 V; Tj = 25 °C; Fig. 17 - 0.82 1.2 V trr reverse recovery time IS = 10 A; dIS/dt = -100 A/µs; VGS = 0 V; - 41 - ns recovered charge VDS = 50 V; Tj = 25 °C - 75 - nC Qr PSMN040-100MSE Product data sheet All information provided in this document is subject to legal disclaimers. 26 March 2013 © NXP B.V. 2013. All rights reserved 6 / 13 PSMN040-100MSE NXP Semiconductors N-channel 100 V 36.6 mΩ standard level MOSFET in LFPAK33 designed specifically for high power PoE applications ID (A) 003aak536 30 7V 20 V 10 V 8V 25 003aak537 80 RDSon VGS = 6.5 V 70 20 60 6V 15 50 5.5 V 10 40 5V 5 0 Fig. 6. 0 0.5 1 1.5 2 2.5 VDS (V) 20 3 Output characteristics; drain current as a Fig. 7. function of drain-source voltage; typical values gfs (S) ID (A) 24 9 18 6 12 3 6 2 4 6 8 ID (A) 0 10 Forward transconductance as a function of drain current; typical values PSMN040-100MSE Product data sheet Fig. 9. 6 10 12 14 16 18 VGS (V) 20 003aak539 175°C 0 1 2 3 4 Tj = 25°C 5 6 7 VGS (V) 8 Transfer characteristics; drain current as a function of gate-source voltage; typical values All information provided in this document is subject to legal disclaimers. 26 March 2013 8 30 12 0 4 Drain-source on-state resistance as a function of gate-source voltage; typical values 003aak538 15 0 Fig. 8. 30 4.5 V © NXP B.V. 2013. All rights reserved 7 / 13 PSMN040-100MSE NXP Semiconductors N-channel 100 V 36.6 mΩ standard level MOSFET in LFPAK33 designed specifically for high power PoE applications 003aak573 5 VGS(th) (V) ID (A) Max 4 3 typ max 10- 3 10- 4 Min 10- 5 1 0 -60 min 10- 2 Typ 2 003aak574 10- 1 -30 0 30 60 90 120 150 Tj (°C) 180 Fig. 10. Gate-source threshold voltage as a function of junction temperature 10- 6 2 VGS (V) 6 003aak540 100 RDSon a 4 Fig. 11. Sub-threshold drain current as a function of gate-source voltage 003aaj323 3 0 2.4 5.5 V 6V 6.5V 80 1.8 60 1.2 7V 8V 40 0.6 10 V 0 -60 0 60 120 Tj (°C) 20 180 Fig. 12. Normalized drain-source on-state resistance factor as a function of junction temperature PSMN040-100MSE Product data sheet 5 10 15 20 25 ID (A) 30 Fig. 13. Drain-source on-state resistance as a function of drain current; typical values All information provided in this document is subject to legal disclaimers. 26 March 2013 © NXP B.V. 2013. All rights reserved 8 / 13 PSMN040-100MSE NXP Semiconductors N-channel 100 V 36.6 mΩ standard level MOSFET in LFPAK33 designed specifically for high power PoE applications VDS VGS (V) ID 003aak542 10 VGS = 20V 8V 8 15 V 50 VGS(pl) 6 VGS(th) 24 V 80V VGS 4 QGS1 QGS2 QGS QGD QG(tot) 2 003aaa508 0 Fig. 14. Gate charge waveform definitions 0 5 10 15 20 25 30 QG (nC) 35 Fig. 15. Gate-source voltage as a function of gate charge; typical values 003aak543 104 C (pF) IS (A) 003aak544 30 24 Ciss 103 18 Coss 12 102 Crss 10 10-1 1 10 VDS (V) 175°C 6 0 102 0 0.2 0.4 Tj = 25°C 0.6 0.8 1 VSD (V) 1.2 Fig. 16. Input, output and reverse transfer capacitances Fig. 17. Source current as a function of source-drain as a function of drain-source voltage; typical voltage; typical values values PSMN040-100MSE Product data sheet All information provided in this document is subject to legal disclaimers. 26 March 2013 © NXP B.V. 2013. All rights reserved 9 / 13 PSMN040-100MSE NXP Semiconductors N-channel 100 V 36.6 mΩ standard level MOSFET in LFPAK33 designed specifically for high power PoE applications 11. Package outline Plastic single ended surface mounted package (LFPAK33); 8 leads E e1 L SOT1210 A A c1 b1 E1 mounting base D1 D H 1 4 e b w X A A1 c C θ Lp y C detail X 0 2.5 Dimensions Unit(1) mm 5 mm scale A A1 b b1 c c1 D(1) D1 E(1) E1 e e1 H L Lp w y max 0.90 0.10 0.35 0.35 0.20 0.30 2.70 2.35 3.40 2.45 3.40 0.25 0.50 nom 0.65 0.65 0.20 0.10 3.20 0.13 0.30 min 0.80 0.00 0.25 0.25 0.10 0.20 2.50 1.90 3.20 2.00 Note 1. Plastic or metal protrusions of 0.15 mm per side are not included. Outline version JEDEC 8° 0° sot1210_po References IEC θ JEITA European projection Issue date 11-12-19 12-03-12 SOT1210 Fig. 18. Package outline LFPAK33 (SOT1210) PSMN040-100MSE Product data sheet All information provided in this document is subject to legal disclaimers. 26 March 2013 © NXP B.V. 2013. All rights reserved 10 / 13 PSMN040-100MSE NXP Semiconductors N-channel 100 V 36.6 mΩ standard level MOSFET in LFPAK33 designed specifically for high power PoE applications In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. 12. Legal information 12.1 Data sheet status Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. 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Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the All information provided in this document is subject to legal disclaimers. 26 March 2013 © NXP B.V. 2013. All rights reserved 11 / 13 PSMN040-100MSE NXP Semiconductors N-channel 100 V 36.6 mΩ standard level MOSFET in LFPAK33 designed specifically for high power PoE applications grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of nonautomotive qualified products in automotive equipment or applications. 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Contents 1 General description ............................................... 1 2 Features and benefits ............................................1 3 Applications ........................................................... 1 4 Quick reference data ............................................. 1 5 Pinning information ............................................... 2 6 Ordering information ............................................. 2 7 Marking ................................................................... 2 8 Limiting values .......................................................2 9 Thermal characteristics .........................................4 10 Characteristics ....................................................... 5 11 Package outline ................................................... 10 12 12.1 12.2 12.3 12.4 Legal information .................................................11 Data sheet status ............................................... 11 Definitions ...........................................................11 Disclaimers .........................................................11 Trademarks ........................................................ 12 © NXP B.V. 2013. All rights reserved For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 26 March 2013 PSMN040-100MSE Product data sheet All information provided in this document is subject to legal disclaimers. 26 March 2013 © NXP B.V. 2013. All rights reserved 13 / 13