CSD75205W1015 www.ti.com.............................................................................................................................................................................................. SLPS222 – OCTOBER 2009 P-Channel NexFET™ Power MOSFET FEATURES 1 • • • • • • • • Table 1. PRODUCT SUMMARY Dual P-Ch MOSFETs Common Source Configuration Small Footprint 1mm × 1.5mm Gate-Source Voltage Clamp Gate ESD Protection –3kV Pb Free RoHS Compliant Halogen Free Drain to Source Voltage –20 V Qg Gate Charge Total (-4.5V) 1.6 nC Qgd Gate Charge Gate to Drain RDS(on) Drain to Source On Resistance RD1D2(on) APPLICATIONS • • • VDS VGS(th) Battery Management Load Switch Battery Protection Drain to Drain On Resistance 0.4 nC VGS = –1.8V 145 mΩ VGS = –2.5V 115 mΩ VGS = –4.5V 95 mΩ VGS = -1.8V 245 mΩ VGS = -2.5V 180 mΩ VGS = -4.5V 140 mΩ Threshold Voltage –0.65 V ORDERING INFORMATION DESCRIPTION The device has been designed to deliver the lowest on resistance and gate charge in the smallest outline possible with excellent thermal characteristics in an ultra low profile. Low on resistance coupled with the small footprint and low profile make the device ideal for battery operated space constrained applications. Device Package Media CSD75205W1015 1-mm × 1.5-mm Wafer Level Package 7-Inch Reel Ship 3000 Tape and Reel ABSOLUTE MAXIMUM RATINGS TA = 25°C unless otherwise stated VALUE UNIT VDS Drain to Source Voltage –20 V VGS Gate to Source Voltage -6 V Continuous Drain to Source Current, TC = 25°C (1) –1.2 A Pulsed Drain to Source Current, TC = 25°C (2) -9.6 A Continuous Source Pin Current -2.3 A Pulsed Source Pin Current (2) -30 A Continuous Gate Clamp Current -0.5 A IDS Top View Qty IS IG Pulsed Gate Clamp Current (2) PD Power Dissipation (1) TJ, TSTG Operating Junction and Storage Temperature Range -7 A 0.75 W –55 to 150 °C P0099-01 (1) (2) Per device, both sides in conduction Pulse duration 10μs, duty cycle ≤2% RDS(on) vs VGS RD1D2(on) vs VGS RD1D2(on) − On-State Resistance − mW RDS(on) − On-State Resistance − mΩ 500 ID = -1A 450 400 350 300 250 TJ = 25°C TJ = 125°C 200 150 100 50 0 0 1 2 3 4 5 -VGS − Gate to Source Voltage − V 6 G006 500 ID1D2 = -1A 450 400 350 TJ = 25°C 300 TJ = 125°C 250 200 150 100 50 0 0 1 2 3 4 -VGS − Gate to Source Voltage − V 5 6 G013 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated CSD75205W1015 SLPS222 – OCTOBER 2009.............................................................................................................................................................................................. www.ti.com ELECTRICAL CHARACTERISTICS TA = 25°C unless otherwise stated PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Static Characteristics BVDSS Drain to Source Voltage VGS = 0V, IDS = –250μA –20 BVGSS Gate to Source Voltage VDS = 0V, IG = -250μA -6.1 IDSS Drain to Source Leakage Current VGS = 0V, VDS = –16V IGSS Gate to Source Leakage Current VDS = 0V, VGS = -6V VGS(th) Gate to Source Threshold Voltage VDS = VGS, IDS = –250μA RDS(on) Drain to Source On Resistance –0.45 Source to Drain On Resistance gfs Transconductance V –1 μA –100 nA –0.65 –0.85 VGS = –1.8V, ID = –1A 145 180 mΩ VGS = –2.5V, ID = –1A 115 145 mΩ VGS = –4.5V, ID = –1A RD1D2(on) V -7.2 V 95 120 mΩ VGS = -1.8V, ID1D2 = –1A 245 305 mΩ VGS = -2.5V, ID1D2 = –1A 180 225 mΩ VGS = -4.5V, ID1D2 = –1A 140 175 mΩ VDS = –10V, ID = –1A 5 S Dynamic Characteristics CISS Input Capacitance VGS = 0V, VDS = –10V, f = 1MHz 205 265 pF pF COSS Output Capacitance 80 105 CRSS Reverse Transfer Capacitance 25 33 pF Qg Gate Charge Total (–4.5V) 1.6 2.2 nC Qgd Gate Charge - Gate to Drain Qgs Gate Charge - Gate to Source Qg(th) Gate Charge at Vth QOSS Output Charge td(on) Turn On Delay Time tr Rise Time td(off) Turn Off Delay Time tf Fall Time VDS = –10V, IDS = –1A VDS = –10.25V, VGS = 0V VDS = –10V, VGS = –4.5V, IDS = –1A, RG = 10Ω 0.4 nC 0.3 nC 0.12 nC 1.5 nC 6.3 ns 5.3 ns 32 ns 17 ns Diode Characteristics VSD Diode Forward Voltage IDS = –1A, VGS = 0V –0.75 –1 V Qrr Reverse Recovery Charge Vdd = –10.25V, IF = –1A, di/dt = 200A/μs 5.7 nC trr Reverse Recovery Time Vdd = –10.25V, IF = –1A, di/dt = 200A/μs 15.7 ns THERMAL CHARACTERISTICS TA = 25°C unless otherwise stated PARAMETER RθJA (1) (2) (3) 2 MAX UNIT (2) 212 °C/W (2) (3) 119 °C/W Thermal Resistance Junction to Ambient (1) Thermal Resistance Junction to Ambient MIN TYP Device mounted on FR4 material with Minimum Cu mounting area Measured with both devices biased in a parallel condition. Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated CSD75205W1015 www.ti.com.............................................................................................................................................................................................. SLPS222 – OCTOBER 2009 P-Chan 1.0x1.5 CSP TTA MAX Rev1 P-Chan 1.0x1.5 CSP TTA MIN Rev1 Max RθJA = 119°C/W when mounted on 1 inch2 (6.45 cm2) of 2-oz. (0.071-mm thick) Cu. Max RθJA = 212°C/W when mounted on minimum pad area of 2-oz. (0.071-mm thick) Cu. M0155-01 M0156-01 TYPICAL MOSFET CHARACTERISTICS Graphs are Per MOSFET at TA = 25°C, unless stated otherwise. Drain to Drain measurements are done with both MOSFETs in series (common source configuration). ZqJA – NormalizedThermal Impedance 10 1 0.5 0.3 0.1 0.1 0.05 0.01 Duty Cycle = t1/t2 0.02 0.01 P t1 t2 0.001 o Typical R qJA = 169 C/W (min Cu) TJ = P x ZqJA x R qJAJ Single Pulse 0.0001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1k tP – Pulse Duration–s G012 Figure 1. Transient Thermal Impedance Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 3 CSD75205W1015 SLPS222 – OCTOBER 2009.............................................................................................................................................................................................. www.ti.com TYPICAL MOSFET CHARACTERISTICS (continued) 5.0 5.0 4.5 4.5 VGS = -4.5V 4.0 3.5 -ID − Drain Current − A -ID − Drain Current − A Graphs are Per MOSFET at TA = 25°C, unless stated otherwise. Drain to Drain measurements are done with both MOSFETs in series (common source configuration). VGS = -2.5V 3.0 VGS = -2V 2.5 2.0 1.5 VGS = -1.5V VGS = -1.8V 1.0 VDS = 5V 4.0 3.5 3.0 TJ = 125°C 2.5 2.0 1.5 TJ = 25°C 1.0 TJ = -55°C 0.5 0.5 0.0 0.0 0.5 1.0 1.5 2.5 2.0 -VDS − Drain to Source Voltage − V 0.0 0.5 3.0 1 1.25 1.5 1.75 -VGS − Gate to Source Voltage − V G001 Figure 2. Saturation Characteristics 2 G002 Figure 3. Transfer Characteristics 6 250 ID = -1A VDS = -10V 5 f = 1MHz VGS = 0V 225 C − Capacitance − nF -VGS − Gate Voltage − V 0.75 4 3 2 200 175 CISS = CGD + CGS 150 COSS = CDS + CGD 125 100 75 CRSS = CGD 50 1 25 0 0 0 0.25 0.5 0.75 1 1.25 1.5 1.75 Qg − Gate Charge − nC 2 0 5 RD1D2(on) − On-State Resistance − mW RDS(on) − On-State Resistance − mΩ ID = -1A 400 350 300 TJ = 25°C TJ = 125°C 200 150 100 50 0 0 1 2 3 4 5 -VGS − Gate to Source Voltage − V Figure 6. On-State Resistance vs. Gate Voltage 4 Submit Documentation Feedback 20 G004 Figure 5. Capacitance 500 250 15 -VDS − Drain to Source Voltage − V G003 Figure 4. Gate Charge 450 10 6 G006 500 ID1D2 = -1A 450 400 350 TJ = 25°C 300 TJ = 125°C 250 200 150 100 50 0 0 1 2 3 4 5 -VGS − Gate to Source Voltage − V 6 G013 Figure 7. On-State Resistance vs. Gate Voltage Copyright © 2009, Texas Instruments Incorporated CSD75205W1015 www.ti.com.............................................................................................................................................................................................. SLPS222 – OCTOBER 2009 TYPICAL MOSFET CHARACTERISTICS (continued) Graphs are Per MOSFET at TA = 25°C, unless stated otherwise. Drain to Drain measurements are done with both MOSFETs in series (common source configuration). 10 ID1D2 = -1A VGS = -4.5V 1.4 -ISD − Source to Drain Current − A Normalized On-State Resistance 1.6 1.2 1.0 0.8 0.6 0.4 0.2 0.0 −75 −25 25 75 125 TJ = 125°C 0.1 TJ = 25°C 0.01 0.001 0.0001 0.0 175 TJ − Junction Temperature − °C 1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 -VSD − Source to Drain Voltage − V G007 Figure 8. Normalized On-State Resistance vs. Temperature G008 Figure 9. Typical Diode Forward Voltage 1.8 100 -ID − Drain Current − A -ID − Drain Current − A 1.6 10 1ms 1 10ms Area Limited by RDS(on) 0.1 100ms Single Pulse Typical RqJA = 169°C/W (min Cu) 0.01 0.01 1.2 1.0 0.8 0.6 0.4 0.2 DC 1 1.4 10 0.0 −50 100 -VDS − Drain Voltage − V −25 0 25 50 75 100 125 150 175 TJ − Junction Temperature − °C G009 Figure 10. Maximum Safe Operating Area G011 Figure 11. Maximum Drain Current vs. Temperature -VGS(th) − Threshold Voltage − V 1.0 ID = -250mA 0.9 0.8 0.7 0.6 0.5 0.4 0.4 0.2 0.1 0.0 −75 −25 25 75 125 TJ − Junction Temperature − °C 175 G005 Figure 12. Threshold Voltage vs. Temperature Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 5 CSD75205W1015 SLPS222 – OCTOBER 2009.............................................................................................................................................................................................. www.ti.com MECHANICAL DATA CSD75203W1015 Package Dimensions Pin 1 Mark 1 Solder Ball Ø 0.31 ±0.075 2 1 A B 15.00 B 1.00 +0.00 –0.10 0.50 A 2 Pin 1 Mark C C 1.00 +0.00 –0.10 0.50 Side View Bottom View 0.04 0.62 Max 0.38 Top View 0.62 Max Seating Plate Front View M0157-01 NOTE: All dimensions are in mm (unless otherwise specified) Pinout 6 POSITION DESIGNATION B1, B2 Source C1 Gate1 C2 Drain1 Submit Documentation Feedback A2 Gate2 A1 Drain2 Copyright © 2009, Texas Instruments Incorporated CSD75205W1015 www.ti.com.............................................................................................................................................................................................. SLPS222 – OCTOBER 2009 Land Pattern Recommendation Ø 0.25 1 2 1.00 0.50 A B C 0.50 M0158-01 NOTE: All dimensions are in mm (unless otherwise specified) Tape and Reel Information 4.00 ±0.10 Ø 1.50 ±0.10 4.00 ±0.10 Ø 0.60 0.86 ±0.05 +0.05 –0.10 1.65 ±0.05 2° Max 3.50 ±0.05 8.00 +0.30 –0.10 1.75 ±0.10 2.00 ±0.05 0.254 ±0.02 1.19 ±0.05 2° Max M0159-01 NOTE: All dimensions are in mm (unless otherwise specified) Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 7 CSD75205W1015 SLPS222 – OCTOBER 2009.............................................................................................................................................................................................. www.ti.com Package Marking Information Location 1st Line Product Code = NNNNN, First 5 digits after CSD (Fixed Text) NNNNN XXXXX 2nd Line XXXXX = Last 5 digits of lot number Pin 1 Identifier 8 Submit Documentation Feedback M0160-01 Copyright © 2009, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 11-Nov-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing CSD75205W1015 ACTIVE DSBGA YZF Pins Package Eco Plan (2) Qty 9 3000 TBD Lead/Ball Finish Call TI MSL Peak Temp (3) Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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