CSD16322Q5 www.ti.com................................................................................................................................................................................................. SLPS219 – AUGUST 2009 N-Channel NexFET™ Power MOSFET PRODUCT SUMMARY FEATURES 1 • • • • • • • • 2 Optimized for 5V Gate Drive Ultralow Qg and Qgd Low Thermal Resistance Avalanche Rated Pb Free Terminal Plating RoHS Compliant Halogen Free SON 5-mm × 6-mm Plastic Package VDS Drain to Source Voltage 25 V Qg Gate Charge Total (4.5V) 6.8 nC Qgd Gate Charge Gate to Drain RDS(on) VGS(th) • 8 1 D 7 2 4 1.1 Package Media CSD16322Q5 13-Inch Reel V Qty Ship 2500 Tape and Reel Text and br Added for Spacing VALUE UNIT VDS Drain to Source Voltage 25 V VGS Gate to Source Voltage +10 / –8 V Continuous Drain Current, TC = 25°C 97 A Continuous Drain Current (1) 21 A IDM Pulsed Drain Current, TA = 25°C (2) 136 A PD Power Dissipation (1) 3.1 W TJ, TSTG Operating Junction and Storage Temperature Range D –55 to 150 °C EAS Avalanche Energy, single pulse ID = 50A, L = 0.1mH, RG = 25Ω 125 mJ 6 D 5 D D (1) (2) P0094-01 RθJA = 39°C/W on 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 0.06-inch (1.52-mm) thick FR4 PCB. Pulse duration ≤300µs, duty cycle ≤2% RDS(on) vs VGS 12 11 10 GATE CHARGE 10 ID = 20A ID = 20A VDS = 12.5V 9 8 9 8 7 VG − Gate Voltage − V RDS(on) − On-State Resistance − mW mΩ Threshold Voltage SON 5-mm × 6-mm Plastic Package ID G mΩ 3.9 Device Top View 3 4.6 VGS = 8V TA = 25°C unless otherwise stated The NexFET™ power MOSFET has been designed to minimize losses in power conversion applications and optimized for 5V gate drive applications. S VGS = 4.5V ABSOLUTE MAXIMUM RATINGS DESCRIPTION S mΩ Text and br Added for Spacing Point-of-Load Synchronous Buck in Networking, Telecom and Computing Systems Synchronous or Control FET Applications S Drain to Source On Resistance nC 5.4 ORDERING INFORMATION APPLICATIONS • 1.3 VGS = 3V TC = 125°C 6 5 4 TC = 25°C 3 2 7 6 5 4 3 2 1 1 0 0 0 1 2 3 4 5 6 7 VGS − Gate to Source Voltage − V 8 9 10 0 2 4 6 8 10 Qg − Gate Charge − nC 12 14 G003 G006 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NexFET is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated CSD16322Q5 SLPS219 – AUGUST 2009................................................................................................................................................................................................. www.ti.com ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Static Characteristics BVDSS Drain to Source Voltage VGS = 0V, ID = 250µA IDSS Drain to Source Leakage Current VGS = 0V, VDS = 20V IGSS Gate to Source Leakage Current VDS = 0V, VGS = +10/–8V VGS(th) Gate to Source Threshold Voltage VDS = VGS, ID = 250µA RDS(on) Drain to Source On Resistance gfs Transconductance 25 0.9 V 1.1 1 µA 100 nA 1.4 V VGS = 3V, ID = 20A 5.4 7 mΩ VGS = 4.5V, ID = 20A 4.6 5.8 mΩ VGS = 8V, ID = 20A 3.9 5 mΩ VDS = 15V, ID = 20A 106 S Dynamic Characteristics CISS Input Capacitance COSS Output Capacitance 1050 1365 CRSS Reverse Transfer Capacitance Rg Series Gate Resistance Qg Gate Charge Total (4.5V) 6.8 Qgd Gate Charge Gate to Drain Qgs Gate Charge Gate to Source Qg(th) Gate Charge at Vth QOSS Output Charge td(on) Turn On Delay Time tr Rise Time td(off) Turn Off Delay Time tf Fall Time VGS = 0V, VDS = 12.5V, f = 1MHz 740 VDS = 12.5V, ID = 20A VDS = 13V, VGS = 0V VDS = 12.5V, VGS = 4.5V, ID = 20A RG =2Ω pF 950 pF 55 70 pF 1.1 2.2 Ω 9.7 nC 1.3 nC 2.4 nC 1.3 nC 17 nC 6.1 ns 10.7 ns 12.3 ns 3.7 ns Diode Characteristics VSD Diode Forward Voltage IS = 20A, VGS = 0V 0.8 1 V Qrr Reverse Recovery Charge VDD = 13V, IF = 20A, di/dt = 300A/µs 19 nC trr Reverse Recovery Time VDD = 13V, IF = 20A, di/dt = 300A/µs 21 ns THERMAL CHARACTERISTICS (TA = 25°C unless otherwise stated) MAX UNIT RθJC Thermal Resistance Junction to Case (1) PARAMETER 2.4 °C/W RθJA Thermal Resistance Junction to Ambient (1) (2) 50 °C/W (1) (2) 2 MIN TYP RθJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design. Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): CSD16322Q5 CSD16322Q5 www.ti.com................................................................................................................................................................................................. SLPS219 – AUGUST 2009 GATE Source GATE N-Chan 5x6 QFN TTA MIN Rev3 N-Chan 5x6 QFN TTA MAX Rev3 Max RθJA = 50°C/W when mounted on 1 inch2 (6.45 cm2) of 2-oz. (0.071-mm thick) Cu. Source DRAIN Max RθJA = 123°C/W when mounted on minimum pad area of 2-oz. (0.071-mm thick) Cu. DRAIN M0137-01 M0137-02 Spacing Spacing pacing pacing TYPICAL MOSFET CHARACTERISTICS (TA = 25°C unless otherwise stated) ZqJA – Normalized Thermal Impedance – °C/W 10 1 0.5 0.3 0.1 Duty Cycle = t1/t2 0.1 0.05 P 0.02 0.01 t1 0.01 t2 RthJA = 99°C/W (min Cu) TJ = P ´ ZqJA ´ RqJA Single Pulse 0.001 0.001 0.01 0.1 1 10 100 1k tp – Pulse Duration – s G012 Figure 1. Transient Thermal Impedance Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): CSD16322Q5 3 CSD16322Q5 SLPS219 – AUGUST 2009................................................................................................................................................................................................. www.ti.com TYPICAL MOSFET CHARACTERISTICS (continued) (TA = 25°C unless otherwise stated) TEXT 50 45 40 35 VGS = 3.5V 30 25 VGS = 2.5V 20 VDS = 5V 45 VGS = 4.5V ID − Drain Current − A ID − Drain Current − A T SPACING 50 VGS = 8V VGS = 2V 15 40 35 25 TC = 25°C 20 15 10 10 5 5 0 TC = 125°C 30 TC = −55°C 0 0 0.5 1 1.5 2 VDS − Drain to Source Voltage − V 1 1.5 1.25 1.75 2.5 2.25 2.75 VGS − Gate to Source Voltage − V G001 Figure 2. Saturation Characteristics 3 G002 Figure 3. Transfer Characteristics SPACING SPACING TSPACING SPACING 3 10 ID = 20A VDS = 12.5V 9 f = 1MHz VGS = 0V 2.5 C − Capacitance − nF 8 VG − Gate Voltage − V 2 7 6 5 4 3 2 2 COSS = CDS + CGD CISS = CGD + CGS 1.5 1 CRSS = CGD 0.5 1 0 0 0 2 4 6 8 10 12 Qg − Gate Charge − nC 0 14 5 G003 10 Figure 4. Gate Charge RDS(on) − On-State Resistance − mW VGS(th) − Gate-Source Threshold Voltage − V ID = 250mA 1.4 1.2 1 0.8 0.6 0.4 0.2 75 125 175 TC − Case Temperature − °C 12 11 10 ID = 20A 9 8 7 TC = 125°C 6 5 4 TC = 25°C 3 2 1 0 0 1 2 3 4 5 6 7 VGS − Gate to Source Voltage − V G005 Figure 6. Threshold Voltage vs. Temperature 4 G004 SPACING 1.6 25 25 SPACING SPACING −25 20 Figure 5. Capacitance SPACING 0 −75 15 VDS − Drain to Source Voltage − V 8 9 10 G006 Figure 7. On-State Resistance vs. Gate to Source Voltage Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): CSD16322Q5 CSD16322Q5 www.ti.com................................................................................................................................................................................................. SLPS219 – AUGUST 2009 TYPICAL MOSFET CHARACTERISTICS (continued) (TA = 25°C unless otherwise stated) SPACING SPACING vs vs 1.2 100 ID = 20A VGS = 4.5V ISD − Source to Drain Current − A Normalized On-State Resistance 1.4 1 0.8 0.6 0.4 0.2 0 −75 10 1 TC = 125°C 0.1 TC = 25°C 0.01 0.001 0.0001 −25 25 75 125 175 TC − Case Temperature − °C 0 0.2 0.4 G007 Figure 8. Normalized On-State Resistance vs. Temperature 1.2 G008 SPACING 1k I(AV) − Peak Avalanche Current − A 1k 100 ID − Drain Current − A 1 SPACING SPACING 1ms 10 10ms 100ms Area Limited by RDS(on) 1s 0.1 0.01 0.01 0.8 Figure 9. Typical Diode Forward Voltage SPACING 1 0.6 VSD − Source to Drain Voltage − V Single Pulse RthJA = 99oC/W (min Cu) 0.1 DC 1 10 TC = 25°C 10 TC = 125°C 1 0.00001 100 VD − Drain Voltage − V 100 0.0001 0.001 0.01 t(AV) − Time in Avalanche − ms G009 Figure 10. Maximum Safe Operating Area 0.1 G010 Figure 11. Single Pulse Unclamped Inductive Switching SPACING SPACING 120 ID − Drain Current − A 100 80 60 40 20 0 −50 −25 0 25 50 75 100 125 TC − Case Temperature − °C 150 175 G011 Figure 12. Maximum Drain Current vs. Temperature Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): CSD16322Q5 5 CSD16322Q5 SLPS219 – AUGUST 2009................................................................................................................................................................................................. www.ti.com MECHANICAL DATA Q5 Package Dimensions K L L c1 E1 E2 b D2 4 4 5 5 e 3 6 3 6 E D1 7 7 2 2 8 8 1 1 q Top View Bottom View Side View c E1 A q Front View M0140-01 DIM MILLIMETERS MIN MAX MIN MAX A 0.950 1.050 0.037 0.039 b 0.360 0.460 0.014 0.018 c 0.150 0.250 0.006 0.010 c1 0.150 0.250 0.006 0.010 D1 4.900 5.100 0.193 0.201 D2 4.320 4.520 0.170 0.178 E 4.900 5.100 0.193 0.201 E1 5.900 6.100 0.232 0.240 E2 3.920 4.12 0.154 0.162 e 6 INCHES 1.27 TYP K 0.760 L 0.510 θ 0.00 0.050 0.030 0.710 Submit Documentation Feedback 0.020 0.028 Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): CSD16322Q5 CSD16322Q5 www.ti.com................................................................................................................................................................................................. SLPS219 – AUGUST 2009 MILLIMETERS INCHES Recommended PCB Pattern DIM MIN MAX MIN MAX F1 F1 6.205 6.305 0.244 0.248 F2 4.460 4.560 0.176 0.180 F3 4.460 4.560 0.176 0.180 F4 0.650 0.700 0.026 0.028 F5 0.620 0.670 0.024 0.026 F6 0.630 0.680 0.025 0.027 F7 0.700 0.800 0.028 0.031 F8 0.650 0.700 0.026 0.028 F9 0.620 0.670 0.024 0.026 F10 4.900 5.000 0.193 0.197 F11 4.460 4.560 0.176 0.180 F7 F3 8 1 F2 F11 F5 F9 5 4 F6 F8 F4 F10 M0139-01 For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCB Layout Techniques. K0 4.00 ±0.10 (See Note 1) 0.30 ±0.05 2.00 ±0.05 +0.10 –0.00 12.00 ±0.30 Ø 1.50 1.75 ±0.10 Q5 Tape and Reel Information 5.50 ±0.05 B0 R 0.30 MAX A0 8.00 ±0.10 Ø 1.50 MIN A0 = 6.50 ±0.10 B0 = 5.30 ±0.10 K0 = 1.40 ±0.10 R 0.30 TYP M0138-01 Notes: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2 2. Camber not to exceed 1mm in 100mm, noncumulative over 250mm 3. Material: black static-dissipative polystyrene 4. All dimensions are in mm, unless otherwise specified. 5. A0 and B0 measured on a plane 0.3mm above the bottom of the pocket 6. MSL1 260°C (IR and convection) PbF reflow compatible Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): CSD16322Q5 7 CSD16322Q5 SLPS219 – AUGUST 2009................................................................................................................................................................................................. www.ti.com Package Marking Information Location 8 1st Line CSD 5 5 8 4 1 = Fixed Characters NNNNN = 5-digit Product Code 2nd Line (Date Code) YY = Last 2 digits of the Year WW = 2-digit Work Week C = Country of Origin CSDNNNNN YYWWC LLLLL > Philippines = P > Taiwan = T > China = C 3rd Line LLLLL = Last 5 digits of the Wafer Lot # 1 4 Pin 1 Identifier M0141-01 8 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): CSD16322Q5 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing CSD16322Q5 ACTIVE SON DQH Pins Package Eco Plan (2) Qty 8 2500 Green (RoHS & no Sb/Br) Lead/Ball Finish Call TI MSL Peak Temp (3) Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. 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