CSD16301Q2 www.ti.com.............................................................................................................................................................................................. SLPS235 – OCTOBER 2009 N-Channel NexFET™ Power MOSFETs Check for Samples: CSD16301Q2 FEATURES 1 • • • • • • 2 Table 1. PRODUCT SUMMARY Ultralow Qg and Qgd Low Thermal Resistance Pb Free Terminal Plating RoHS Compliant Halogen Free SON 2-mm × 2-mm Plastic Package APPLICATIONS • • VDS Drain to Source Voltage 25 V Qg Gate Charge Total (–4.5V) 2 nC Qgd Gate Charge Gate to Drain RDS(on) Drain to Source On Resistance VGS(th) Threshold Voltage DC-DC Converters Battery and Load Management Applications Top View D 1 6 5 2 3 G 4 S D S mΩ VGS = 8V 19 mΩ 1.1 Media CSD16301Q2 13-Inch Reel V Qty Ship 3000 Tape and Reel Text and br Added for Spacing ABSOLUTE MAXIMUM RATINGS TA = 25°C unless otherwise stated VALUE UNIT VDS Drain to Source Voltage 25 V VGS Gate to Source Voltage +10 / –8 V Continuous Drain Current, TC = 25°C 5 A Continuous Drain Current (1) 5 A IDM Pulsed Drain Current, TA = 25°C (2) 20 A PD Power Dissipation (1) 2.3 W TJ, TSTG Operating Junction and Storage Temperature Range –55 to 150 °C EAS Avalanche Energy, single pulse ID = 14A, L = 0.1mH, RG = 25Ω 10 mJ Packaged Limited. Pulse duration 10μs, duty cycle ≤2% RDS(on) vs VGS GATE CHARGE 80 8 ID = 4A 70 7 VG − Gate Voltage − V RDS(on) − On-State Resistance − mΩ 23 Package (1) (2) P0108-01 VGS = 4.5V SON 2-mm × 2-mm Plastic Package D D mΩ Device ID D nC 27 Text and br Added for Spacing ORDERING INFORMATION DESCRIPTION The NexFET™ power MOSFET has been designed to minimize losses in power conversion and load management applications. The SON 2x2 offers excellent thermal performance for the size of the package. 0.4 VGS = 3V 60 50 TC = 125°C 40 30 20 10 0 1 2 3 6 5 4 3 2 1 TC = 25°C 0 ID = 4A VDS = 12.5V 4 5 6 7 8 VGS − Gate to Source Voltage − V 9 10 G006 0 0.0 0.5 1.0 1.5 2.0 2.5 Qg − Gate Charge − nC 3.0 3.5 G003 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NexFET is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated CSD16301Q2 SLPS235 – OCTOBER 2009.............................................................................................................................................................................................. www.ti.com ELECTRICAL CHARACTERISTICS TA = 25°C, unless otherwise specified PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Static Characteristics BVDSS Drain to Source Voltage VGS = 0V, ID = 250μA IDSS Drain to Source Leakage Current VGS = 0V, VDS = 20V IGSS Gate to Source Leakage Current VDS = 0V, VGS = +10/–8V VGS(th) Gate to Source Threshold Voltage VDS = VGS, IDS = 250μA RDS(on) Drain to Source On Resistance gfs Transconductance 25 V 1 μA 100 nA 1.1 1.4 V VGS = 3V, IDS = 4A 27 34 mΩ VGS = 4.5V, IDS = 4A 23 29 mΩ VGS = 8V, IDS = 4A 19 24 mΩ 0.9 VDS = 15V, IDS = 4A 16.5 S Dynamic Characteristics CISS Input Capacitance COSS Output Capacitance CRSS Reverse Transfer Capacitance Rg Series Gate Resistance Qg Gate Charge Total (4.5V) Qgd Gate Charge – Gate to Drain Qgs Gate Charge Gate to Source Qg(th) Gate Charge at Vth QOSS Output Charge td(on) Turn On Delay Time tr Rise Time 4.4 ns td(off) Turn Off Delay Time 4.1 ns tf Fall Time 1.7 ns VGS = 0V, VDS = 12.5V, f = 1MHz VDS = 10V, IDS = 4A VDS = 12.5V, VGS = 0V VDS = 12.5V, VGS = 4.5V, IDS = 4A RG = 2Ω 260 340 pF 165 215 pF 13 17 pF 1.3 2.6 Ω 2 2.8 nC 0.4 nC 0.6 nC 0.3 nC 3 nC 2.7 ns Diode Characteristics VSD Diode Forward Voltage IDS = 4A, VGS = 0V 0.8 1 V Qrr Reverse Recovery Charge VDD = 12.5V, IF = 4A, di/dt = 200A/μs 5.1 nC trr Reverse Recovery Time VDD = 12.5V, IF = 4A, di/dt = 200A/μs 11 ns THERMAL CHARACTERISTICS TA = 25°C, unless otherwise specified PARAMETER RθJC Thermal Resistance Junction to Case (1) RθJA Thermal Resistance Junction to Ambient (1) (1) (2) 2 MIN (2) 2 TYP MAX UNIT 8.4 °C/W 69 °C/W 2 RθJC is determined with the device mounted on a 1-inch (6.45-cm ), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design. Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): CSD16301Q2 CSD16301Q2 www.ti.com.............................................................................................................................................................................................. SLPS235 – OCTOBER 2009 GATE GATE Source Source N-Chan N-Chan Max RθJA = 69°C/W when mounted on 1 inch2 (6.45 cm2) of 2-oz. (0.071-mm thick) Cu. Max RθJA = 220°C/W when mounted on minimum pad area of 2-oz. (0.071-mm thick) Cu. DRAIN DRAIN M0164-02 M0164-01 TYPICAL MOSFET CHARACTERISTICS TA = 25°C, unless otherwise specified ZθJA − Normalized Thermal Impedance 10 1 0.5 0.3 0.1 0.1 Duty Cycle = t1/t2 0.05 0.01 P 0.02 0.01 t1 t2 Single Pulse o Typical RqJA = 177 C/W (min Cu) TJ = P x ZqJA x RqJA 0.001 0.0001 0.001 0.01 0.1 1 10 100 t P − Pulse Duration − s 1k G012 Figure 1. Transient Thermal Impedance Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): CSD16301Q2 3 CSD16301Q2 SLPS235 – OCTOBER 2009.............................................................................................................................................................................................. www.ti.com TYPICAL MOSFET CHARACTERISTICS (continued) TA = 25°C, unless otherwise specified 10 10 9 7 8 ID − Drain Current − A 8 ID − Drain Current − A VDS = 5V 9 VGS = 4.5V VGS = 3.5V 6 VGS = 2.5V 5 4 VGS = 2V 3 2 7 TC = 125°C 6 5 TC = 25°C 4 3 2 VGS = 1.5V TC = −55°C 1 1 0 0.0 0 1.00 0.5 1.0 1.5 2.0 VDS − Drain to Source Voltage − V 2.00 2.25 2.50 G002 0.6 ID = 4A VDS = 12.5V 7 f = 1MHz VGS = 0V 0.5 C − Capacitance − nF 6 5 4 3 2 COSS = CDS + CGD 0.4 CISS = CGD + CGS 0.3 0.2 CRSS = CGD 0.1 1 0 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Qg − Gate Charge − nC 0 3.5 5 10 15 20 25 VDS − Drain to Source Voltage − V G003 Figure 4. Gate Charge G004 Figure 5. Capacitance 1.4 80 RDS(on) − On-State Resistance − mΩ VGS(th) − Threshold Voltage − V 1.75 Figure 3. Transfer Characteristics 8 ID = 250µA 1.2 1.0 0.8 0.6 0.4 0.2 0.0 −75 ID = 4A 70 60 50 TC = 125°C 40 30 20 10 TC = 25°C 0 −25 25 75 125 TC − Case Temperature − °C 175 0 1 2 3 4 5 6 7 VGS − Gate to Source Voltage − V G005 Figure 6. Threshold Voltage vs. Temperature 4 1.50 VGS − Gate to Source Voltage − V G001 Figure 2. Saturation Characteristics VG − Gate Voltage − V 1.25 8 9 10 G006 Figure 7. On-State Resistance vs. Gate to Source Voltage Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): CSD16301Q2 CSD16301Q2 www.ti.com.............................................................................................................................................................................................. SLPS235 – OCTOBER 2009 TYPICAL MOSFET CHARACTERISTICS (continued) TA = 25°C, unless otherwise specified 10 ID = 4A VGS = 4.5V 1.6 ISD − Source to Drain Current − A Normalized On-State Resistance 1.8 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 −75 −25 25 75 125 0.1 0.01 TC = 25°C 0.001 0.2 0.4 0.6 0.8 VSD − Source to Drain Voltage − V G007 Figure 8. Normalized On-State Resistance vs. Temperature 1.0 G008 Figure 9. Typical Diode Forward Voltage 100 I(AV) − Peak Avalanche Current − A 100 ID − Drain Current − A TC = 125°C 0.0001 0.0 175 TC − Case Temperature − °C 1 100ms 10 1ms 1 10ms Area Limited by RDS(on) 0.1 100ms 1s Single Pulse o Typical RqJA = 177 C/W (min Cu) 0.01 0.01 0.1 DC 1 10 TC = 125oC 10 1 0.01 100 VD - Drain Voltage - V TC = 25oC 0.1 1 10 100 t(AV) − Time in Avalanche − ms G009 Figure 10. Maximum Safe Operating Area Figure 11. 6 ID − Drain Current − A 5 4 3 2 1 0 −50 −25 0 25 50 75 100 125 150 175 TC − Case Temperature − °C G011 Figure 12. Maximum Drain Current vs. Temperature Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): CSD16301Q2 5 CSD16301Q2 SLPS235 – OCTOBER 2009.............................................................................................................................................................................................. www.ti.com MECHANICAL DATA Q2 Package Dimensions D2 D K3 K1 K K2 4 1 2 3 4 5 6 3 2 1 K4 E E1 E2 5 E3 6 L Pin 1 Dot Top View Pin 1 ID e b D1 A A1 C Bottom View M0165-01 Front View DIM MILLIMETERS NOM MAX MIN NOM MAX A 0.700 0.750 0.800 0.028 0.030 0.032 A1 0.000 0.050 0.000 b 0.250 0.350 0.010 C 0.300 0.203 TYP D D1 0.950 0.080 TYP 1.000 0.036 0.038 0.300 TYP 0.012 TYP E 2.000 TYP 0.080 TYP 0.900 1.000 1.100 0.036 0.040 E2 0.280 TYP 0.0112 TYP E3 0.470 TYP 0.0188 TYP e 0.650 BSC 0.026 TYP K 0.280 TYP 0.0112 TYP K1 0.350 TYP 0.014 TYP K2 0.200 TYP 0.008 TYP K3 0.200 TYP 0.008 TYP K4 0.470 TYP 0.0188 TYP L 0.200 0.25 0.014 0.008 TYP 2.000 TYP 0.900 0.002 0.012 D2 E1 6 INCHES MIN 0.300 0.008 Submit Documentation Feedback 0.010 0.040 0.044 0.012 Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): CSD16301Q2 CSD16301Q2 www.ti.com.............................................................................................................................................................................................. SLPS235 – OCTOBER 2009 For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCB Layout Techniques. Recommended PCB Pattern 0.85 2.30 1.10 1.05 0.22 0.65 TYP 1.40 1 0.46 0.40 TYP 0.25 M0167-01 Q2 Tape and Reel Information 4.00 ±0.10 Ø 1.50 ±0.10 4.00 ±0.10 Ø 1.00 ±0.25 1.00 ±0.05 2.30 ±0.05 10° Max 3.50 ±0.05 8.00 +0.30 –0.10 1.75 ±0.10 2.00 ±0.05 0.254 ±0.02 2.30 ±0.05 10° Max M0168-01 Notes: 1. Measured from centerline of spocket hole to centerline of pocket 2. Cumulative tolerance of 10 sprocket holes is ±0.20 3. Measured from centerline of sprocket hole to centerline of pocket 4. Other material available 5. Typical SR of form tape Max 109 OHM/SQ 6. All dimensions are in mm, unless otherwise specified. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): CSD16301Q2 7 CSD16301Q2 SLPS235 – OCTOBER 2009.............................................................................................................................................................................................. www.ti.com Package Marking Information Location Top View 1st Line NNNN = 4-digit Product Code 6 Bottom View 4 4 6 3 3 1 2nd Line (Date Code) Y = Last digit of the Year WW = 2-digit Work Week C = Country of Origin > Philippines = P NNNN YWWC > Taiwan = T > China = C > Malaysia = M Product Code = CSD16301 NNNN Mark = 1631 1 Pin 1 Identifier M0166-01 8 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): CSD16301Q2 PACKAGE OPTION ADDENDUM www.ti.com 16-Oct-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing CSD16301Q2 ACTIVE SON DQK Pins Package Eco Plan (2) Qty 6 3000 Green (RoHS & no Sb/Br) Lead/Ball Finish Call TI MSL Peak Temp (3) Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. 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