TI CSD17304Q3

CSD17304Q3
www.ti.com
SLPS258 – FEBRUARY 2010
30V N-Channel NexFET™ Power MOSFETs
Check for Samples: CSD17304Q3
PRODUCT SUMMARY
FEATURES
1
•
•
•
•
•
•
•
•
2
Optimized for 5V Gate Drive
Ultralow Qg and Qgd
Low Thermal Resistance
Avalanche Rated
Pb Free Terminal Plating
RoHS Compliant
Halogen Free
SON 3.3-mm × 3.3-mm Plastic Package
VDS
Drain to Source Voltage
30
V
Qg
Gate Charge Total (4.5V)
5.1
nC
Qgd
Gate Charge Gate to Drain
RDS(on)
Drain to Source On Resistance
VGS(th)
nC
9.8
mΩ
VGS = 4.5V
6.9
mΩ
VGS = 8V
5.9
mΩ
Threshold Voltage
1.3
V
ORDERING INFORMATION
Device
Package
Media
CSD17304Q3
SON 3.3-mm × 3.3-mm
Plastic Package
13-Inch
Reel
APPLICATIONS
•
•
1.1
VGS = 3V
Notebook Point of Load
Point-of-Load Synchronous Buck in
Networking, Telecom, and Computing Systems
Qty
Ship
2500
Tape and
Reel
ABSOLUTE MAXIMUM RATINGS
DESCRIPTION
TA = 25°C unless otherwise stated
The NexFET™ power MOSFET has been designed
to minimize losses in power conversion applications
and optimized for 5V gate drive applications.
Top View
S
8
1
D
S
2
7
D
S
3
6
D
G
4
5
D
VALUE
UNIT
VDS
Drain to Source Voltage
30
V
VGS
Gate to Source Voltage
+10 / –8
V
Continuous Drain Current, TC = 25°C
56
A
Continuous Drain Current(1)
15
A
IDM
Pulsed Drain Current, TA = 25°C(2)
88
A
PD
Power Dissipation(1)
2.7
W
TJ,
TSTG
Operating Junction and Storage
Temperature Range
–55 to 150
°C
EAS
Avalanche Energy, Single Pulse
ID = 42, L = 0.1mH, RG = 25Ω
88
mJ
ID
(1) Typical RqJA = 46°C/W on a 1-inch2 (6.45-cm2),
2-oz. (0.071-mm thick) Cu pad on a 0.06-inch (1.52-mm) thick
FR4 PCB.
(2) Pulse duration ≤300ms, duty cycle ≤2%
D
P0095-01
Text 4 Spacing
RDS(on) vs VGS
Text 4 Spacing
GATE CHARGE
8
ID = 17A
18
VGS - Gate-to-Source Voltage - V
RDS(on) - On-State Resistance - mΩ
20
16
14
T C = 125°C
12
10
8
6
4
T C = 25°C
6
5
4
3
2
2
1
0
0
0
1
2
3
4
5
6
7
8
VGS - Gate-to-Source Voltage - V
9
10
G006
ID = 17A
VDS = 15V
7
0
2
4
6
Qg - Gate Charge - nC
8
10
G003
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NexFET is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
CSD17304Q3
SLPS258 – FEBRUARY 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Static Characteristics
BVDSS
Drain to Source Voltage
VGS = 0V, ID = 250mA
IDSS
Drain to Source Leakage Current
VGS = 0V, VDS = 24V
IGSS
Gate to Source Leakage Current
VDS = 0V, VGS = +10 / –8
VGS(th)
Gate to Source Threshold Voltage
VDS = VGS, ID = 250mA
RDS(on)
Drain to Source On Resistance
gfs
Transconductance
30
0.9
V
1
mA
100
nA
1.3
1.8
V
VGS = 3V, ID = 17A
9.8
12.6
mΩ
VGS = 4.5V, ID = 17A
6.9
8.8
mΩ
VGS = 8V, ID = 17A
5.9
7.5
mΩ
VDS = 15V, ID = 17A
48
S
Dynamic Characteristics
CISS
Input Capacitance
COSS
Output Capacitance
735
955
pF
390
505
CRSS
pF
Reverse Transfer Capacitance
29
38
pF
Rg
Series Gate Resistance
1.1
2.2
Ω
Qg
Gate Charge Total (4.5V)
5.1
6.6
nC
Qgd
Gate Charge Gate to Drain
1.1
nC
Qgs
Gate Charge Gate to Source
1.8
nC
Qg(th)
Gate Charge at Vth
0.9
nC
QOSS
Output Charge
9.9
nC
td(on)
Turn On Delay Time
5.1
ns
tr
Rise Time
td(off)
Turn Off Delay Time
tf
Fall Time
VGS = 0V, VDS = 15V,
f = 1MHz
VDS = 15V, ID = 17A
VDS = 13V, VGS = 0V
VDS = 15V, VGS = 4.5V,
ID = 17A , RG = 2Ω
9.1
ns
10.4
ns
3.1
ns
Diode Characteristics
VSD
Diode Forward Voltage
Qrr
Reverse Recovery Charge
trr
Reverse Recovery Time
IDS = 17A, VGS = 0V
0.85
VDD = 13V, IF = 17A,
di/dt = 300A/ms
14.5
1
nC
V
17.3
ns
THERMAL CHARACTERISTICS
(TA = 25°C unless otherwise stated)
PARAMETER
RqJC
RqJA
(1)
(2)
2
MIN
Thermal Resistance Junction to Case (1)
Thermal Resistance Junction to Ambient
(1) (2)
2
TYP
MAX
UNIT
3.9
°C/W
57
°C/W
2
RqJC is determined with the device mounted on a 1-inch (6.45-cm ), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm ×
3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RqJC is specified by design, whereas RqJA is determined by the user’s board design.
Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu.
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Product Folder Link(s): CSD17304Q3
CSD17304Q3
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SLPS258 – FEBRUARY 2010
GATE
GATE
Source
Source
Max RqJA = 57°C/W
when mounted on
1 inch2 (6.45 cm2) of
2-oz. (0.071-mm thick)
Cu.
Max RqJA = 158°C/W
when mounted on a
minimum pad area of
2-oz. (0.071-mm thick)
Cu.
DRAIN
DRAIN
M0161-02
M0161-01
TYPICAL MOSFET CHARACTERISTICS
(TA = 25°C unless otherwise stated)
ZqJA - Normalized Thermal Impedance
10
1
0.5
0.3
0.1
Duty Cycle = t1/t2
0.1
0.05
P
0.01
0.02
0.01
t1
t2
Single Pulse
0.001
0.001
0.01
Typical RqJA = 126°C/W (min Cu)
TJ = P ´ ZqJA ´ RqJA
0.1
1
tp - Pulse Duration - s
10
100
1k
G012
Figure 1. Transient Thermal Impedance
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CSD17304Q3
SLPS258 – FEBRUARY 2010
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TYPICAL MOSFET CHARACTERISTICS (continued)
50
50
45
45
IDS - Drain-to-Source Current - A
IDS - Drain-to-Source Current - A
(TA = 25°C unless otherwise stated)
VGS = 2.5V
40
VGS = 8V
35
30
25
VGS = 4.5V
20
VGS = 3.5V
15
10
VGS = 3V
VDS = 5V
40
35
30
T C = 125°C
25
20
T C = 25°C
15
T C = -55°C
10
5
5
0
0
0
0.5
1
1.5
VDS - Drain-to-Source Voltage - V
0
2
0.5
Figure 2. Saturation Characteristics
7
G002
f = 1MHz
VGS = 0V
1.8
1.6
C - Capacitance - nF
6
5
4
3
2
1.4
Coss = Cds + Cgd
1.2
Ciss = Cgd + Cgs
1
0.8
0.6
0.4
1
Crss = Cgd
0.2
0
0
2
4
6
Qg - Gate Charge - nC
8
10
0
5
10
15
20
VDS - Drain-to-Source Voltage - V
G003
Figure 4. Gate Charge
25
30
G004
Figure 5. Capacitance
20
1.6
RDS(on) - On-State Resistance - mΩ
ID = 250µA
1.4
VGS(th) - Threshold Voltage - V
3.5
2
ID = 17A
VDS = 15V
0
1.2
1
0.8
0.6
0.4
0.2
0
-75
ID = 17A
18
16
14
T C = 125°C
12
10
8
6
4
T C = 25°C
2
0
-25
25
75
T C - Case Temperature - °C
125
175
0
1
G005
Figure 6. Threshold Voltage vs. Temperature
4
3
Figure 3. Transfer Characteristics
8
VGS - Gate-to-Source Voltage - V
1
1.5
2
2.5
VGS - Gate-to-Source Voltage - V
G001
2
3
4
5
6
7
8
VGS - Gate-to-Source Voltage - V
9
10
G006
Figure 7. On-State Resistance vs. Gate-to-Source Voltage
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Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): CSD17304Q3
CSD17304Q3
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SLPS258 – FEBRUARY 2010
TYPICAL MOSFET CHARACTERISTICS (continued)
(TA = 25°C unless otherwise stated)
1.4
100
ID = 17A
VGS = 8V
ISD - Source-to-Drain Current - A
Normalized On-State Resistance
1.6
1.2
1
0.8
0.6
0.4
0.2
-75
10
1
T C = 125°C
0.1
T C = 25°C
0.01
0.001
0.0001
-25
25
75
T C - Case Temperature - °C
125
175
0
Figure 8. Normalized On-State Resistance vs. Temperature
0.4
0.6
0.8
VSD - Source-to-Drain Voltage - V
1
1.2
G008
Figure 9. Typical Diode Forward Voltage
1k
I(AV) - Peak Avalanche Current - A
1k
IDS - Drain-to-Source Current - A
0.2
G007
100
1ms
10
10ms
1
11110
100ms
Area Limited
by RDS(on)
0.1
1s
Single Pulse
Typical R θJA = 126°C/W (min Cu)
0.01
0.01
DC
0.1
1
10
VDS - Drain-to-Source Voltage - V
100
100
T C = 25°C
10
T C = 125°C
1
0.01
G009
Figure 10. Maximum Safe Operating Area
0.1
1
10
t(AV) - Time in Avalanche - ms
100
G010
Figure 11. Single Pulse Unclamped Inductive Switching
IDS - Drain-to-Source Current - A
80
70
60
50
40
30
20
10
0
-50
-25
0
25
50
75
100 125
T C - Case Temperature - °C
150
175
G011
Figure 12. Maximum Drain Current vs. Temperature
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Product Folder Link(s): CSD17304Q3
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CSD17304Q3
SLPS258 – FEBRUARY 2010
www.ti.com
MECHANICAL DATA
Q3 Package Dimensions
D2
D
H
L
1
2
7
3
6
4
5
5
4
3
b
E2
E
6
e
E
7
2
8
8
1
q
L1
Top View
A1
Bottom View
A
Side View
c
D
Front View
M0142-01
DIM
MILLIMETERS
NOM
MAX
MIN
NOM
MAX
A
0.950
1.000
1.100
0.037
0.039
0.043
A1
0.000
0.000
0.050
0.000
0.000
0.002
b
0.280
0.340
0.400
0.011
0.013
0.016
c
0.150
0.200
0.250
0.006
0.008
0.010
D
3.200
3.300
3.400
0.126
0.130
0.134
D1
–
–
–
–
–
–
D2
1.650
1.750
1.800
0.065
0.069
0.071
E
3.200
3.300
3.400
0.126
0.130
0.134
E1
–
–
–
–
–
–
E2
2.350
2.450
2.550
0.093
0.096
0.100
e
6
INCHES
MIN
0.650 TYP
0.026
H
0.35
0.450
0.550
0.014
0.018
0.022
L
0.35
0.450
0.550
0.014
0.018
0.022
L1
–
–
–
–
–
–
q
–
–
–
–
–
–
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Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): CSD17304Q3
CSD17304Q3
www.ti.com
SLPS258 – FEBRUARY 2010
2.31
1
8
8
1
0.65 Typ.
2.45
5
4
5
3.50
0.56
0.41
4
0.50 Typ.
Recommended PCB Pattern
0.63
M0143-01
For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through
PCB Layout Techniques.
1.75 ±0.10
Q3 Tape and Reel Information
4.00 ±0.10 (See Note 1)
2.00 ±0.05
Ø 1.50
+0.10
–0.00
3.60
1.30
3.60
5.50 ±0.05
12.00
+0.30
–0.10
8.00 ±0.10
M0144-01
Notes:
1. 10-sprocket hole-pitch cumulative tolerance ±0.2
2. Camber not to exceed 1mm in 100mm, noncumulative over 250mm
3. Material: black static-dissipative polystyrene
4. All dimensions are in mm (unless otherwise specified)
5. Thickness: 0.30 ±0.05mm
6. MSL1 260°C (IR and convection) PbF reflow compatible
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CSD17304Q3
SLPS258 – FEBRUARY 2010
www.ti.com
Package Marking Information
Location
8
1st Line
CSD
= Fixed Characters
NNNNN
= Product Code
2nd Line (Date Code)
YY
= Last 2 digits of the Year
WW
= 2-digit Work Week
C
= Country of Origin
5
5
8
4
1
CSDNNNNN
YYWWC
LLLLL
> Philippines = P
> Taiwan = T
> China = C
1
3rd Line
LLLLL
= Last 5 digits of the Wafer Lot #
4
Pin 1
Identifier
M0145-01
8
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PACKAGE OPTION ADDENDUM
www.ti.com
27-May-2010
PACKAGING INFORMATION
Orderable Device
CSD17304Q3
Status
(1)
ACTIVE
Package Type Package
Drawing
SON
DQG
Pins
Package Qty
8
2500
Eco Plan
(2)
Pb-Free (RoHS
Exempt)
Lead/
Ball Finish
Call TI
MSL Peak Temp
(3)
Samples
(Requires Login)
Level-1-260C-UNLIM
Request Free Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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