CSD17505Q5A www.ti.com SLPS301 – DECEMBER 2010 30V, N-Channel NexFET™ Power MOSFETs Check for Samples: CSD17505Q5A PRODUCT SUMMARY FEATURES 1 • • • • • • • 2 TA = 25°C unless otherwise stated Ultralow Qg and Qgd Low Thermal Resistance Avalanche Rated Pb Free Terminal Plating RoHS Compliant Halogen Free SON 5-mm × 6-mm Plastic Package • 30 V Qg Gate Charge Total (4.5V) 10 nC Qgd Gate Charge Gate to Drain DESCRIPTION RDS(on) Drain to Source On Resistance VGS(th) Threshold Voltage 8 D S 2 7 D S 3 6 D G 4 5 D VGS = 10V 2.9 mΩ 1.3 V Package Media CSD17505Q5A SON 5-mm × 6-mm Plastic Package 13-Inch Reel Qty Ship 2500 Tape and Reel TEXT ADDED FOR SPACING ABSOLUTE MAXIMUM RATINGS VALUE UNIT VDS Drain to Source Voltage 30 V VGS Gate to Source Voltage +20 / –12 V Continuous Drain Current, TC = 25°C 100 A Continuous Drain Current(1) 24 A IDM Pulsed Drain Current, TA = 25°C(2) 153 A PD Power Dissipation(1) 3.2 W TJ, TSTG Operating Junction and Storage Temperature Range –55 to 150 °C EAS Avalanche Energy, single pulse ID = 76A, L = 0.1mH, RG = 25Ω 290 mJ (1) Typical RqJA = 39°C/W on 1-inch2 (6.45-cm2), 2-oz. (0.071mm thick) Cu pad on a 0.06-inch (1.52-mm) thick FR4 PCB. (2) Pulse duration ≤300ms, duty cycle ≤2% D P0093-01 TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING RDS(on) vs VGS TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING GATE CHARGE 16 10 ID = 20A 14 VGS - Gate-to-Source Voltage (V) RDS(on) - On-State Resistance - mΩ mΩ Device ID Top View 1 nC 3.7 TA = 25°C unless otherwise stated The NexFET™ power MOSFET has been designed to minimize losses in power conversion applications. 12 10 8 6 4 TC = 25°C TC = 125ºC 2 0 2.7 VGS = 4.5V TEXT ADDED FOR SPACING ORDERING INFORMATION Point-of-Load Synchronous Buck in Networking, Telecom, and Computing Systems Optimized for Control and Synchronous FET Applications S UNIT Drain to Source Voltage APPLICATIONS • TYPICAL VALUE VDS 0 1 2 3 ID = 20A VDD = 15V 9 8 7 6 5 4 3 2 1 4 5 6 7 VGS - Gate-to- Source Voltage - V 8 9 10 0 0 2 4 6 8 10 12 14 16 18 20 Qg - Gate Charge - nC (nC) 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NexFET is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated CSD17505Q5A SLPS301 – DECEMBER 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Static Characteristics BVDSS Drain to Source Voltage VGS = 0V, IDS = 250mA IDSS Drain to Source Leakage Current VGS = 0V, VDS = 24V IGSS Gate to Source Leakage Current VDS = 0V, VGS = +20/-12V VGS(th) Gate to Source Threshold Voltage VDS = VGS, IDS = 250mA RDS(on) Drain to Source On Resistance gfs Transconductance 30 1 V 1 mA 100 nA 1.3 1.8 V VGS = 4.5V, IDS = 20A 3.7 4.6 mΩ VGS = 10V, IDS = 20A 2.9 3.5 mΩ VDS = 15V, IDS = 20A 82 S Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance RG Series Gate Resistance Qg Gate Charge Total (4.5V) Qgd Gate Charge Gate to Drain Qgs Gate Charge Gate to Source Qg(th) Gate Charge at Vth Qoss Output Charge td(on) Turn On Delay Time tr Rise Time td(off) Turn Off Delay Time tf Fall Time VGS = 0V, VDS = 15V, f = 1MHz VDS = 15V, IDS = 20A VDS = 13.7V, VGS = 0V VDS = 15V, VGS = 4.5V, IDS = 20A,RG = 2Ω 1560 1980 pF 1030 1330 pF 65 85 pF 1 2 Ω 10 13 nC 2.7 nC 3.5 nC 1.9 nC 26 nC 8.3 ns 11.5 ns 15 ns 6.1 ns Diode Characteristics VSD Diode Forward Voltage Qrr Reverse Recovery Charge trr Reverse Recovery Time ISD = 20A, VGS = 0V 0.8 VDD= 13.7V, IF = 20A, di/dt = 300A/ms 1 V 30 nC 28 ns THERMAL CHARACTERISTICS (TA = 25°C unless otherwise stated) PARAMETER (1) RqJC Thermal Resistance Junction to Case RqJA Thermal Resistance Junction to Ambient (1) (2) (1) (2) 2 MIN TYP MAX UNIT 1.3 °C/W 50 °C/W RqJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RqJC is specified by design, whereas RqJA is determined by the user’s board design. Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD17505Q5A CSD17505Q5A www.ti.com GATE SLPS301 – DECEMBER 2010 GATE Source N-Chan 5x6 QFN TTA MIN Rev3 N-Chan 5x6 QFN TTA MAX Rev3 Max RqJA = 50°C/W when mounted on 1 inch2 (6.45 cm2) of 2oz. (0.071-mm thick) Cu. Source Max RqJA = 120°C/W when mounted on a minimum pad area of 2-oz. (0.071-mm thick) Cu. DRAIN DRAIN M0137-02 M0137-01 TYPICAL MOSFET CHARACTERISTICS ZqJA - Normalized Thermal Impedance (TA = 25°C unless otherwise stated) 0.5 0.3 0.1 0.05 Duty Cycle = t1/t2 0.02 0.01 P t1 Single Pulse t2 Typical RqJA = 98°C/W (min Cu) TJ = P ´ ZqJA ´ RqJA Figure 1. Transient Thermal Impedance Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD17505Q5A 3 CSD17505Q5A SLPS301 – DECEMBER 2010 www.ti.com TYPICAL MOSFET CHARACTERISTICS (continued) (TA = 25°C unless otherwise stated) TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 80 100 60 50 40 30 VGS = 3.0V VGS = 4.5V VGS = 6.0V VGS = 10V 20 10 0 0 0.05 0.1 0.15 0.2 0.25 IDS - Drain-to-Source Current - A IDS - Drain-to-Source Current - A VDS = 5V 70 10 1 0.1 0.01 0.001 0.3 TC = 125°C TC = 25°C TC = −55°C 0 0.5 1 VDS - Drain-to-Source Voltage - V Figure 2. Saturation Characteristics 2 2.5 3 3.5 4 Figure 3. Transfer Characteristics TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 10 100 Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd ID = 20A VDD = 15V 9 8 10 C − Capacitance − nF VGS - Gate-to-Source Voltage (V) 1.5 VGS - Gate-to-Source Voltage - V 7 6 5 4 3 1 0.1 2 1 0 0 2 4 6 8 10 12 14 16 18 0.01 20 0 5 10 Qg - Gate Charge - nC (nC) 15 20 25 Figure 4. Gate Charge Figure 5. Capacitance TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 16 2.1 ID = 20A RDS(on) - On-State Resistance - mΩ VGS(th) - Threshold Voltage - V ID = 250µA 1.8 1.5 1.2 0.9 0.6 0.3 0 −75 −25 25 75 125 175 14 12 10 8 6 4 TC = 25°C TC = 125ºC 2 0 0 1 Figure 6. Threshold Voltage vs. Temperature 2 3 4 5 6 7 8 9 10 VGS - Gate-to- Source Voltage - V TC - Case Temperature - ºC 4 30 VDS - Drain-to-Source Voltage - V Figure 7. On-State Resistance vs. Gate-to-Source Voltage Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD17505Q5A CSD17505Q5A www.ti.com SLPS301 – DECEMBER 2010 TYPICAL MOSFET CHARACTERISTICS (continued) (TA = 25°C unless otherwise stated) TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 1.8 ID = 20A VGS = 10V ISD − Source-to-Drain Current - A Normalized On-State Resistance 1.6 100 1.4 1.2 1 0.8 0.6 0.4 0.2 −75 −25 25 75 125 10 1 0.1 0.01 0.001 0.0001 175 TC = 25°C TC = 125°C 0 0.2 Figure 8. Normalized On-State Resistance vs. Temperature 0.6 0.8 1 Figure 9. Typical Diode Forward Voltage TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 1000 I(AV) - Peak Avalanche Current - A 200 100 IDS - Drain-to-Source Current - A 0.4 VSD − Source-to-Drain Voltage - V TC - Case Temperature - ºC 10 1 1ms 10ms 100ms 1s DC 0.1 0.01 Single Pulse, Min Cu Area Typical RthJA = 98ºC/W 0.001 0.01 0.1 1 10 TC = 125°C TC = 25°C 100 10 1 0.01 100 0.1 1 10 t(AV) - Time in Avalanche - ms VDS - Drain-to-Source Voltage - V Figure 10. Maximum Safe Operating Area Figure 11. Single Pulse Unclamped Inductive Switching TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING IDS - Drain- to- Source Current - A 120 100 80 60 40 20 0 −50 −25 0 25 50 75 100 125 150 175 TC - Case Temperature - ºC Figure 12. Maximum Drain Current vs. Temperature Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD17505Q5A 5 CSD17505Q5A SLPS301 – DECEMBER 2010 www.ti.com MECHANICAL DATA Q5A Package Dimensions E2 L K H 2 7 8 8 2 7 1 1 q 3 5 4 6 3 4 D2 6 D1 5 e b L1 Top View Bottom View Side View q A c E1 E Front View M0135-01 DIM 6 MILLIMETERS MIN NOM MAX A 0.90 1.00 1.10 b 0.33 0.41 0.51 c 0.20 0.25 0.34 D1 4.80 4.90 5.00 D2 3.61 3.81 4.02 E 5.90 6.00 6.10 E1 5.70 5.75 5.80 E2 3.38 3.58 3.78 e 1.17 1.27 1.37 H 0.41 0.56 0.71 K 1.10 L 0.51 0.61 0.71 L1 0.06 0.13 0.20 q 0° Submit Documentation Feedback 12° Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD17505Q5A CSD17505Q5A www.ti.com SLPS301 – DECEMBER 2010 Recommended PCB Pattern 4.900 (0.193) 0.605 (0.024) 5 4 0.630 (0.025) 0.620 (0.024) 1.270 (0.050) 4.460 (0.176) 8 1 0.650 (0.026) 3.102 (0.122) 0.700 (0.028) 1.798 (0.071) M0139-01 NOTE: Dimensions are in mm (inches). TEXT ADDED FOR SPACING Stencil Recommendation 0.500 (0.020) 1.235 (0.049) 0.500 (0.020) 1.585 (0.062) 4 5 0.450 (0.018) 1.570 (0.062) 0.620 (0.024) 1.270 (0.050) 1.570 (0.062) 4.260 (0.168) 8 1 PCB Pattern 0.632 (0.025) 3.037 (0.120) 1.088 (0.043) Stencil Opening M0209-01 NOTE: Dimensions are in mm (inches). TEXT ADDED FOR SPACING For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCB Layout Techniques. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD17505Q5A 7 CSD17505Q5A SLPS301 – DECEMBER 2010 www.ti.com Q5A Tape and Reel Information K0 4.00 ±0.10 (See Note 1) 0.30 ±0.05 +0.10 2.00 ±0.05 Ø 1.50 –0.00 1.75 ±0.10 5.50 ±0.05 12.00 ±0.30 B0 R 0.30 MAX A0 8.00 ±0.10 Ø 1.50 MIN R 0.30 TYP A0 = 6.50 ±0.10 B0 = 5.30 ±0.10 K0 = 1.40 ±0.10 M0138-01 NOTES: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2 2. Camber not to exceed 1mm in 100mm, noncumulative over 250mm 3. Material: black static-dissipative polystyrene 4. All dimensions are in mm (unless otherwise specified) 5. A0 and B0 measured on a plane 0.3mm above the bottom of the pocket 8 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD17505Q5A PACKAGE OPTION ADDENDUM www.ti.com 11-Dec-2010 PACKAGING INFORMATION Orderable Device CSD17505Q5A Status (1) ACTIVE Package Type Package Drawing Pins Package Qty 8 2500 Eco Plan TBD (2) Lead/ Ball Finish Call TI MSL Peak Temp (3) Samples (Requires Login) Call TI Purchase Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Dec-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device CSD17505Q5A Package Package Pins Type Drawing SON 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.2 12.4 Pack Materials-Page 1 6.5 B0 (mm) K0 (mm) P1 (mm) 5.3 1.4 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Dec-2010 *All dimensions are nominal Device Package Type CSD17505Q5A SON Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) 8 2500 347.0 342.0 55.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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