CSD16415Q5 SLPS259 – DECEMBER 2011 www.ti.com N-Channel NexFET™ Power MOSFET Check for Samples: CSD16415Q5 FEATURES 1 • • • • • • • 2 PRODUCT SUMMARY Ultralow Qg and Qgd Very Low On-Resistance Low Thermal Resistance Avalanche Rated Pb Free Terminal Plating RoHS Compliant Halogen Free VDS Drain-to-source voltage 25 V Qg Gate charge, total (4.5 V) 21 nC Qgd Gate charge, gate-to-drain rDS(on) Drain-to-source on-resistance VGS(th) Threshold voltage • DESCRIPTION The NexFET™ power MOSFET has been designed to minimize losses in power conversion applications. Top View VGS = 10 V 0.99 mΩ 1.5 V Package Media Qty Ship CSD16415Q5 SON 5-mm × 6-mm plastic package 13-inch (33-cm) reel 2500 Tape and reel ABSOLUTE MAXIMUM RATINGS TA = 25°C unless otherwise stated VALUE UNIT VDS Drain-to-source voltage 25 V VGS Gate-to-source voltage +16/-12 V Continuous drain current, TC = 25°C 100 A Continuous drain current (1) 38 A IDM Pulsed drain current, TA = 25°C (2) 200 A PD Power dissipation (1) 3.2 W –55 to 150 °C 500 mJ ID S 1 8 D TJ, TSTG Operating junction and storage temperature range S 2 7 D EAS Avalanche energy, single-pulse ID = 100 A, L = 0.1 mH, RG = 25 Ω S 3 6 D G 4 5 D D (1) (2) P0094-01 RθJA = 40°C/W on 1-in2 (6.45-cm2) Cu [2 oz. (0.071-mm thick)] on 0.060-inch (1.52-mm) thick FR4 PCB. Pulse duration ≤300 μs, duty cycle ≤2% rDS(ON) vs VGS Gate Charge 12 5 ID = 40A 4.5 ID = 40A VDS = 12.5V 10 4 VG − Gate Voltage − V RDS(on) - On-State Resistance - mΩ mΩ ORDERING INFORMATION Point-of-Load Synchronous Buck Converter for Applications in Networking, Telecom and Computing Systems Optimized for Synchronous FET Applications 3.5 3 2.5 2 1.5 8 6 4 2 1 TC = 25°C TC = 125ºC 0.5 0 nC 1.5 Device APPLICATIONS • 5.2 VGS = 4.5 V 0 0 0 1 2 3 4 5 6 7 VGS - Gate-to- Source Voltage - V 8 9 10 20 30 40 50 60 10 Qg − Gate Charge − nC G003 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NexFET is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated CSD16415Q5 SLPS259 – DECEMBER 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Static Characteristics BVDSS Drain-to-source voltage VGS = 0 V, ID = 250 μA IDSS Drain-to-source leakage current VGS = 0 V, VDS = 20 V IGSS Gate-to-source leakage current VDS = 0 V, VGS = –12 V to 16 V VGS(th) Gate-to-source threshold voltage VDS = VGS, ID = 250 μA rDS(on) Drain-to-source on-resistance gfs Transconductance 25 1.2 V 1 μA 100 nA 1.5 1.9 V VGS = 4.5 V, ID = 40 A 1.5 1.8 mΩ VGS = 10 V, ID = 40 A 0.99 1.15 mΩ VDS = 15 V, ID = 40 A 168 S Dynamic Characteristics CISS Input capacitance COSS Output capacitance CRSS Reverse transfer capacitance 175 230 pF Rg Series gate resistance 1.2 2.4 Ω Qg Gate charge total (4.5 V) 21 29 nC Qgd Gate charge, gate-to-drain 5.2 nC Qgs Gate charge, gate-to-source 8.3 nC Qg(th) Gate charge at Vth 4.8 nC QOSS Output charge 55 nC td(on) Turnon delay time 16.6 ns tr Rise time 30 ns td(off) Turnoff delay time 20 ns tf Fall time 12.7 ns VGS = 0 V, VDS = 12.5 V, f = 1 MHz VDS = 12.5 V, ID = 40 A VDS = 15 V, VGS = 0 V VDS = 12.5 V, VGS = 4.5 V, ID = 40 A RG = 2 Ω 3150 4100 pF 2530 3300 pF Diode Characteristics VSD Diode forward voltage IS = 40 A, VGS = 0 V Qrr Reverse recovery charge VDD = 15 V, IF = 40 A, di/dt = 300 A/μs 0.85 72 1 nC V trr Reverse recovery time VDD = 15 V, IF = 40 A, di/dt = 300 A/μs 45 ns THERMAL CHARACTERISTICS (TA = 25°C unless otherwise stated) PARAMETER MIN R θJC Thermal resistance, junction-to-case (1) R θJA Thermal resistance, junction-to-ambient (1) (1) (2) 2 (2) TYP MAX UNIT 1.1 °C/W 50 °C/W RθJC is determined with the device mounted on a 1-inch (2.54-cm) square, 2-oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm × 3.81-cm), 0.060-inch (1.52-mm) thick FR4 board. RθJC is specified by design, whereas RθJA is determined by the user’s board design. Device mounted on FR4 material with 1 inch2 (6.45 cm2) of 2-oz. (0.071-mm thick) Cu. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): CSD16415Q5 CSD16415Q5 SLPS259 – DECEMBER 2011 www.ti.com GATE GATE Source N-Chan 5x6 QFN TTA MIN Rev3 N-Chan 5x6 QFN TTA MAX Rev3 Max RθJA = 50°C/W when mounted on 1 inch2 (6.45 cm2) of 2-oz. (0.071-mm thick) Cu. Source Max RθJA = 121°C/W when mounted on minimum pad area of 2-oz. (0.071-mm thick) Cu. DRAIN DRAIN M0137-02 M0137-01 Text and Text and Text and Text and Text and br Added for Spacing br br br br Added Added Added Added for for for for Spacing Spacing Spacing Spacing TYPICAL MOSFET CHARACTERISTICS (TA = 25°C unless otherwise stated) ZqJA – Normalized Thermal Impedance 10 1 0.5 0.3 Duty Cycle = t1/t2 0.1 0.1 0.05 0.01 P t1 0.02 0.01 t2 RqJA = 97°C/W (min Cu) TJ = P ´ ZqJA ´ RqJA Single Pulse 0.001 0.001 0.01 0.1 1 10 100 1k tp – Pulse Duration – s G012 Figure 1. Transient Thermal Impedance Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): CSD16415Q5 3 CSD16415Q5 SLPS259 – DECEMBER 2011 www.ti.com TYPICAL MOSFET CHARACTERISTICS (continued) (TA = 25°C unless otherwise stated) TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 100 100 90 80 ID − Drain Current − A ID − Drain Current − A 80 VGS = 3V 70 VGS = 3.5V 60 50 VGS = 4.5V 40 30 VGS = 2.5V 70 50 40 20 10 1.0 1.5 2.0 2.5 TC = −55°C 0 1.5 3.0 VDS − Drain to Source Voltage − V TC = 25°C 30 10 0.5 TC = 125°C 60 20 0 0.0 2.0 2.5 3.0 3.5 VGS − Gate to Source Voltage − V G001 G002 Figure 2. Saturation Characteristics Figure 3. Transfer Characteristics TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 12 9 ID = 40A VDS = 12.5V f = 1MHz VGS = 0V 8 C − Capacitance − nF 10 VG − Gate Voltage − V VDS = 5V 90 VGS = 10V 8 6 4 7 6 COSS = CDS + CGD 5 CISS = CGD + CGS 4 3 2 CRSS = CGD 2 1 0 0 0 10 20 30 40 50 60 Qg − Gate Charge − nC 0 G003 20 Figure 5. Capacitance TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 25 G004 5 ID = 250µA 1.8 RDS(on) - On-State Resistance - mΩ VGS(th) − Threshold Voltage − V 15 Figure 4. Gate Charge 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 −25 25 75 125 175 TC − Case Temperature − °C ID = 40A 4.5 4 3.5 3 2.5 2 1.5 1 TC = 25°C TC = 125ºC 0.5 0 0 1 2 3 4 5 6 7 8 9 10 VGS - Gate-to- Source Voltage - V G005 Figure 6. Threshold Voltage vs. Temperature 4 10 VDS − Drain to Source Voltage − V 2.0 0.0 −75 5 Figure 7. On-Resistance vs. Gate Voltage Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): CSD16415Q5 CSD16415Q5 SLPS259 – DECEMBER 2011 www.ti.com TYPICAL MOSFET CHARACTERISTICS (continued) (TA = 25°C unless otherwise stated) TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 100 1.4 ID = 40A VGS = 10V ISD − Source to Drain Current − A Normalized On-State Resistance 1.6 1.2 1.0 0.8 0.6 0.4 0.2 0.0 −75 10 1 0.1 0.001 25 75 125 175 0.0 0.4 0.6 0.8 1.0 VSD − Source to Drain Voltage − V Figure 8. On-Resistance vs. Temperature Figure 9. Typical Diode Forward Voltage TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING G008 1k I(AV) − Peak Avalanche Current − A ID − Drain Current − A 0.2 G007 1k 100 1ms 10 10ms 100ms Area Limited by RDS(on) 1s 0.1 0.01 0.01 TC = 25°C 0.01 0.0001 −25 TC − Case Temperature − °C 1 TC = 125°C Single Pulse RqJA = 97°C/W (min Cu) 0.1 DC 1 10 10 TC = 125°C 1 0.001 100 VDS − Drain To Source Voltage − V TC = 25°C 100 0.01 0.1 1 10 100 t(AV) − Time in Avalanche − ms G009 Figure 10. Maximum Safe Operating Area G010 Figure 11. Single-Pulse Unclamped Inductive Switching TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 120 ID − Drain Current − A 100 80 60 40 20 0 −50 −25 0 25 50 75 100 125 TC − Case Temperature − °C 150 175 G011 Figure 12. Maximum Drain Current vs. Temperature Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): CSD16415Q5 5 CSD16415Q5 SLPS259 – DECEMBER 2011 www.ti.com MECHANICAL DATA Q5 Package Dimensions K L L c1 E1 E2 b D2 4 4 5 5 e 3 6 3 6 E D1 7 7 2 2 8 8 1 1 q Top View Bottom View Side View c E1 A q Front View M0140-01 DIM MILLIMETERS MAX MIN MAX A 0.950 1.050 0.037 0.039 b 0.360 0.460 0.014 0.018 c 0.150 0.250 0.006 0.010 c1 0.150 0.250 0.006 0.010 D1 4.900 5.100 0.193 0.201 D2 4.320 4.520 0.170 0.178 E 4.900 5.100 0.193 0.201 E1 5.900 6.100 0.232 0.240 E2 3.920 4.12 0.154 e 6 INCHES MIN 1.27 TYP K 0.760 L 0.510 θ 0.00 0.162 0.050 0.030 0.710 Submit Documentation Feedback 0.020 0.028 Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): CSD16415Q5 CSD16415Q5 SLPS259 – DECEMBER 2011 www.ti.com Figure 13. Recommended PCB Pattern DIM F1 F7 F3 8 1 F2 F11 F5 F9 5 4 F6 MILLIMETERS INCHES MIN MAX MIN MAX F1 6.205 6.305 0.244 0.248 F2 4.460 4.560 0.176 0.180 F3 4.460 4.560 0.176 0.180 F4 0.650 0.700 0.026 0.028 F5 0.620 0.670 0.024 0.026 F6 0.630 0.680 0.025 0.027 F7 0.700 0.800 0.028 0.031 F8 0.650 0.700 0.026 0.028 F9 0.620 0.670 0.024 0.026 F10 4.900 5.000 0.193 0.197 F11 4.460 4.560 0.176 0.180 F8 F4 F10 M0139-01 For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCB Layout Techniques. K0 4.00 ±0.10 (See Note 1) 0.30 ±0.05 2.00 ±0.05 +0.10 –0.00 12.00 ±0.30 Ø 1.50 1.75 ±0.10 Q5 Tape and Reel Information 5.50 ±0.05 B0 R 0.30 MAX A0 8.00 ±0.10 Ø 1.50 MIN A0 = 6.50 ±0.10 B0 = 5.30 ±0.10 K0 = 1.40 ±0.10 R 0.30 TYP M0138-01 Notes: 1. 10 sprocket hole pitch cumulative tolerance ±0.2 2. Camber not to exceed 1 mm IN 100 mm, noncumulative over 250 mm 3. Material:black static dissipative polystyrene 4. All dimensions are in mm (unless otherwise specified) 5. A0 and B0 measured on a plane 0.3 mm above the bottom of the pocket 6. MSL1 260°C (IR and Convection) PbF Reflow Compatible Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): CSD16415Q5 7 PACKAGE OPTION ADDENDUM www.ti.com 24-Dec-2011 PACKAGING INFORMATION Orderable Device CSD16415Q5 Status (1) ACTIVE Package Type Package Drawing SON DQH Pins Package Qty 8 2500 Eco Plan (2) Pb-Free (RoHS Exempt) Lead/ Ball Finish CU SN MSL Peak Temp (3) Samples (Requires Login) Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device CSD16415Q5 Package Package Pins Type Drawing SON DQH 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.8 Pack Materials-Page 1 6.5 B0 (mm) K0 (mm) P1 (mm) 5.3 1.4 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CSD16415Q5 SON DQH 8 2500 335.0 335.0 32.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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