Very Wide Input Voltage Range, Off-line Flyback Switching Power Supply

AN1327/D
Very Wide Input Voltage
Range, Off-Line Flyback
Switching Power Supply
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APPLICATION NOTE
Added to this are those industrial companies which may not
only have their products reside on residential power systems
but also have the varied international industrial power
systems. This means that a single product family might have
to operate from an input voltage of 90 to 600 VAC, well
beyond the residential limits of 90 to 270 VAC.
This paper reviews one method of enabling a
discontinuous−mode flyback converter to operate beyond
its traditional range of input voltage of 3:1 to a range of more
than 6.6:1 without affecting the reliability of its operation.
This is done by changing its mode of operation and the use
of recently available power MOSFETs with breakdown
voltage ratings of 1,200 V.
One of the many problems besetting the power supply
designer today is being able to design a switching power
supply that is able to operate in all the power systems within
their international marketplaces. Forward−mode switching
power supplies typically operate over a single power
system’s range of voltage, that is, 90 to 130 VAC or
200 to 270 VAC. Boost−mode converters can just make the
range of 90 to 270 VAC. Any higher input voltages would
then require a different design.
This leads companies to create products targeted at
specific marketplaces, which can be costly, or to have their
customers arrange jumpers to accommodate their power
system which can be annoying or lead to costly errors.
Figure 1. The Wide Input Range Flyback Power Supply Demonstration Board
This document may contain references to devices which are
no longer offered. Please contact your ON Semiconductor
representative for information on possible replacement devices.
© Semiconductor Components Industries, LLC, 2012
December, 2012 − Rev. 2
1
Publication Order Number:
AN1327/D
AN1327/D
A Summary of the Operation of Fixed Frequency
Flyback Converters
The most common topology for those applications less
than 150 W has been the fixed frequency, current−mode
controlled, flyback converter. Its block diagram can be seen
in Figure 2.
+Vin(DC)
FLYBACK
TRANSFORMER
STARTUP
CKT
OUTPUT
RECTIFIER
AND
FILTER
STAGE
OUTPUT
VOLTAGE
OSCILLATOR
VOLTAGE
REF
CLOCK
PEAK CURRENT
COMPARATOR
S
+
POWER
SWITCH
Q
R
-
VOLTAGE
FEEDBACK
CIRCUIT
OUTPUT
DRIVER
ERROR
AMP
LEADING EDGE
SPIKE
SUPPRESSOR
CURRENT
SENSE
ELEMENT
FEEDBACK VOLTAGE
INPUT RETURN
Figure 2. Block Diagram of a Fixed Frequency Current−Mode, Flyback Converter
Here a fixed frequency oscillator initiates a power switch
conduction period which is terminated by either the current
within the power switch reaching a predetermined limit as
set by the error amplifier or the oscillator terminating the
period and initiating the next power switch conduction
period.
A representative flyback converter can be seen in
Figure 3.
T
ipk +
D
Vin
Vin · Ton
Lpri
(eq. 1)
The slope of the current ramp is Vin/Lpri.
The flyback topology, as with all boost−mode converters,
operate under the principle of storing energy within the core
material of the transformer. The energy stored during each
conduction period is given by:
Vout
+
−
The power switch essentially places the primary
inductance of the flyback transformer across the input
voltage source when it is turned on. The secondary is
disconnected because the output rectifier (D) is reverse
biased. The primary winding’s current takes the form of a
linear ramp starting from zero amps and whose peak value
is given by:
Q
CONTROL
Esto +
Ipri
2
Lpri · i pk
2
(eq. 2)
To meet the short−term steady−state power demands of
the load(s), the following relationship must be met:
Figure 3. A Simplified Schematic of a
Flyback Converter
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AN1327/D
Pout v
2
fop · Lpri · i pk
2
The shortcoming arises in the output drivers of the typical
current−mode control IC and the power switch. Typically a
power MOSFET is used as the power switch in most modern
flyback power supplies. At high input voltages, the on−time
of the power switch becomes so short (300 − 600 nS) that
the output driver cannot source enough instantaneous
current to drive the MOSFET into a saturated condition
before turning it back off. The effect is the power switch
operates in the linear conduction mode during these short
“on’’ pulses. This causes a drastic drop in power switch
operating efficiency and jeopardizes the power supply’s
reliability.
(eq. 3)
In reality, for any one output power, the current−mode
controller strives to maintain a constant value for Ipk over the
entire range of input voltages as visualized in Figure 4.
PRIMARY CURRENT
HI INPUT VOLTAGE
LOW INPUT
VOLTAGE
The New Method of Control
By a very simple modification to the traditional fixed
frequency current−mode controlled flyback converter
design, one can greatly extend its operational input voltage
range. The modifications make the control method one of
variable on−time, and variable frequency. Figure 5
illustrates the newly added and redefined functional blocks
of this new method of control.
Ipk
TIME
Figure 4. Peak Currents at Differing Input Voltages
+Vin(DC)
FLYBACK
TRANSFORMER
STARTUP
CKT
VOLTAGE
TRANSLATOR
VOLTAGE
REF
OUTPUT
VOLTAGE
CONTROL
PEAK
CURRENT
DETECTOR
VCO
CLOCK
POWER
SWITCH
Q
R
VOLTAGE
FEEDBACK
CIRCUIT
OUTPUT
DRIVER
S
+
-
OUTPUT
RECTIFIER
AND
FILTER
STAGE
ERROR
AMP
CURRENT
RAMP
TIME DELAY
CURRENT
SENSE
ELEMENT
FEEDBACK VOLTAGE
INPUT RETURN
Figure 5. Block Diagram of the Wide Input Range, Flyback Converter
entire output voltage swing. The other new block is really a
redefinition of an old familiar function − the leading edge
spike filter from the current sensing element. Here, the
formerly annoying parasitic of time lag serves an important
function within the control algorithm. It now delays the
actual current ramp prior to being sensed by the control IC.
It allows the actual peak current to increase with increasing
input voltages while the controller sees a lowering peak
current needed by this control strategy. This will be
discussed later.
A VCO (voltage−controlled oscillator) is created by
removing the timing capacitor’s charging circuit from a
fixed voltage or current source and placing it under the
control of the error voltage. In the design example shown
later, it means simply removing the timing resistor from the
voltage reference and wiring it to a variable voltage created
by the output of the error amplifier. A voltage translator is
placed between the output of the error amplifier and the
control input to the VCO. It consists of a simple biased 3.3 V
zener diode so that the error amplifier may make use of its
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AN1327/D
fixed−frequency flyback converter. This will allow us to
determine the appropriate value for the primary inductance.
In the sample design, the frequency of operation at the
highest input voltage will drop to one−half from that at the
lowest input voltage. Equation 4 then dictates:
The ultimate goal of the new control methodology is to
force the on−time of the power switch to be greater than this
minimum effective on−time over the power supply’s entire
line/load operating range. Its operation can be best
understood by examining equation 3. The error
amplifier/VCO section of the circuit lowers the operating
frequency as the input voltage is increased. This requires the
energy stored per conduction period to increase to meet the
short−term power requirement of the output. This is done by
extending the on−time of the power switch. If the key
component parameters such as maximum operating flux
density (Bmax) of the transformer, the avalanche ratings of
the diodes and power switch, and the current ratings of the
output rectifiers are adequate, then no degradation in the
reliable operation of the supply is experienced.
Its operation can be better defined by rearranging
equation 3 and neglecting any power loss due to the
inefficiency of the supply one gets:
ipk +
Ǹ
2 Pout
Lpri · f(f(Ve))
ipk(hi) [ Ǹ2 ipk(lo)
If the desired maximum operating flux density (Bmax) is
one−half the core material’s saturation flux density at 100°C
and at the high input line, then the operating flux density at
the low input voltage should be:
Bmax(lo) [
Ǹ
2 Pout · Lpri
f(f(Ve))
Bsat(min)
2 Ǹ2
(eq. 7)
For most common ferrite materials such as 3C8, N27, or
F, the operating flux density at low line will be at
approximately 1,300 gauss. The Bmax at the high input
voltage will be no more than one−half the saturation flux
density at 100°C.
The inductance can now be calculated by using equation 1
at the low input voltage, and an air gap calculated using any
one of the common methods.
It is important to determine the secondary inductance such
that the core’s energy can be emptied as close to 50 percent
duty−cycle (1/fop(hi)) as possible. This will minimize the
RMS currents to their lowest possible point over the entire
operating range. The output peak current at any operating
point is described as:
(eq. 4)
where f(f(Ve)) is the controlled frequency of the power supply.
As one can see, the peak current is inversely proportional
to the square root of the frequency of operation, since all the
other terms are fixed in the short−term operation and by the
circuit design.
By substituting equation 1 into equation 4 one further gets:
ton + 1 ·
Vin
(eq. 6)
ipk(out) [ 2 · Iout(av) · Tdisch · fop
(eq. 5)
(eq. 8)
This would describe both the peak currents flowing
through the output rectifiers and the peak ripple currents
flowing into and out of the output filter capacitors. Within
the sample design with one ampere rated outputs, at low line
the peak−to−peak rectifier currents would be four times the
average output current. At the high line, the peak−to−peak
currents would be eight times the average output current for
the rated output current.
There are more unknowns than there are independent
equations, but at the low input line voltage and at the rated
output load, one can solve equation 5. The input voltage is
known to be 125 VDC (90 VAC), the frequency will be at its
highest point as designated by the designer, the on−time will
be one−half of the entire operating period and the peak
current will be calculated as it is in a common
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AN1327/D
The Wide−Range Flyback Converter Demonstration Board
The wide−input range off−line flyback converter described has the following maximum and performance ratings.
Output Power:
17 Watts
Outputs:
+5.0 Vdc @ 1.0 Amp Max
+12 Vdc @ 1.0 Amp Max
Input Voltage Range:
90 VRMS − 600 VRMS
Maximum Input Voltage:
675 VRMS
J1
D1
C2
L1
R1
R2
R9
D3
+
H2
C1
+
D4
C3 C4
C5
R5
R16
D5
U1
R12
C7
C8
D10
R6
+
T1
C11
D8
D9
+
C12
Q1
G
C10
WIDE INPUT RANGE
FLYBACK POWER SUPPLY
ITC109B
R7
C13
1
D6
R10
R8
C6
C9
CAUTION
HIGH VOLTAGES
INDUSTRIAL
TECHNOLOGY CENTER
R11
R4
D2
H1
GND
R3
C16
R13
R14
R15
+
C17
C15
D7
R20
U2
Figure 6. Printed Circuit Board Layout
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5
R17
+
C14
+
+
R18
R19
J2
O/P + 12V + 5V
U3
R21
GND
AN1327/D
Table 1. Parts List
Designator
Quantity
Value/Rating
C1, C4
2
0.1 mF, 1.0 kV
Capacitor, Ceramic
Description
C2, C3
2
0.0047 mF, 3.0 kV
Capacitor, Ceramic
C5, C6
2
100 mF, 450 V
Capacitor, Electrolytic
C7
1
220 pF, 50 V
Capacitor, Ceramic
C8
1
1000 pF, 50 kV
Capacitor, Ceramic
C9
1
1000 pF, 1.0 kV
Capacitor, Ceramic
C10
1
10 mF, 25 V
Capacitor, Tantalum
C11, C12
2
100 mF, 20 V
Capacitor, Tantalum
C13, 14
2
100 mF, 10 V
Capacitor, Tantalum
C15
1
1500 pF, 50 V
Capacitor, Ceramic
C16
1
1.3 mF, 50 V
Capacitor, Mylar
C17
1
0.22 mF, 35 V
Capacitor, Ceramic
D1−D4
4
1.0 A, 1.0 kV
Diode, 1N4007
D5
1
3.3 V, 500 mW
Zener Diode, 1N5226B
D6
1
1.0 A, 1.0 kV
Diode, UF, MUR1100E
D7
1
4.0 A, 300 V
Diode, UF, MUR430E
D8
1
3.0 A, 70 V
Diode, Schottky, MBR370
Diode, UF, MUR130E
D9
1
1.0 A, 300 V
D10
1
−
Diode, SIGNAL, 1N4148
J1
1
−
Connector
J2
1
−
Connector
L1
1
−
Coil Craft P/N E3493
Q1
1
3.0 A, 1.2 kV
R1−R4
4
470 kW, 1/2 W
Resistor
R5−R9
5
82 kW, 1/2 W
Resistor
R10
1
1.8 kW, 1/4 W
Resistor
R11
1
27 kW, 1/4 W
Resistor
R12
1
10 W, 1/4 W
Resistor
R13
1
1.0 kW, 1/4 W
Resistor
R14
1
1.2 W, 1/2 W
Resistor
R15
1
680 W, 1/4 W
Resistor
R16
1
100 kW, 1/2 W
Resistor
R17
1
7.5 kW, 1/4 W
Resistor
R18
1
3.57 kW, 1/4 W
Resistor
R19
1
32.4 kW, 1/4 W
Resistor
R20
1
120 W, 1/4 W
Resistor
R21
1
2.49 kW, 1/4 W
Resistor
T1
1
Transformer
U1
1
−
IC, UC3845B
U2
1
−
Optoisolator, MOC8102
U3
1
−
IC, TL431CLP
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MOSFET, MTB3N120E
Cramer, CSM, 3015−027
AN1327/D
L1
H1
C1
90 VAC− 0.1
600 VAC 1 kV
D1−D4
1N4007s
C4
0.1
1 kV
L1
+Vin
C6
100 mF
450 V
H2
C3
0.0047
3 kV
EARTH
GND
C2
0.0047
3 kV
+
C5
100 mF
450 V
+
R4
470 k
1/2 W
R3
470 k
1/2 W
R2
470 k
1/2 W
R1
470 k
1/2 W
INPUT GND
Figure 7. AC Input/Filter Circuit Section
T1
D9
MUR430
C11
D8
100 mF
MBR370
10 V
+Vin
Vaux
R9
82 k, 1/2 W
R8
100 mF
20 V
R7
R6
R5
D10
R16
100 k
1/2 W
10 mF
25 V
+
LL
R11
1.8 k
D5
3.3 V
6
4
1
C7
220 pF
C9
C13
MUR130
MUR1100
D6
D7
7
UC3845BN
R10
27 k
1 nF
3 kV
2
U2
1/2
MOC8102
5
3
MTB3N120E
R12 10 W
+
C8
1000 pF
C14
Vaux
R14
1.2 W
1/2 W
INPUT GND
Figure 8. DC/DC Converter Circuit Section
7
C12
U2
MOC8102
C17
2.2 nF
Q1
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+12V
+
+5V
+
R13
1k
R15
680 W
+
R20
120 W
C15
1.5 nF
R19
32.4 k
1.3 mF 7.5 k
U3
TL431
C16
R17
R21
2.49 k
GND
AN1327/D
Design of the Wide Input Range Flyback
Converter
Npri + 1000
Predesign Considerations
+ 1000
Output Power:
Po
= (5.0 V)(1.0 A) + (12 V)(1.0 A) = 17 Watts
DC Input Voltages:
Vin(low) = 1.414 · Vin−ac(low)
= 1.414(90 VAC) = 127 VDC
Vin(hi)
= 1.414 · Vin(hi)
= 1.414(600 VAC) = 854 VDC
Maximum Average Input:
Current:
Iin−av(max) = Pout/(eff · Vin(min))
= (17 W)/(0.8)(127 VDC)
= 167 mA
N sec +
N() 5) +
(eq. 9)
(eq. 10)
Co [
The minimum length of the airgap for the core is then:
+
Io(max)
fest(min) · Vripple(max)
(1 A)
[
+ 142 mF
(70 kHz)(0.1 V)
2
8
0.4 p Lpri i pk10
AC B2
max
(eq. 14)
Sizing the Output Filter Capacitors
Since this is a variable frequency system, all the
calculations for the value of the output filter capacitors will
be done at the lowest frequency since the ripple voltage will
be greatest at this frequency. Since capacitor values are
determined by the output current, and both the +5.0 V and
the +12 V outputs have the same maximum output current
rating, their capacitance values will be equal.
Using equation 6, one gets the maximum operating flux
density at the low input voltage of:
Ig +
(5 V ) 0.5 V)(8T)
+ 4 turns
(12.9 V)
The amount of error between the actual transformer
output voltages and the required output voltages are:
+5 V:
+5.0 V
+12 V: +10.1 V after the rectifier drop.
Add one turn (9 turns) to the +12 V outputs. The resulting
output voltage, including the rectifier drop is 11.5 volts.
The physical winding of the transformer is extremely
important (refer to Figure 9). First, there are the creepage
requirements (space between windings over surface) of the
safety agencies. Secondly, with 850 volts across the primary
winding at the high input voltage, the interlayer voltage
could cause arcing between layers of the primary winding.
A layer of Mylar tape must be placed between adjacent
layers of the primary. The final transformer construction is
given below.
0.5(127 V)
+
+ 553 mH
(0.82 A)(140 kHz)
3500 G
+ 1237 G
2 Ǹ2
(eq. 13)
The auxiliary winding to power the control IC is also
+12 V, so it will have the same number of turns.
The number of turns needed for the +5.0 volt winding is:
Designing the Transformer
After reviewing the core sizing information provided by
the various core manufacturers, it is decided that an E−E
core of about 1.2 inches (30.5 mm) on a side will adequately
fit the windings and insulation needed by this application.
This corresponds to a Magnetics Inc. part number
43007−EC core (or Philips 782E272 (E 30)). The core
material should be a Magnetics P, F or N material or Philips
3C85 or 3F3 material. A Magnetics part number
F−43007−EC will be used.
Calculating the primary inductance needed for this
application:
Bmax(lo) [
(Vout ) Vfwd)(1 * ē max) · Npri
ē max · Vin(min)
(12 V ) 0.9 V)(0.5)(74T)
+
+ 7.5 turns, make 8 turns
(0.5)(127 VDC)
Nominal Peak Current:
Ipk
= 5.5 · Pout/Vin(min)
= 5.5(17 W)/127 V = 0.74 Amps
The desired maximum frequency of operation is 140 kHz.
ē max Vin(min)
Ipkf max
Ǹ
(eq. 12)
0.553 mH
+ 74.4 turns, make 74 turns
100 mH
The number of turns needed by the +12 V secondary, and
assuming ultrafast recovery rectifier is:
NOTE: The primary winding’s AWG should be #30 AWG.
Lpri +
ǸLApriL
(eq. 15)
Make the output capacitors two 100 mF capacitors placed
in parallel for each output (C11 and C13, C13 and C14).
(eq. 11)
0.4 p (553 mH)(0.82 A)2 108
+ 0.046 cm or 18 mils
(0.6 cm2)(1300 G)2
Designing the Voltage Feedback Section
The internal error amplifier in the UC3845 (U1) will not
be used. The inverting input pin should be grounded to
ensure that the output will be always high. The error
amplifier function will be provided by a TL431 (U3) on the
An airgap that produces an AL of 100 mH/1000T is larger
than this, so that is what is used.
The number of turns needed to produce the required
primary inductance is:
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AN1327/D
secondary being connected to the primary side via an
optoisolator, the MOC8102 (U2).
The collector of the MOC8102 optoisolator represents the
key control node for power supply. The value of the voltage
at this node sets both the frequency of operation and the peak
current flowing through the power switch during each cycle.
The collector of the U2 will be connected to the
compensation pin of the UC3845 which will directly set the
peak current. Then a 3.3 volt zener diode (D5) will elevate
this voltage to a higher voltage to set the frequency of the
voltage controlled oscillator. Choosing the maximum
current from the output of the MOC8102 optoisolator to be
5.0 mA, an external resistor (R11) from the VCC of the IC to
the VCO input is needed. Its value is set when the
MOC8102’s output is at saturation and is:
R11 + (12 V * 3.3 V)ń5 mA + 1740 ohms, make 1.8 k
(eq. 16)
The MOC8102 has a Ctrr of 100 percent. That makes the
LED current 6.0 mA (5.0 mA from R10, 1.0 mA from pin 1
of U1). A margin of 30 percent should be added for
variations in the gain of the optoisolator. That would make
the LED current 8.0 mA.
The value of the current limiting resistor for the
optoisolator LED (R20) is:
R20 + [5 V * (VU3 ) VLED)]ń8 mA
+ 138 ohms, make 120 k
(eq. 17)
BOARDER TAPE
5 mm
+5 V AND +12 V WINDINGS
(SELF RATED)
3 LAYERS
TAPE EA.
+12 V WINDING (Vaux)
KAPTON INSULATED
1 LAYER
TAPE
PRIMARY
BOARDER TAPE
4 mm
Figure 9. Construction of the Transformer
be at its highest and the duty cycle will be 50 percent. The
VCO control node will be at its highest linear value which
is 7.7 volts.
One starts by selecting the size of the timing capacitor (Ct,
C7). This is done by referring to UC3845 data sheet,
Figure 2 “deadtime vs. frequency.’’ It is desired that the
deadtime be a minimum, since the UC3845 is already 50
percent duty cycle limited. At an oscillator frequency of
280 kHz, which is divided by 2 for an operating frequency
of 140 kHz, the largest capacitor that yields the least
deadtime is approximately 220 pF.
Using Figure 1 from the UC3845 data sheet “Timing
Resistor vs. Oscillator Frequency’’ and knowing the VCO
control voltage will be 2.2 V higher than the +5.0 V
reference assumed by the chart, one can “scale’’ Figure 1 so
that the same charging current is flowing through the timing
resistor (R10) but from the higher voltage source. So by
multiplying the ratio of 7.7 V divided by 5.0 V by the value
of the resultant resistor value from Figure 1, one gets the
approximate final resistor value. Figure 1 results in a value
of 18 k ohms for the timing resistor for a timing capacitor of
220 pF. The final value of R10 is then:
The lower resistor of the voltage sensing network (R21)
is set by assuming a sense current. One milliamp yields 1.0 k
ohm per volt, which is easy. So:
R21 + VrefńIsense + 2.5 Vń1 mA
(eq. 18)
+ 2.5 k make 2.49 k 1%
Splitting the output voltage sensing between more than
one output will improve the cross regulation of all the
outputs. The +5.0 V output is usually connected to MCUs
which are voltage sensitive. Usually, the loads connected to
the +12 V output are less susceptible to voltage variations.
Select the proportion of sense current to be 70 percent from
the +5.0 V and 30 percent from the +12 V outputs. The value
of the +5.0 V sense resistor (R18) is:
R18 +
(5 V * 2.5 V)
+ 3.57 k, 1%
0.7(1 mA)
(eq. 19)
The +12 V sense resistor (R19) is:
R19 +
(12.2 V * 2.5 V)
+ 32.3 k
0.3(1 mA)
(eq. 20)
make it 32.4 k, 1%
Designing the Voltage Controlled Oscillator
One designs the VCO component values when the power
supply is at the lowest input voltage. Here the frequency will
Rt +
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7.7 V (18 k)
+ 27.7 k make 27 k
5.0 V
(eq. 21)
AN1327/D
The lowest frequency that the power supply is capable
occurs when the error amplifier is at its lowest output which
is about 0.8 V. The lowest operating frequency would then
be:
flow +
Rst +
PD +
The Current Sense Resistor
Determining the value of the current sense resistor (R14),
one uses the peak current determined in the predesign
considerations and at the minimum input voltage. To keep
the current−mode operation linear, the peak currents must be
kept less than 1.0 volt in normal operation. So to find the
current sensing resistor (R14) value:
The Voltage Feedback Loop Compensation
The output that is most heavily sensed is the +5.0 V
output, so that will be the output that is used as the reference
input for the feedback loop analysis.
The output filter pole at light load (0.1 A) of this output is:
(eq. 23)
1
ffp() 5) +
2pRoCo
(eq. 27)
1
+
+ 15.9 Hz
2p(50 W)(200 mF)
The Current Ramp Time Delay Circuit
This circuit is very important to the operation of the
overall circuit. Aside from providing the usual spike
elimination to the current comparator, it also provides a time
delay function from the current sense resistor to the input to
the current comparator. Although a wide range of resistor
and capacitor values will work, some minimum time delay
is required to avoid instabilities due to too short an on−time
at the high range of input voltages.
One starts by selecting a value for the capacitor (C8). The
common range of values for this function are 470 pF to
1000 pF. For this particular application a value of 1,000 pF
was selected for C8. A good estimate of the time delay
needed would be approximately 0.7 mS. This is also the
approximate minimum on−time at the high input voltage.
The value of the resistor (R15) would then be:
(700 nS)
+ 700 W make 680 ohms
(1000 pF)
(Vin(max))2
(854)2
+
+ 1.66 W (eq. 26)
Rst
4(110 k)
This makes the power dissipated in each resistor 0.41 watts.
This is a little high, so place five resistors (R5−R9) each
having a value of 82 k ohms and each will dissipate 0.36
watts which is below a 25 percent derating point.
1.0 V
V
Rsc + sc +
+ 1.35 W make 1.2 ohms, 1ń2 W
Ipk
0.74 A
+
(eq. 25)
Each resistor is then 110 k.
The power dissipated is:
(0.8 V ) 3.3 V)
· 140 kHz + 75 kHz (eq. 22)
7.7 V
T
Rf + d
Cf
Vin(min)
127 V
+
+ 423 k
Istart(min)
0.3 mA
The +5.0 V output filter pole at rated load (1.0 A) is
159 Hz.
The zero contributed by the ESR of the output filter
capacitors will be approximately 15 kHz.
The gain exhibited by the open loop power supply at the
high input voltage will be:
ADC +
(Vin * Vout)2 N sec
Vin · Ve · Npri
(854 V * 5 V)2 4T
+
+ 48.3
(854 V)(1)(70T)
(eq. 28)
or GDC = 33.6 dB. This is the highest DC gain that will be
exhibited by the open loop power supply and will reduce to
16.5 dB at the low input line. This will reduce the bandwidth
of the closed loop power supply by almost a decade when
going from high input line to low input line. This is
marginally acceptable. By setting the widest allowable
bandwidth at the high input line, then one can be assured of
a reasonable bandwidth at the low input line. The maximum
recommended bandwidth is approximately:
(eq. 24)
The Start−Up Circuit
A passive start−up circuit is used. That is, resistors will
bring current from the input line to start−up the control IC.
It is desired that a “hiccup’’ mode of overcurrent protection
be implemented, which means that the amount of current
that flows through the start−up circuit must be less than the
current needed to run the control IC. The UC3845B uses
approximately 10 mA during normal operation and draws
between 0.3 to 0.5 mA in standby. The start−up energy will
be stored in the 10 mF filter capacitor.
To meet the breakdown rating of the half watt resistors
(approximately 250 V), a minimum of four resistors in
series will be needed to accommodate the 854 VDC
maximum input voltage. The total start−up resistance will
be:
fxo +
fsw(min)
75 kHz
+
+ 15 kHz
5
5
(eq. 29)
The gain needed to be contributed by the error amplifier
to achieve this bandwidth is calculated at rated load because
that will yield the widest bandwidth condition which is:
ǒffxofp Ǔ * GDC
15 kHz
Ǔ * 33.6 dB + 5.9 dB
Gxo + 20 Log ǒ
159 Hz
Gxo + 20 Log
The gain in absolute terms (needed later) is:
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10
(eq. 30)
AN1327/D
Axo + 10
ǒG20xoǓ
ǒ Ǔ
fc + fsw · 10 Att
40
(eq. 31)
Axo + 10(5.9 dBń20) + 1.97
where Att is the attenuation needed at the switching
frequency in negative dB.
Now the compensating circuit elements can be calculated.
1
2 · p · Axo · R19 · fxo
1
+
2 · p (1.97)(3.57 k)(15 kHz)
ǒ
(eq. 32)
+ (1.97)(3.57 k) + 7033 ohms, make R20 7.5 k
The compensating zero must be placed at or below the
light load filter pole.
1
2 · p · R20 · fze
1
+
+ 1.3 mF
2 · p(7.5 k)(15.9 Hz)
L+
(eq. 33)
C+
+
(50)(0.707)
+ 598 mH
p (18.8 kHz)
(eq. 37)
1
1
+
(2pfc)2L
[2p (18.8 kHz)]2(598 mH)
Post Design Modifications
It was found that the control circuitry drew more quiescent
current than anticipated. That made the start−up voltage
higher than desired. It was also found that the optoisolator’s
dark collector leakage current and the timing capacitor’s
leakage current were responsible for this behavior. D10 and
C17 which isolated these elements behind a low reverse
leakage diode during the start−up process were added.
Toff · Iin * av(max)
(5 mS)(0.167 A)
[
+ 42 mF
20 V
p · fc
Coilcraft offers off−the−shelf common−mode filter
chokes (transformers) and the part number closest to this
value is E3493. With this filter design a minimum of −40 dB
between the frequencies of 500 kHz and 10 MHz can be
expected. If later during the EMI testing stage, additional
filtering is needed, a third order to the filter design will be
added by using a differential−mode filter.
The Bulk Input Filter Capacitor
The approximate value of capacitance needed is:
Vripple
RL · z
+ 0.1 mF
Design of the Input Rectifier/Filter Circuit
This circuit provides EMI filtering, rectification and bulk
energy storage for the power supply. It has some severe
operating conditions it must withstand, such as very high AC
and DC voltages at the high input voltage range. High
voltage ratings for the rectifiers and bulk filter capacitors are
needed. Also large creepage distances, the distance an arc
must travel over a surface, must be maintained to meet the
requirements of the safety regulatory agencies.
1N4007’s will be used as the input rectifiers because of
their 1000 V reverse voltage ratings and the average input
current of the power supply is less than 1.0 amp.
Cin [
(eq. 36)
A damping factor of 0.707 or greater is good and it
provides a −3.0 dB attenuation at the corner frequency and
does not produce ringing in the filter reactances. Assume
that the input line impedance is 50 ohms since the regulatory
agencies use a LISN (Line Impedance Stabilization
Network) which makes the line impedance equal this value.
Calculating the values needed in the common−mode
inductor (L1) and “X’’ capacitors (C1 and C4):
R17 + Axo · R18
C16 +
Ǔ
fc + (75 kHz) 10 * 24 + 18.8 kHz
40
C15 +
+ 1500 pF
(eq. 35)
(eq. 34)
Performance of the Sample Design
Output Regulation:
+5.0 V
−1.2%
+12 V
−1.5%
make this two 100 mF, 450 VDC capacitors in series (C5 and
C6).
Input Regulation:
+5.0 V
+0.4%
+12 V
+0.5%
The EMI Filter
A second order, common−mode filter is used. The lowest
frequency of operation occurs at the low input voltages. The
estimated lowest frequency of operation is 75 kHz. This is
important to attenuate the switching noise sufficiently to
pass EMI testing.
A good starting point is to assume that 24 dB of
attenuation at 75 kHz is needed. That makes the corner
frequency of the common−mode filter as:
Output Ripple:
+5.0 V
100 mV (@ 90 VAC)
+12 V
130 mV (@ 90 VAC)
http://onsemi.com
11
AN1327/D
160
3.5
140
3.0
120
2.5
ON−TIME (mS)
FREQUENCY (kHz)
Figures 10 through 13 graphically represent some of the parameters of the evaluation board that are important to
its operation. These parameters were measured at full−rated load for all of the outputs.
100
80
60
40
200
300
400
500
600
700
800
1.0
0
120
854
300
400
500
600
700
800
INPUT VOLTAGE (VDC)
Figure 10. Frequency vs. Input Voltage
Figure 11. On−Time vs. Input Voltage
0.6
0.6
0.5
0.5
0.4
0.3
0.2
0.1
0
120
200
INPUT VOLTAGE (VDC)
PEAK CURRENT (A)
PEAK CURRENT (A)
1.5
0.5
20
0
120
2.0
854
ACTUAL PEAK CURRENT
0.4
MEASURED PEAK CURRENT
0.3
0.2
0.1
200
300
400
500
600
700
800
0
120
854
200
300
400
500
600
700
800
854
INPUT VOLTAGE (VDC)
INPUT VOLTAGE (VDC)
Figure 12. Actual Peak Current vs
Input Voltage
Figure 13. Actual and Measured Peak Current
vs. Input Voltage
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
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AN1327/D