IRFS3004-7P Data Sheet (487 KB, EN)

PD - 97378A
IRFS3004-7PPbF
HEXFET® Power MOSFET
Applications
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
D
G
Benefits
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free
S
VDSS
RDS(on) typ.
max.
ID (Silicon Limited)
40V
0.90mΩ
1.25mΩ
400A
ID (Package Limited)
240A
c
D
S
G
S
S
S
S
D2Pak 7 Pin
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
ID @ TC = 25°C
ID @ TC = 100°C
ID @ TC = 25°C
IDM
PD @TC = 25°C
Parameter
Max.
d
Pulsed Drain Current
Maximum Power Dissipation
Avalanche Characteristics
EAS (Thermally limited)
IAR
EAR
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
d
Thermal Resistance
Symbol
RθJC
RθJA
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e
Parameter
kl
W/°C
V
V/ns
°C
300
290
See Fig. 14, 15, 22a, 22b
d
Junction-to-Case
Junction-to-Ambient (PCB Mount)
W
2.5
± 20
2.0
-55 to + 175
f
dv/dt
TJ
TSTG
A
240
1610
380
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds (1.6mm from case)
VGS
Units
400c
280c
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Wire Bond Limited)
j
mJ
A
mJ
Typ.
Max.
Units
–––
–––
0.40
40
°C/W
1
04/22/2010
IRFS3004-7PPbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
V(BR)DSS
∆V(BR)DSS/∆TJ
RDS(on)
VGS(th)
IDSS
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Drain-to-Source Leakage Current
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
RG
Min. Typ. Max. Units
40
–––
–––
2.0
–––
–––
–––
–––
–––
––– –––
0.038 –––
0.90 1.25
–––
4.0
–––
20
––– 250
––– 100
––– -100
2.0
–––
Conditions
V VGS = 0V, ID = 250µA
V/°C Reference to 25°C, ID = 5mA
mΩ VGS = 10V, ID = 195A
V VDS = VGS, ID = 250µA
µA VDS = 40V, VGS = 0V
VDS = 40V, VGS = 0V, TJ = 125°C
nA VGS = 20V
VGS = -20V
Ω
d
g
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Qg
Qgs
Qgd
Qsync
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Coss eff. (ER)
Coss eff. (TR)
Parameter
Min. Typ. Max. Units
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Qg - Qgd)
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)
h
i
1300
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
160
42
65
95
23
240
91
160
9130
2020
990
2590
2650
–––
240
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
S
nC
Conditions
VDS = 10V, ID = 195A
ID = 180A
VDS =20V
VGS = 10V
ID = 180A, VDS =0V, VGS = 10V
VDD = 26V
ID = 240A
RG = 2.7Ω
VGS = 10V
VGS = 0V
VDS = 25V
ƒ = 1.0 MHz, See Fig. 5
VGS = 0V, VDS = 0V to 32V , See Fig. 11
VGS = 0V, VDS = 0V to 32V
g
ns
pF
g
i
h
Diode Characteristics
Symbol
IS
Parameter
Continuous Source Current
VSD
trr
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Qrr
Reverse Recovery Charge
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
ISM
d
Notes:
 Calculated continuous current based on maximum allowable junction
temperature. Bond wire current limit is 240A. Note that current
limitations arising from heating of the device leads may occur with
some lead mounting arrangements. (Refer to AN-1140)
‚ Repetitive rating; pulse width limited by max. junction
temperature.
ƒ Limited by TJmax, starting TJ = 25°C, L = 0.01mH
RG = 25Ω, IAS = 240A, VGS =10V. Part not recommended for use
above this value .
2
Min. Typ. Max. Units
–––
–––
–––
Conditions
c
A
MOSFET symbol
1610
A
showing the
integral reverse
––– 400
D
G
p-n junction diode.
TJ = 25°C, IS = 195A, VGS = 0V
VR = 34V,
TJ = 25°C
IF = 240A
TJ = 125°C
di/dt = 100A/µs
TJ = 25°C
g
S
––– –––
1.3
V
–––
49
–––
ns
–––
51
–––
–––
37
–––
nC
TJ = 125°C
–––
41
–––
–––
3.2
–––
A TJ = 25°C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
g
„ ISD ≤ 240A, di/dt ≤ 740A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
… Pulse width ≤ 400µs; duty cycle ≤ 2%.
† Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .
‡ Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
ˆ When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
‰ Rθ is measured at TJ approximately 90°C.
Š RθJC value shown is at time zero.
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IRFS3004-7PPbF
1000
1000
100
BOTTOM
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
BOTTOM
100
10
1
4.5V
≤60µs PULSE WIDTH
0.1
1
10
Tj = 175°C
10
100
0.1
1000
1
10
100
1000
V DS, Drain-to-Source Voltage (V)
V DS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
RDS(on) , Drain-to-Source On Resistance
(Normalized)
2.0
100
T J = 175°C
T J = 25°C
10
1
VDS = 25V
≤60µs PULSE WIDTH
0.1
ID = 195A
VGS = 10V
1.5
1.0
0.5
3
4
5
6
7
8
-60 -40 -20 0 20 40 60 80 100120140160180
VGS, Gate-to-Source Voltage (V)
T J , Junction Temperature (°C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance vs. Temperature
100000
14.0
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
ID= 180A
VGS, Gate-to-Source Voltage (V)
ID, Drain-to-Source Current (A)
≤60µs PULSE WIDTH
4.5V
Tj = 25°C
0.1
C oss = C ds + C gd
C, Capacitance (pF)
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
Ciss
10000
Coss
Crss
1000
12.0
VDS= 32V
VDS= 20V
10.0
8.0
6.0
4.0
2.0
0.0
100
1
10
100
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
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0
50
100
150
200
250
QG, Total Gate Charge (nC)
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
3
IRFS3004-7PPbF
10000
T J = 175°C
100
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
1000
T J = 25°C
10
1
OPERATION IN THIS AREA
LIMITED BY R DS(on)
1000
100µsec
100
1msec
10msec
10
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
0.1
1
0.0
0.5
1.0
1.5
2.0
0
VSD, Source-to-Drain Voltage (V)
300
240
180
120
60
0
50
75
100
125
150
175
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
ID, Drain Current (A)
Limited By Package
25
100
50
Id = 5mA
48
46
44
42
40
-60 -40 -20 0 20 40 60 80 100120140160180
T J , Temperature ( °C )
T C , Case Temperature (°C)
Fig 9. Maximum Drain Current vs.
Case Temperature
3.5
Fig 10. Drain-to-Source Breakdown Voltage
EAS , Single Pulse Avalanche Energy (mJ)
1200
3.0
ID
44A
80A
BOTTOM 240A
TOP
1000
2.5
Energy (µJ)
10
Fig 8. Maximum Safe Operating Area
420
360
1
VDS, Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
2.0
1.5
1.0
0.5
0.0
800
600
400
200
0
-5
0
5
10 15 20 25 30 35 40 45
VDS, Drain-to-Source Voltage (V)
Fig 11. Typical COSS Stored Energy
4
DC
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
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IRFS3004-7PPbF
Thermal Response ( Z thJC ) °C/W
1
D = 0.50
0.1
0.20
0.10
τJ
0.05
0.02
0.01
0.01
R1
R1
τJ
τ1
R2
R2
R3
R3
τC
τ
τ2
τ1
τ2
τ3
τ3
τ4
τ4
Ci= τi/Ri
Ci i/Ri
1E-005
τi (sec)
0.00757
0.000006
0.06508
0.000064
0.18313
0.001511
0.14378
0.009800
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
Ri (°C/W)
R4
R4
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Avalanche Current (A)
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Tj = 150°C and
Tstart =25°C (Single Pulse)
0.01
100
0.05
0.10
10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Τ j = 25°C and
Tstart = 150°C.
1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
320
280
EAR , Avalanche Energy (mJ)
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
TOP
Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 240A
240
200
160
120
80
40
0
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
4.5
10
4.0
9
8
3.5
3.0
2.5
ID = 250µA
ID = 1.0mA
ID = 1.0A
2.0
7
IRRM (A)
VGS(th), Gate threshold Voltage (V)
IRFS3004-7PPbF
IF = 96A
V R = 34V
TJ = 25°C
TJ = 125°C
6
5
4
1.5
3
2
1.0
-75 -50 -25 0
100
25 50 75 100 125 150 175 200
200
T J , Temperature ( °C )
IF = 144A
V R = 34V
TJ = 25°C
TJ = 125°C
8
120
IF = 96A
V R = 34V
100
TJ = 25°C
TJ = 125°C
QRR (nC)
IRRM (A)
9
500
140
12
10
400
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage vs. Temperature
11
300
diF /dt (A/µs)
7
6
80
60
5
4
40
3
20
2
100
200
300
400
100
500
200
300
400
500
diF /dt (A/µs)
diF /dt (A/µs)
Fig. 19 - Typical Stored Charge vs. dif/dt
Fig. 18 - Typical Recovery Current vs. dif/dt
180
160
QRR (nC)
140
120
IF = 144A
V R = 34V
TJ = 25°C
TJ = 125°C
100
80
60
40
20
100
200
300
400
500
diF /dt (A/µs)
6
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRFS3004-7PPbF
Driver Gate Drive
D.U.T
ƒ
-
‚
-
-
„
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+

RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
VDD
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D=
Period
P.W.
+
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor
Current
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V(BR)DSS
15V
DRIVER
L
VDS
tp
D.U.T
RG
VGS
20V
+
V
- DD
IAS
A
0.01Ω
tp
I AS
Fig 22a. Unclamped Inductive Test Circuit
RD
VDS
Fig 22b. Unclamped Inductive Waveforms
VDS
90%
VGS
D.U.T.
RG
+
- VDD
V10V
GS
10%
VGS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
td(on)
Fig 23a. Switching Time Test Circuit
tr
t d(off)
Fig 23b. Switching Time Waveforms
Id
Current Regulator
Same Type as D.U.T.
Vds
Vgs
50KΩ
12V
tf
.2µF
.3µF
D.U.T.
+
V
- DS
Vgs(th)
VGS
3mA
IG
ID
Current Sampling Resistors
Fig 24a. Gate Charge Test Circuit
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Qgs1 Qgs2
Qgd
Qgodr
Fig 24b. Gate Charge Waveform
7
IRFS3004-7PPbF
D2Pak - 7 Pin Package Outline
Dimensions are shown in millimeters (inches)
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
8
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IRFS3004-7PPbF
D2Pak - 7 Pin Part Marking Information
14
D2Pak - 7 Pin Tape and Reel
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 04/2010
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9