MSQA6V1W5T2G, SZMSQA6V1W5T2G Quad Array for ESD Protection ESD Protection Diodes with Low Clamping Voltage http://onsemi.com This quad monolithic silicon voltage suppressor is designed for applications requiring transient overvoltage protection capability. It is intended for use in voltage and ESD sensitive equipment such as computers, printers, business machines, communication systems, medical equipment, and other applications. Its quad junction common anode design protects four separate lines using only one package. These devices are ideal for situations where board space is at a premium. 1 Features 2 Low Clamping Voltage Stand Off Voltage 3 V Low Leakage < 1 mA @ 3 V SC−88A Package Allows Four Separate Unidirectional Configurations IEC1000−4−2 Level 4 ESD Protection SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable Pb−Free Package is Available* Mechanical Characteristics: Void Free, Transfer−Molded, Thermosetting Plastic Case Corrosion Resistant Finish, Easily Solderable Package Designed for Optimal Automated Board Assembly Small Package Size for High Density Applications SC−88A/SOT−323 CASE 419A 5 3 4 MARKING DIAGRAM 61 M G G 61 = Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Package Shipping† MSQA6V1W5T2G SC−88A (Pb−Free) 3,000 / Tape & Reel SZMSQA6V1W5T2G SC−88A (Pb−Free) 3,000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. *T2 Suffix Devices are Packaged with Pin 1 Opposing Sprocket Hole. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Semiconductor Components Industries, LLC, 2012 February, 2012 − Rev. 7 1 Publication Order Number: MSQA6V1W5T2/D MSQA6V1W5T2G, SZMSQA6V1W5T2G MAXIMUM RATINGS Rating Symbol Peak Power Dissipation @ 20 ms @TA 25C (Note 1) Ppk Steady State Power − 1 Diode (Note 2) PD Value Unit 150 W 385 mW 325 3.1 C/W mW/C Thermal Resistance Junction−to−Ambient Above 25C, Derate RqJA Maximum Junction Temperature TJmax 150 C Operating Junction and Storage Temperature Range TJ Tstg −55 to +150 C ESD Discharge MIL STD 883C − Method 3015−6 IEC1000−4−2, Air Discharge IEC1000−4−2, Contact Discharge VPP Lead Solder Temperature (10 s duration) kV 16 16 9 TL 260 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Non−repetitive current per Figure 5. Derate per Figure 10. 2. Only 1 diode under power. For all 4 diodes under power, PD will be 25%. Mounted on FR−4 board with min pad. See Application Note AND8308/D for further description of survivability specs. ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) I Parameter Symbol IPP Maximum Reverse Peak Pulse Current VC Clamping Voltage @ IPP VRWM IR VBR Working Peak Reverse Voltage VC VBR VRWM Maximum Reverse Leakage Current @ VRWM Breakdown Voltage @ IT IT Test Current IF Forward Current VF Forward Voltage @ IF Ppk Peak Power Dissipation C IF V IR VF IT IPP Uni−Directional TVS Capacitance @ VR = 0 and f = 1.0 MHz *See Application Note AND8308/D for detailed explanations of datasheet parameters. ELECTRICAL CHARACTERISTICS Breakdown Voltage VBR @ 1 mA (Vo) (Note 3) Device* MSQA6V1W5T2G Min Nom Max Leakage Current IRM @ VRWM = 3 V (mA) 6.1 6.6 7.2 1.0 Capacitance @ 0 V Bias (pF) Max VF @ IF = 200 mA (V) 90 1.25 3. VBR is measured with a pulse test current IT at an ambient temperature of 25C. 4. For test procedure see Figures 3 and 4 and Application Note AND8307/D. *Include SZ-prefix devices where applicable. http://onsemi.com 2 VC Per IEC61000−4−2 (Note 4) Figures 1 and 2 See Below MSQA6V1W5T2G, SZMSQA6V1W5T2G Figure 1. ESD Clamping Voltage Screenshot Positive 8 kV Contact per IEC61000−4−2 Figure 2. ESD Clamping Voltage Screenshot Negative 8 kV Contact per IEC61000−4−2 IEC61000−4−2 Waveform IEC 61000−4−2 Spec. Ipeak Level Test Voltage (kV) First Peak Current (A) Current at 30 ns (A) Current at 60 ns (A) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 100% 90% I @ 30 ns I @ 60 ns 10% tP = 0.7 ns to 1 ns Figure 3. IEC61000−4−2 Spec ESD Gun Oscilloscope TVS 50 W Cable 50 W Figure 4. Diagram of ESD Test Setup http://onsemi.com 3 MSQA6V1W5T2G, SZMSQA6V1W5T2G The following is taken from Application Note AND8308/D − Interpretation of Datasheet Parameters for ESD Devices. systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D. ESD Voltage Clamping For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger % OF PEAK PULSE CURRENT 100 PEAK VALUE IRSM @ 8 ms tr 90 PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 ms 80 70 60 HALF VALUE IRSM/2 @ 20 ms 50 40 30 tP 20 10 0 0 20 40 t, TIME (ms) 60 Figure 5. 8 X 20 ms Pulse Waveform http://onsemi.com 4 80 MSQA6V1W5T2G, SZMSQA6V1W5T2G 100 Ipp, PEAK PULSE CURRENT (AMPS) IF , FORWARD CURRENT (A) 1.0 0.1 0.01 0.001 0.7 0.8 0.9 1.0 1.1 2.5 ms SQUARE WAVE 1.0 1.2 0 10 20 15 25 VC, CLAMPING VOLTAGE (VOLTS) Figure 6. Forward Voltage Figure 7. Clamping Voltage versus Peak Pulse Current (Reverse Direction) 100 30 1000 10 1.0 2.5 ms SQUARE WAVE 100 10 NOTE: Non−Repetitive Surge. 0.1 1 0 2.0 4.0 6.0 8.0 12 10 100 VC, FORWARD CLAMPING VOLTAGE (VOLTS) Figure 9. Pulse Width 100 90 90 80 70 60 50 40 30 20 10 0 10 Figure 8. Clamping Voltage versus Peak Pulse Current (Forward Direction) 100 0 1 t, TIME (ms) TYPICAL CAPACITANCE (pF) 1 MHz FREQUENCY PEAK PULSE DERATING IN % OF PEAK POWER OR CURRENT @ TA = 25 C 5.0 VF, FORWARD VOLTAGE (VOLTS) Ppk , PEAK SURGE POWER (WATTS) Ipp, PEAK FORWARD PULSE CURRENT (AMPS) 0.6 10 25 50 75 100 125 150 175 200 80 70 60 50 40 30 20 10 0 0 TA, AMBIENT TEMPERATURE (C) 1.0 2.0 3.0 BIAS VOLTAGE (VOLTS) Figure 10. Pulse Derating Curve Figure 11. Capacitance http://onsemi.com 5 1000 4.0 5.0 MSQA6V1W5T2G, SZMSQA6V1W5T2G PACKAGE DIMENSIONS SC−88A (SC−70−5/SOT−353) CASE 419A−02 ISSUE K A NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. 419A−01 OBSOLETE. NEW STANDARD 419A−02. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. G 5 4 −B− S 1 2 DIM A B C D G H J K N S 3 D 5 PL 0.2 (0.008) M B M N INCHES MIN MAX 0.071 0.087 0.045 0.053 0.031 0.043 0.004 0.012 0.026 BSC --0.004 0.004 0.010 0.004 0.012 0.008 REF 0.079 0.087 MILLIMETERS MIN MAX 1.80 2.20 1.15 1.35 0.80 1.10 0.10 0.30 0.65 BSC --0.10 0.10 0.25 0.10 0.30 0.20 REF 2.00 2.20 J C H K ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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