MTP3N60E Designer’s™ Data Sheet TMOS E−FET.™ High Energy Power FET N−Channel Enhancement−Mode Silicon Gate This advanced high voltage TMOS E−FET is designed to withstand high energy in the avalanche mode and switch efficiently. This new high energy device also offers a drain−to−source diode with fast recovery time. Designed for high voltage, high speed switching applications such as power supplies, PWM motor controls and other inductive loads, the avalanche energy capability is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. • Avalanche Energy Capability Specified at Elevated Temperature • Low Stored Gate Charge for Efficient Switching • Internal Source−to−Drain Diode Designed to Replace External Zener Transient Suppressor — Absorbs High Energy in the Avalanche Mode • Source−to−Drain Diode Recovery Time Comparable to Discrete Fast Recovery Diode http://onsemi.com TMOS POWER FET 3.0 AMPERES, 600 VOLTS RDS(on) = 2.2 W TO-220AB CASE 221A−09 Style 5 D ® G S Preferred devices are Motorola recommended choices for future use and best overall value. © Semiconductor Components Industries, LLC, 2006 August, 2006 − Rev. 3 1 Publication Order Number: MTP3N60E/D MTP3N60E MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Symbol Value Unit Drain−Source Voltage VDSS 600 Vdc Drain−Gate Voltage (RGS = 1.0 MΩ) VDGR 600 Vdc Gate−Source Voltage — Continuous Gate−Source Voltage — Non−repetitive VGS VGSM ± 20 ± 40 Vdc Vpk Drain Current — Continuous Drain Current — Continuous @ 100°C Drain Current — Pulsed ID ID 3.0 2.4 14 Adc PD 75 0.6 Watts W/°C TJ, Tstg −55 to 150 °C WDSR(1) mJ WDSR(2) 290 46 7.5 RθJC RθJA 1.67 62.5 °C/W TL 260 °C IDM Total Power Dissipation @ TC = 25°C Derate above 25°C Operating and Storage Temperature Range UNCLAMPED DRAIN−TO−SOURCE AVALANCHE CHARACTERISTICS (TJ < 150°C) Single Pulse Drain−to−Source Avalanche Energy — TJ = 25°C Single Pulse Drain−to−Source Avalanche Energy — TJ = 100°C Repetitive Pulse Drain−to−Source Avalanche Energy THERMAL CHARACTERISTICS Thermal Resistance — Junction to Case° Thermal Resistance — Junction to Ambient° Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds (1) VDD = 50 V, ID = 3.0 A (2) Pulse Width and frequency is limited by TJ(max) and thermal response Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves — representing boundaries on device characteristics — are given to facilitate “worst case” design. http://onsemi.com 2 MTP3N60E ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit Drain−to−Source Breakdown Voltage (VGS = 0, ID = 250 μAdc) V(BR)DSS 600 — — Vdc Zero Gate Voltage Drain Current (VDS = 600 V, VGS = 0) (VDS = 480 V, VGS = 0, TJ = 125°C) IDSS — — — — 10 100 OFF CHARACTERISTICS μAdc Gate−Body Leakage Current — Forward (VGSF = 20 Vdc, VDS = 0) IGSSF — — 100 nAdc Gate−Body Leakage Current — Reverse (VGSR = 20 Vdc, VDS = 0) IGSSR — — 100 nAdc 2.0 1.5 — — 4.0 3.5 — 2.1 2.2 — — — — 9.0 7.5 gFS 1.5 — — mhos Ciss — 770 — pF Coss — 105 — Crss — 19 — td(on) — 23 — tr — 34 — td(off) — 58 — tf — 35 — Qg — 28 31 Qgs — 5.0 — Qgd — 17 — VSD — — 1.4 Vdc ton — ** — ns trr — 400 — — — 3.5 4.5 — — — 7.5 — ON CHARACTERISTICS* Gate Threshold Voltage (VDS = VGS, ID = 250 μAdc) (TJ = 125°C) VGS(th) Static Drain−to−Source On−Resistance (VGS = 10 Vdc, ID = 1.5 A) RDS(on) Drain−to−Source On−Voltage (VGS = 10 Vdc) (ID = 3.0 A) (ID = 1.5 A, TJ = 100°C) VDS(on) Forward Transconductance (VDS = 15 Vdc, ID = 1.5 A) Vdc Ohms Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 V, VGS = 0, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS* Turn−On Delay Time Rise Time Turn−Off Delay Time (VDD = 300 V, ID ≈ 3.0 A, RL = 100 Ω, RG = 12 Ω, VGS(on) = 10 V) Fall Time Total Gate Charge Gate−Source Charge Gate−Drain Charge (VDS = 420 V, ID = 3.0 A, VGS = 10 V) ns nC SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage Forward Turn−On Time (IS = 3.0 A, di/dt = 100 A/μs) Reverse Recovery Time INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the contact screw on tab to center of die) (Measured from the drain lead 0.25″ from package to center of die) Ld Internal Source Inductance (Measured from the source lead 0.25″ from package to source bond pad) Ls * Pulse Test: Pulse Width = 300 μs, Duty Cycle ≤ 2.0%. ** Limited by circuit inductance. http://onsemi.com 3 nH MTP3N60E I D, DRAIN CURRENT (AMPS) 8 VGS = 10 V VGS(th), GATE THRESHOLD VOLTAGE (NORMALIZED TYPICAL ELECTRICAL CHARACTERISTICS 7V 6 4 6V 2 5V 0 0 4 8 12 16 6 10 14 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 2 18 20 1.2 1 0.9 0.8 0.7 −50 I D, DRAIN CURRENT (AMPS) 10 VDS ≥ 10 V 6 4 100°C 2 0 TJ = 25°C 0 1 −55°C 2 4 6 3 5 7 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 8 9 RDS(on) , DRAIN−TO−SOURCE ON−RESISTANCE (NORMALIZED) RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS) 100°C TJ = 25°C 2 −55°C 0 4 6 1 1.1 VGS = 0 ID = 250 μA 1 0.9 0.8 −50 −25 0 25 50 75 100 125 1 Figure 4. Breakdown Voltage Variation With Temperature 4 2 125 TJ, JUNCTION TEMPERATURE (°C) 6 0 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) 1.2 Figure 3. Transfer Characteristics VGS = 10 V −25 Figure 2. Gate−Threshold Voltage Variation With Temperature VBR(DSS), DRAIN−TO−SOURCE BREAKDOWN VOLTAGE (NORMALIZED) Figure 1. On−Region Characteristics 8 VDS = VGS ID = 0.25 mA 1.1 8 10 3 VGS = 10 V ID = 2 A 2 1 0 −50 −25 0 25 50 75 100 125 ID, DRAIN CURRENT (AMPS) TJ, JUNCTION TEMPERATURE (°C) Figure 5. On−Resistance versus Drain Current Figure 6. On−Resistance Variation With Temperature http://onsemi.com 4 1 MTP3N60E SAFE OPERATING AREA INFORMATION 16 VGS = 20 V SINGLE PULSE TC = 25°C I D, DRAIN CURRENT (AMPS) I D, DRAIN CURRENT (AMPS) 100 10 μs 10 100 μs 10 ms 1 ms dc 1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 12 8 TJ ≤ 150°C 4 0 100 10 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 1000 0 Figure 7. Maximum Rated Forward Biased Safe Operating Area 600 200 400 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 80 Figure 8. Maximum Rated Switching Safe Operating Area The power averaged over a complete switching cycle must be less than: FORWARD BIASED SAFE OPERATING AREA TJ(max) − TC RθJC The FBSOA curves define the maximum drain−to−source voltage and drain current that a device can safely handle when it is forward biased, or when it is on, or being turned on. Because these curves include the limitations of simultaneous high voltage and high current, up to the rating of the device, they are especially useful to designers of linear systems. The curves are based on a case temperature of 25°C and a maximum junction temperature of 150°C. Limitations for repetitive pulses at various case temperatures can be determined by using the thermal response curves. Motorola Application Note, AN569, “Transient Thermal Resistance−General Data and Its Use” provides detailed instructions. 10000 VDD = 300 V ID = 3 A VGS(on) = 10 V TJ = 25°C t, TIME (ns) 1000 td(off) tf td(on) 100 tr SWITCHING SAFE OPERATING AREA The switching safe operating area (SOA) of Figure 8 is the boundary that the load line may traverse without incurring damage to the MOSFET. The fundamental limits are the peak current, IDM and the breakdown voltage, V (BR)DSS . The switching SOA shown in Figure 8 is applicable for both turn−on and turn−off of the devices for switching times less than one microsecond. 10 1 10 100 RG, GATE RESISTANCE (OHMS) Figure 9. Resistive Switching Time Variation versus Gate Resistance http://onsemi.com 5 100 RGS DUT MTP3N60E − 1 I D, DRAIN CURRENT (AMPS) r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 4 3 0.5 0.3 0.05 0.03 VGSP(pk) 0.05 0.02 di/dt ≤ 60 A/μs 0 0.02 0.05 RθJC(t) = r(t) RθJC RθJC = 1.67°C/W MAX VR = 80% OF RATED VDS D CURVES APPLY FOR POWER VdsL = Vf +SHOWN Li ⋅ dls/dt PULSE TRAIN READ TIME AT t1 TJ(pk) − TC = P(pk) RθJC(t) t1 t2 0.01 0.02 0.01 0.01 VDS 20 V − 0.1 0.1 Li IS + 0.2 DUTY CYCLE, D = t1/t2 Figure 13. Commutating Safe Operating Area Test Circuit SINGLE PULSE 0 IFM + 0.2 2 1 VR D = 0.5 0.1 0.2 200 400 600 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 0.5 1 2 5 10 20 50 100 200 500 1 t, TIME (ms) 800 V(BR)DSSResponse Figure 10. Thermal Figure 12. Commutating Safe Operating Area (CSOA) Vds(t) COMMUTATING SAFE OPERATING AREA (CSOA) IO 15 V The Commutating Safe Operating Area (CSOA) of Figure L 12 defines the limits of safe operation for commutated source-drain current Vversus re-applied drain voltage when C DS the source-drain diode has undergone forward 4700bias. μF The ID VR250 forV a given curve shows the limitations of IFM and peak commutation speed. It is applicable when waveforms VDD similar to those of Figure 11 are present. Full or half-bridge PWM DC motor controllers are common applications t requiring CSOA data. The time interval tfrr is Rthe GS speed of the commutation 50 Ω cycle. Device stresses increase with commutation speed, so t frr is specified with a minimum value. Faster commutation speeds require an appropriate of IFM, Figure 14. Unclamped Inductive derating Switching peak VR or both. Ultimately, tfrr is limited primarily by device, Test Circuit package, and circuit impedances. Maximum device stress occurs during trr as the diode goes from conduction to reverse blocking. VDS(pk) is the peak drain−to−source voltage that the device must sustain during commutation; I FM is the maximum forward source-drain diode current just prior to the onset of commutation. VR is specified at 80% of V(BR)DSS to ensure that the CSOA stress is maximized as IS decays from IRM to zero. RGS should be minimized during commutation. TJ has only a second order effect on CSOA. Stray inductances, L i in Motorola’s test circuit are assumed to be practical minimums. VGS 0 IFM 90% ID(t) dlS/dt IS trr 10% VDD ton IRM tP 0.25 It,RM(TIME) V(BR)DSS WDSR + 1 LIO2 2 V(BR)DSS–VDD VDS(pk) tfrr ǒ Ǔǒ Ǔ VR Inductive Switching Figure 15. Unclamped Waveforms VDS Vf VdsL MAX. CSOA STRESS AREA Figure 11. Commutating Waveforms http://onsemi.com 6 MTP3N60E TJ = 25°C 1400 VGS = 0 V 1200 C, CAPACITANCE (pF) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 1600 1000 Ciss Crss 800 600 400 200 0 10 VDS = 0 V 5 Coss 0 VGS 10 5 20 15 16 12 250 V 420 V 8 4 0 25 VDS = 100 V TJ = 25°C ID = 3 A 0 10 20 30 15 25 Qg, TOTAL GATE CHARGE (nC) 5 VDS GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 16. Capacitance Variation Figure 17. Gate Charge versus Gate−To−Source Voltage +18 V VDD 1 mA Vin 10 V 15 V SAME DEVICE TYPE AS DUT 100 k 2N3904 0.1 μF 2N3904 100 k 47 k 100 FERRITE BEAD Vin = 15 Vpk; PULSE WIDTH ≤ 100 μs, DUTY CYCLE ≤ 10% Figure 18. Gate Charge Test Circuit http://onsemi.com 7 DUT 35 4 MTP3N60E PACKAGE DIMENSIONS CASE 221A−09 ISSUE Z −T− T SEATING PLANE C S 4 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. DIM A B C D F G H J K L N Q R S T U V Z A Q 1 2 3 U H K Z L R V J G D N INCHES MIN MAX 0.570 0.620 0.380 0.405 0.160 0.190 0.025 0.035 0.142 0.147 0.095 0.105 0.110 0.155 0.018 0.025 0.500 0.562 0.045 0.060 0.190 0.210 0.100 0.120 0.080 0.110 0.045 0.055 0.235 0.255 0.000 0.050 0.045 −−− −−− 0.080 STYLE 5: PIN 1. 2. 3. 4. MILLIMETERS MIN MAX 14.48 15.75 9.66 10.28 4.07 4.82 0.64 0.88 3.61 3.73 2.42 2.66 2.80 3.93 0.46 0.64 12.70 14.27 1.15 1.52 4.83 5.33 2.54 3.04 2.04 2.79 1.15 1.39 5.97 6.47 0.00 1.27 1.15 −−− −−− 2.04 GATE DRAIN SOURCE DRAIN E−FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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