MOTOROLA MTP12N10E

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by MTP12N10E/D
SEMICONDUCTOR TECHNICAL DATA
 
Motorola Preferred Device
N–Channel Enhancement–Mode Silicon Gate
This advanced TMOS E–FET is designed to withstand high
energy in the avalanche and commutation modes. The new energy
efficient design also offers a drain–to–source diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
• Designed to Eliminate the Need for External Zener Transient
Suppressor — Absorbs High Energy in the Avalanche Mode
• Commutating Safe Operating Area (CSOA) Specified for Use
in Half and Full Bridge Circuits
• Source–to–Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature
TMOS POWER FET
12 AMPERES
100 VOLTS
RDS(on) = 0.16 OHM

D
G
S
CASE 221A–06, Style 5
TO–220AB
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Symbol
Value
Unit
Drain–Source Voltage
VDSS
100
Vdc
Drain–Gate Voltage (RGS = 1.0 MΩ)
VDGR
100
Vdc
Gate–Source Voltage — Continuous
Gate–Source Voltage — Single Pulse (tp ≤ 50 µs)
VGS
± 20
± 40
Vdc
Drain Current — Continuous
Drain Current — Single Pulse (tp ≤ 10 µs)
ID
IDM
12
30
Adc
Total Power Dissipation @ TC = 25°C
Derate above 25°C
PD
79
0.53
Watts
W/°C
TJ, Tstg
– 55 to 175
°C
EAS
290
mJ
RθJC
RθJA
1.9
62.5
°C/W
TL
260
°C
Rating
Operating and Storage Temperature Range
UNCLAMPED DRAIN–TO–SOURCE AVALANCHE CHARACTERISTICS (TJ ≤ 175°C)
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 V, VGS = 10 V, L = 4.03 mH, RG = 25 Ω, Peak IL = 12 A)
(See Figures 15, 16 and 17)
THERMAL CHARACTERISTICS
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient°
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 1
TMOS
 Motorola
Motorola, Inc.
1996
Power MOSFET Transistor Device Data
1
MTP12N10E
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
100
—
—
110
—
—
Vdc
mV/°C
—
—
—
—
10
100
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
(VGS = 0, ID = 250 µAdc)
Temperature Coefficient (positive)
V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = 100 V, VGS = 0)°
(VDS = 100 V, VGS = 0, TJ = 150°C)
µA
IDSS
Gate–Body Leakage Current, Forward (VGSF = 20 Vdc, VDS = 0)
IGSSF
—
—
100
nAdc
Gate–Body Leakage Current, Reverse (VGSR = 20 Vdc, VDS = 0)
IGSSR
—
—
100
nAdc
2.0
—
3.0
6.0
4.0
—
mV/°C
—
0.125
0.16
Ohm
—
—
1.5
1.4
2.4
1.92
gFS
4.0
5.0
—
mhos
Ciss
—
600
—
pF
Crss
—
70
—
Coss
—
230
—
td(on)
—
10
—
tr
—
64
—
td(off)
—
21
—
ON CHARACTERISTICS*
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Temperature Coefficient (negative)µ
VGS(th)
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 6.0 Adc)
RDS(on)
Drain–Source On–Voltage (VGS = 10 Vdc)
(ID = 12 Adc)°
(ID = 6.0 Adc, TJ = 150°C)
VDS(on)
Forward Transconductance (VDS ≥ 15 V, ID = 6.0 A)
Vdc
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
Reverse Transfer Capacitance
Output Capacitance
(VDS = 25 V, VGS = 0,
f = 1.0 MHz)
See Figure 14
SWITCHING CHARACTERISTICS (TJ = 100°C)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
(VDD = 50 V, ID = 12 A,
VGS = 10 V, RG = 12 Ω)
See Figure 7
Fall Time
tf
—
30
—
QT
—
18
26
Q1
—
4.0
—
Q2
—
10
—
Q3
—
8.0
—
(IS = 12 A, VGS = 0)
(IS = 12 A, VGS = 0, TJ = 150°C)
VSD
—
1.0
2.5
—
0.83
—
(IS = 12 A, VGS = 0,
dIS/dt = 100 A/µs, VR = 50 V)
trr
—
110
—
—
—
3.5
4.5
—
—
—
7.5
—
Gate Charge
(VDS = 80 V, ID = 12 A,
VGS = 10 Vdc)
See Figures 5 and 6
ns
nC
SOURCE–DRAIN DIODE CHARACTERISTICS*
Forward On–Voltage
Reverse Recovery Time
Vdc
ns
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the contact screw on tab to center of die)″
(Measured from the drain lead 0.25″ from package to center of die)
Ld
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
Ls
nH
* Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%.
2
Motorola TMOS Power MOSFET Transistor Device Data
MTP12N10E
TYPICAL ELECTRICAL CHARACTERISTICS
24
24
VGS = 10 V
VDS ≥ 15 V
9V
20
I D, DRAIN CURRENT (AMPS)
8V
16
7V
12
6V
8
5V
4
12
8
4
0
0
5
1
2
3
4
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
0
Figure 2. Transfer Characteristics
RDS(on) , DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
0.6
VGS = 10 V
0.5
0.4
0.3
TJ = 100°C
0.2
25°C
0.1
–55°C
0
0
3
6
9
12
15
18
ID, DRAIN CURRENT (AMPS)
21
2.2
VGS = 10 V
ID = 6 A
2
1.8
1.6
1.4
1.2
1
0.8
0.6
–50
24
–25
15 V
1 mA
10 V
0.1 µF
2N3904
2N3904
100 k
47 k
100 k
100
FERRITE
BEAD
SAME
DEVICE
TYPE
AS DUT
DUT
Vin = 15 Vpk; PULSE WIDTH ≤ 100 µs, DUTY CYCLE ≤ 10%.
Figure 5. Gate Charge Test Circuit
Motorola TMOS Power MOSFET Transistor Device Data
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
47 k
VDD
0
25
50
75
100 125
TJ, JUNCTION TEMPERATURE (°C)
150
175
Figure 4. On–Resistance Variation
with Temperature
Figure 3. On–Resistance versus Drain Current
+18 V
10
2
4
6
8
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 1. On–Region Characteristics
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
100°C
25°C
16
0
Vin
TJ = –55°C
20
20
100
ID = 12 A
VDS = 80 V
TJ = 25°C
VDS
16
80
12
60
QT
8
40
Q1
Q2
VGS
4
20
Q3
0
0
5
10
15
Qg, TOTAL GATE CHARGE (nC)
20
0
25
VDS , DRAIN–TO–SOURCE VOLTAGE (VOLTS)
I D, DRAIN CURRENT (AMPS)
TJ = 25°C
Figure 6. Gate–To–Source and
Drain–To–Source Voltage versus Gate Charge
3
MTP12N10E
SAFE OPERATING AREA INFORMATION
FORWARD BIASED SAFE OPERATING AREA
The power averaged over a complete switching cycle must
be less than:
TJ(max) – TC
RθJC
1000
100
tf
td(off)
10
The switching safe operating area (SOA) of Figure 9 is the
boundary that the load line may traverse without incurring
damage to the MOSFET. The fundamental limits are the
peak current, I DM and the breakdown voltage, BVDSS. The
switching SOA shown in Figure 9 is applicable for both turn–
on and turn–off of the devices for switching times less than
one microsecond.
1
10
100
RG, GATE RESISTANCE (OHMS)
1000
Figure 7. Resistive Switching Time
versus Gate Resistance
40
1000
100
VGS = 20 V
SINGLE PULSE
TC = 25°C
OPERATION LIMITED IN THIS
AREA BY RDS(on)
10
10 ms
I D, DRAIN CURRENT (AMPS)
I D, DRAIN CURRENT (AMPS)
tr
td(on)
SWITCHING SAFE OPERATING AREA
100 µs
1 ms
dc
1
0.1
VDD = 50 V
ID = 12 A
VGS = 10 V
TJ = 25°C
t, TIME (ns)
The FBSOA curves define the maximum drain–to–source
voltage and drain current that a device can safely handle
when it is forward biased, or when it is on, or being turned on.
Because these curves include the limitations of simultaneous
high voltage and high current, up to the rating of the device,
they are especially useful to designers of linear systems. The
curves are based on a case temperature of 25°C and a maximum junction temperature of 175°C. Limitations for repetitive
pulses at various case temperatures can be determined by
using the thermal response curves. Motorola Application
Note, AN569, “Transient Thermal Resistance–General Data
and Its Use” provides detailed instructions.
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
30
20
TJ ≤ 175°C
10
0
0.1
1
10
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
0
100
Figure 8. Maximum Rated Forward Biased
Safe Operating Area
20
40
60
80
100
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
120
Figure 9. Maximum Rated Switching
Safe Operating Area
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
1
D = 0.5
0.5
0.3
0.2
0.2
0.1
0.1
P(pk)
0.05
0.05
0.02
t1
0.03
t2
DUTY CYCLE, D = t1/t2
0.01
0.02
SINGLE PULSE
0.01
0.01
0.02
0.05
0.1
0.2
0.5
1
2
t, TIME (ms)
5
10
20
RθJC(t) = r(t) RθJC
RθJC = 1.9°C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) – TC = P(pk) RθJC(t)
50
100
200
500
1000
Figure 10. Thermal Response
4
Motorola TMOS Power MOSFET Transistor Device Data
MTP12N10E
COMMUTATING SAFE OPERATING AREA (CSOA)
The Commutating Safe Operating Area (CSOA) of Figure
12 defines the limits of safe operation for commutated source-drain current versus re-applied drain voltage when the
source-drain diode has undergone forward bias. The curve
shows the limitations of IFM and peak VDS for a given rate of
change of source current. It is applicable when waveforms
similar to those of Figure 11 are present. Full or half-bridge
PWM DC motor controllers are common applications requiring CSOA data.
Device stresses increase with increasing rate of change of
source current so dIs/dt is specified with a maximum value.
Higher values of dIs/dt require an appropriate derating of IFM,
peak VDS or both. Ultimately dIs/dt is limited primarily by device, package, and circuit impedances. Maximum device
stress occurs during trr as the diode goes from conduction to
reverse blocking.
VDS(pk) is the peak drain–to–source voltage that the device
must sustain during commutation; IFM is the maximum forward source-drain diode current just prior to the onset of
commutation.
VR is specified at rated BVDSS to ensure that the CSOA
stress is maximized as IS decays from IRM to zero.
RGS should be minimized during commutation. TJ has only
a second order effect on CSOA.
Stray inductances in Motorola’s test circuit are assumed to
be practical minimums.
15 V
VGS
0
IFM
dls/dt
90%
IS
10%
trr
ton
IRM
0.25 IRM
VDS(pk)
VR
VDS
dVDS/dt
VdsL
Vf
MAX. CSOA
STRESS AREA
Figure 11. Commutating Waveforms
IS , SOURCE–TO–DRAIN CURRENT (AMPS)
15
RGS
TJ ≤ 175°C
IS = 12 A
dIs/dt ≤ 100 A/µs
VR ≤ 100 V
12
9
–
VR
+
IFM
IS
6
+
3
20 V
–
0
VGS
0
20
40
60
80 100 120 140 160
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
180
DUT
200
Figure 12. Commutating Safe Operating
Area (CSOA)
Li
VDS
VR = 80% OF RATED BVDSS
VdsL = Vf + Li ⋅ dls/dt
Figure 13. Commutating Safe Operating Area
Test Circuit
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different
applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does
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Motorola TMOS Power MOSFET Transistor Device Data
5
EAS , SINGLE PULSE AVALANCHE ENERGY (mJ)
MTP12N10E
300
2000
VGS = 0 V
VDS = 0 V
PEAK IL = 12 A
VDD = 25 V
250
C, CAPACITANCE (pF)
1500
200
150
1000
Ciss
100
500
Coss
Crss
0
15
0
15
30
45
60
50
0
75
100
125
150
50
TJ, STARTING JUNCTION TEMPERATURE (°C)
25
VGS
VDS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 14. Capacitance Variation
175
Figure 15. Maximum Avalanche Energy versus
Starting Junction Temperature
BVDSS
L
VDS
IL
IL(t)
VDD
RG
t
VDD
tP
Figure 16. Unclamped Inductive Switching
Test Circuit
t, (TIME)
Figure 17. Unclamped Inductive Switching
Waveforms
PACKAGE DIMENSIONS
–T–
B
C
F
T
S
4
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
A
Q
1 2 3
SEATING
PLANE
U
H
K
Z
L
R
V
J
STYLE 5:
PIN 1.
2.
3.
4.
CASE 221A–06
TO–220AB
ISSUE Y
G
D
N
GATE
DRAIN
SOURCE
DRAIN
DIM
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
T
U
V
Z
INCHES
MIN
MAX
0.570
0.620
0.380
0.405
0.160
0.190
0.025
0.035
0.142
0.147
0.095
0.105
0.110
0.155
0.018
0.025
0.500
0.562
0.045
0.060
0.190
0.210
0.100
0.120
0.080
0.110
0.045
0.055
0.235
0.255
0.000
0.050
0.045
–––
–––
0.080
MILLIMETERS
MIN
MAX
14.48
15.75
9.66
10.28
4.07
4.82
0.64
0.88
3.61
3.73
2.42
2.66
2.80
3.93
0.46
0.64
12.70
14.27
1.15
1.52
4.83
5.33
2.54
3.04
2.04
2.79
1.15
1.39
5.97
6.47
0.00
1.27
1.15
–––
–––
2.04
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6
◊
*MTP12N10E/D*
Motorola TMOS Power MOSFET Transistor
Device Data
MTP12N10E/D