S6J311A, S6J3119, S6J3118
32-Bit Traveo™ Family
S6J3110 Series Microcontroller Datasheet
®
The S6J3110 series is a set of 32-bit microcontrollers designed for in-vehicle use. It uses the ARM Cortex-R5 CPU as a CPU.
Features
Cortex-R5 Core
Built-in RAM size
This section explains the Cortex-R5 CPU core.
TCRAM
64 KB (S6J311AHzC*) / 48 KB (S6J3119HzC*) /
32 KB (S6J3118HzC*)
System SRAM 16 KB (S6J311AHzC*) / 16 KB
(S6J3119HzC*) / 16 KB (S6J3118HzC*)
Backup RAM 8 KB (S6J311AHzC*) / Backup RAM 8 KB
(S6J3119HzC*) / Backup RAM 8 KB (S6J3118HzC*)
*z: A/B
ARM® Cortex®-R5
32-bit ARM architecture
2-instruction
8-stage
issuance super scalar
pipeline
ARMv7/Thumb®-2 instruction set
General-purpose ports: 116 channels (S6J311AHzC*) / 116
MPU (memory protection) equipped
16-area
channels (S6J3119HzC*) / 116 channels (S6J3118HzC*)
support
*z: A/B
ECC support for the TCM ports for RAM
1-bit error correction and 2-bit error detection (SEC-DED)
TCM ports
DMA controller
Up
A/D converter (successive approximation type)
2 TCM ports
ATCM port
BTCM port (B0TCM, B1TCM)
12-bit resolution, 2 units mounted: Max 56 channels (25
channels + 31 channels) (S6J311AHzC*) / Max 56
channels (25 channels + 31 channels) (S6J3119HzC*) /
Max 56 channels (25 channels + 31 channels)
(S6J3118HzC*)
*z: A/B
Caches
Instruction
Data
to 16 channels can be activated simultaneously.
cache 16 KB
cache 16 KB
External interrupt input: 16 channels
Level
VIC port
Low latency interrupt
("H"/"L") and edge (rising/falling) can be detected.
Multi-function serial (transmission and reception FIFOs
mounted) :Max 4 channels (S6J311AHzC*) / Max 4 channels
(S6J3119HzC*) / Max 4 channels (S6J3118HzC*)
AXI master interface
64-bit AXI interface (instruction/data access)
*z: A/B
32-bit AXI interface (I/O access)
<I2C>
AXI slave interface
Full-duplex double buffering system, 64-byte transmission
64-bit AXI interface (TCM port access)
FIFO, 64-byte reception FIFO.
ETM-R5 trace
Standard mode ( Max. 100kbps ) is supported only.
Peripheral Functions
DMA transfer is supported.
Clock generation
Full duplex, double buffering system; 64-byte transmission
<UART (asynchronous serial interface) >
This section explains peripheral functions.
FIFO, 64-byte reception FIFO
Main
clock oscillation (4 MHz)
No sub clock oscillation
CR oscillation (100 kHz)
CR oscillation (4 MHz)
Parity check can be enabled/disabled.
Built-in dedicated baud rate generator
An external clock can be used as a transfer clock.
Built-in flash memory size
Program:
1024 K + 64 KB (S6J311AHzC*) / 768 K + 64 KB
(S6J3119HzC*) / 512 K + 64 KB (S6J3118HzC*)
Work: 48 KB (S6J311AHzC*) / 48 KB (S6J3119HzC*) / 48
KB (S6J3118HzC*)
*z: A/B
Cypress Semiconductor Corporation
Document Number: 002-04632 Rev.*B
•
Parity, frame, overrun error detection functions are available.
DMA transfer is supported.
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 20, 2016
S6J311A, S6J3119, S6J3118
<CSIO (synchronous serial interface) >
Full duplex, double buffering system; 64-byte transmission
FIFO, 64-byte reception FIFO
Support for SPI. Both master and slave roles are supported.
Data length in bits can be set to a value from 5 to 16 or one
of the values of 20, 24, and 32.
Built-in dedicated baud rate generator (master operation)
External clock input is enabled (slave operation).
Overrun error detection function is available.
DMA transfer is supported.
Serial chip select SPI function
<LIN-UART (asynchronous serial interface for LIN) >
Full duplex, double buffering system; 64-byte transmission
FIFO, 64-byte reception FIFO
Support for LIN protocol revision 2.1
Both master and slave roles are supported.
Framing error and overrun error detection
LIN Synch break generation and detection, LIN Synch
Delimiter generation
Built-in dedicated baud rate generator
The external clock can be adjusted by the reload counter.
DMA transfer is supported.
CAN controller: CAN-FD Max 1 channel
CAN-FD
(V3.2.0)
transfer speed :Max 5Mbps
CAN Clock :Max 40MHz
192 message buffers/channel (reception message buffer
size)
32 message buffer/channel (transmission message buffer
size)
CAN
Base timer: Max 30 channels
16bit
Timer.
is selectable by 4 functions of the
PWM/PPG/PWC/Reload Timer.
2-channel cascade connection enables operation as a
32-bit timer.(PWC and Reload Timer)
It
Free-run timer: Max 6 channels
32bit
Timer.
Main clock oscillation and CR oscillation are available.
Free-run timer output can work in combination with an
input capture and an output compare.
Input capture: Max 12 channels
32bit
Timer.
Document Number: 002-04632 Rev.*B
Output compare: Max 12 channels
32bit
Timer.
Real time clock (RTC) (day/hour/minute/second)
Main
clock oscillation or CR oscillation (100 kHz) can be
selected as an operation clock.
Calibration: Real time clock (RTC) driven by the CR clock
Correction can be done by configuring the prescaler of the
real time clock based on the ratio between the main clock
and the CR clock.
Clock supervisor
Abnormality
(such as damaged crystal) of the main clock
oscillation (4 MHz) can be monitored.
The clock can switch to the CR clock when an abnormality
is detected.
PLL abnormality can be detected.
CRC generation
Fixed-length
CRC
CRC16 generator polynomial: 0x1021
IEEE-802.3 CRC32 generator polynomial: 0x04C11DB7
CCITT
Watchdog timer
Hardware
Software
watchdog
watchdog
NMI
I/O relocation
Peripheral
function pin locations can be changed.
Low-power consumption control
Standby
function
function
Partial wakeup function
Power-off
Power-on reset
Low-voltage detection reset
Security
Flash
security
security (JTAG + test port)
Interface
SHE
Unique
device ID
Package: LEU144 (S6J311xHzC*)
*z: A/B
CMOS 55 nm technology
Power supply
5
V single power supply
voltage step-down circuit generates internal 1.2 V from
5 V.
5 V power supply is used for I/O.
The
Page 2 of 92
S6J311A, S6J3119, S6J3118
Contents
1. Product Lineup .................................................................................................................................................................. 4
2. Pin Assignment ................................................................................................................................................................. 6
3. Pin Description .................................................................................................................................................................. 7
4. I/O Circuit Types.............................................................................................................................................................. 15
5. Handling Precautions ..................................................................................................................................................... 18
5.1
Precautions for Product Design ................................................................................................................................... 18
5.2
Precautions for Package Mounting .............................................................................................................................. 19
5.3
Precautions for Use Environment ................................................................................................................................ 20
6. Handling Devices ............................................................................................................................................................ 21
7. Block Diagram ................................................................................................................................................................. 23
8. Memory Map .................................................................................................................................................................... 24
9. Pin Status in CPU Status ................................................................................................................................................ 29
10. Electrical Characteristics ............................................................................................................................................... 32
10.1 Absolute Maximum Ratings ......................................................................................................................................... 32
10.2 Recommended Operating Conditions.......................................................................................................................... 34
10.3 DC Characteristics....................................................................................................................................................... 37
10.4 AC Characteristics ....................................................................................................................................................... 44
10.4.1 Source Clock Timing .................................................................................................................................................... 44
10.4.2 Internal Clock Timing ................................................................................................................................................... 45
10.4.3 Reset Input................................................................................................................................................................... 48
10.4.4 Power-on Conditions .................................................................................................................................................... 49
10.4.5 Multi-function Serial...................................................................................................................................................... 50
10.5 Timer Input Timing....................................................................................................................................................... 71
10.6 Trigger Input Timing .................................................................................................................................................... 72
10.7 NMI Input Timing ......................................................................................................................................................... 73
10.8 Low-Voltage Detection (External Low-Voltage Detection) ........................................................................................... 74
10.9 Low-Voltage Detection (RAM Retention Low-Voltage Detection) ................................................................................ 75
10.10 Low-Voltage Detection (1.2 V Power Supply Low-Voltage Detection) ......................................................................... 75
10.11 A/D Converter.............................................................................................................................................................. 76
10.11.1 Electrical Characteristics .......................................................................................................................................... 76
10.11.2 Notes on Using A/D Converters ................................................................................................................................ 77
10.11.3 Definition of terms ..................................................................................................................................................... 78
10.12 Flash Memory .............................................................................................................................................................. 80
11. Ordering Information ...................................................................................................................................................... 81
12. Part Number Option ........................................................................................................................................................ 81
13. Package Dimensions ...................................................................................................................................................... 82
14. Major Changes ................................................................................................................................................................ 83
Document History ................................................................................................................................................................. 91
Sales, Solutions, and Legal Information............................................................................................................................. 92
Document Number: 002-04632 Rev.*B
Page 3 of 92
S6J311A, S6J3119, S6J3118
1. Product Lineup
The following table lists the product lineup of the S6J3110 series.
Table 1-1. Memory Size
S6J311AHzC*
Flash
RAM
S6J3119HzC*
S6J3118HzC*
Work
1024K bytes
+
Small sector (8 KB x 8)
48K bytes
768K bytes
+
Small sector (8 KB x 8)
48K bytes
512K bytes
+
Small sector (8 KB x 8)
48K bytes
TCRAM
64K bytes
48K bytes
32K bytes
System SRAM
16K bytes
16K bytes
16K bytes
Backup RAM
8K bytes
8K bytes
8K bytes
Program
*z: A/B
Table 1-2. SHE option
S6J311xHAC*
S6J311xHBC*
ON
OFF
Security (SHE)
* x: A/9/8
Table 1-3. Product Lineup
S6J311xHzC*
CPU core
Coretex-R5
CMOS 55 nm technology
55 nm
Package
LEU144
Main clock
4 MHz
Built-in CR oscillator
100 kHz
4 MHz
Maximum CPU operating frequency
96 MHz
Watchdog timer
1 channel (hardware)
1 channel (software)
Clock supervisor
YES
External power supply, low-voltage detection reset
YES
Internal power supply, low-voltage detection reset
YES
NMI request
YES
External interrupt
16 channels
DMA controller
16 channels
CAN-FD
1 channel
(192 msg buffers/ch)
Multi-function serial
4 channels
A/D converter
12-bit (2 units)
Unit 0 x 25 channels
Unit 1 x 31 channels
Document Number: 002-04632 Rev.*B
Page 4 of 92
S6J311A, S6J3119, S6J3118
S6J311xHzC*
Free-run timer
6 channels
Input capture
12 channels
Output compare
12 channels
Base timer (16-bit)
30 channels
Real time clock (RTC)
1 channel
CR clock calibration
YES
CRC generation
YES
Low-power consumption mode
Standby function
Power-off function
Partial wakeup function
SHE
YES
General-purpose port GPIO
116 channels
Power supply
5 V + 5% to 10%
Operation assurance temperature (TA)
-40 °C to +125 °C
On-chip debugger (JTAG)
YES
* x: A/9/8, z: A/B
Document Number: 002-04632 Rev.*B
Page 5 of 92
S6J311A, S6J3119, S6J3118
2. Pin Assignment
The following figures show the pin assignment of the S6J3110 series.
Figure 2-1. Pin Assignment for S6J311xHzC*
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
VCC
P421/SIN2_1/TRACECTL
P420/SCK2_1/TRACECLK
P418/INT14_0/SCS22_0
P417/INT15_1/TIOA23_1
P416/IN5_0/TIOA22_1
P414/SCS21_0
P413/INT14_1/SCS20_0
P411/INT13_1/SCK2_0/SCL2_0/TRACEDATA7
P409/SOT2_0/SDA2_0/TIOA24_1/TRACEDATA6
P408/INT12_0/SIN2_0/TRACEDATA5
P407/TRACEDATA4
P406/TRACEDATA3
P405/INT11_0/IN4_0/TRACEDATA2
P404/IN3_0/TRACEDATA1
P403/IN2_0/TRACEDATA0
P402/INT2_0/IN1_0
P401/IN0_0
C
VSS
VCC
RSTX
P400
P331
VSS
X1
X0
MD
P330
P327
TCK
TMS
TDI/P324
TDO/P323
TRST/P322
VCC
* x: A/9/8, z: A/B
VSS
P000/SOT2_1
P001/SCS20_1
P003/SCS22_1
P005/SIN3_0/IN6_0
P006/SDA3_0/SOT3_0/IN7_0
P007/SCK3_0/SCL3_0/IN8_0
P008/SCS30_0/IN9_0/TIOA0_0
P009/INT0_1/IN10_0/TIOA1_0
P010/IN11_0/TIOA2_0
P012/OUT5_0/TIOA3_0
P013/OUT6_0/TIOA4_0
P015/OUT7_0/TIOA5_0
P016/OUT8_0/TIOA6_0
P017/OUT9_0/TIOA7_0
P018/OUT10_0/TIOA8_0
P019/TEXT0_0/OUT11_0/TIOB0_0
P020/SOT0_0/SDA0_0/TEXT1_0/TIOB1_0
P021/SCK0_0/SCL0_0/TIOB2_0
P022/INT3_0/SIN0_0/TIOB3_0
P023/SCS0_0/TIOB4_0
P024/TIOB5_0
P027/INT1_1/TEXT0_1/TIOB6_0/TIOA4_1
P028/INT4_0/SIN1_0/OUT0_1/TIOB7_0
P029/AN0/SOT1_0/SDA1_0/OUT1_1
P030/OUT2_1
P031/AN1/SCS1_0/OUT3_1
P100/AN2/SCK1_0/SCL1_0/OUT4_1
P101/AN3/OUT5_1
P103/AN5/OUT6_1
P105/OUT7_1/TIOA9_0
P106/OUT8_1
P107/INT2_1/OUT9_1/TIOA10_0
P108/INT3_1/AN6/OUT10_1/TIOA11_0
P109/OUT11_1/TIOA12_0
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
●
TOP VIEW
LEU-144
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
VSS
P321/PWUTRG
VSS
VCC
P317/INT11_1/AN62/TIOA9_1
P315/AN61/IN5_1/TIOA8_1
P314/AN60/IN4_1/TIOA7_1
P313/INT10_1/AN59/IN3_1
P312/AN58/IN2_1
P309/AN57/IN1_1/TIOA29_1
P308/AN56/IN0_1/TIOA28_1
P307/INT1_0/AN55/RX0_0
P306/AN54/TX0_0
NMIX
P305/AN53/TEXT5_0/TIOA29_0
P304/AN52/TEXT4_0/TIOA20_1
P302/AN51/TIOA19_1
P301/AN50/OUT4_0/TIOA18_1
P300/AN49/OUT3_0/TIOA28_0
P231/AN48/OUT2_0/TIOA27_0
P230/AN47/PWU_AN7/OUT1_0/TIOA26_0
P229/INT8_0/AN46/PWU_AN6/RX0_1/OUT0_0/TIOA25_0
P228/AN45/PWU_AN5/TX0_1/TIOA24_0
P227/AN44/PWU_AN4/TIOA23_0
AVCC1
AVRH1
AVSS1/AVRL1
P226/AN43/PWU_AN3/IN11_2/TIOA17_1
P225/INT0_0/AN42/PWU_AN2/RX0_2/IN10_2
P224/AN41/PWU_AN1/TX0_2/IN9_2
P223/AN40/PWU_AN0/IN8_2
P222/INT7_0/AN39/IN7_2
P220/AN38/IN6_2
P219/AN37/TEXT3_0
P218/AN36/TEXT2_0
VSS
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
VCC
P215/INT9_1/IN5_2/TIOA16_1
P214/IN4_2/TIOA15_1
P213/INT8_1/IN3_2/TIOA14_1
P212/AN35/IN2_2/TIOA13_1
P211/AN34/IN1_2/TIOA22_0
P210/INT6_0/AN33/IN0_2/TIOA21_0
P209/AN32/TIOA20_0
P208/AN31/TIOA19_0
P207/INT7_1/AN30/TEXT5_1
P206/AN29/TEXT4_1
P205/AN28/TEXT3_1
P204/AN27/IN11_1
P203/IN10_1
P202/INT6_1/IN9_1
P131/AN24/IN8_1
P130/INT5_0/AN23/IN7_1
P129/AN22/IN6_1
P128/AN21/TEXT2_1
P127/AN20/TEXT1_1
P126/AN19
P123/AN18/TIOA12_1
P122/AN17/TIOA11_1
P120/AN15
P119/AN14
P118/INT5_1/AN13
P117/INT4_1/AN12
P115
AVSS0/AVRL0
AVRH0
AVCC0
P114/AN10/TIOA6_1
P113/TIOA5_1
P112/AN9/TIOA13_0
C
VSS
Document Number: 002-04632 Rev.*B
Page 6 of 92
S6J311A, S6J3119, S6J3118
3. Pin Description
This section provides a list of the pin functions of the S6J3110 series
Table 3-1. S6J311xHzC* Pin Functions
* x: A/9/8, z: A/B
Pin No.
S6J311xHAC
Pin Name
Polarity
I/O
Circuit
Type
Function
2
P000
SOT2_1
-
P
General-purpose I/O port
Multi-function serial ch.2 serial data output pin (1)
3
P001
SCS20_1
-
P
General-purpose I/O port
Multi-function serial ch.2 serial chip select 0 I/O pin (1)
4
P003
SCS22_1
-
P
General-purpose I/O port
Multi-function serial ch.2 serial chip select 2 output pin (1)
P005
IN6_0
SIN3_0
P006
IN7_0
SOT3_0
SDA3_0
P007
IN8_0
SCK3_0
SCL3_0
P008
IN9_0
SCS30_0
TIOA0_0
P009
IN10_0
TIOA1_0
INT0_1
P010
IN11_0
TIOA2_0
P012
TIOA3_0
OUT5_0
P013
TIOA4_0
OUT6_0
P015
TIOA5_0
OUT7_0
P016
TIOA6_0
OUT8_0
P017
TIOA7_0
OUT9_0
P018
TIOA8_0
OUT10_0
P019
OUT11_0
TIOB0_0
TEXT0_0
-
5
6
7
8
9
10
11
12
13
14
15
16
17
Document Number: 002-04632 Rev.*B
P
P
P
P
P
P
P
P
P
P
P
P
P
General-purpose I/O port
Input capture ch.6 input pin (0)
Multi-function serial ch.3 serial data input pin (0)
General-purpose I/O port
Input capture ch.7 input pin (0)
Multi-function serial ch.3 serial data output pin (0)
I2C bus ch.3 serial data I/O pin
General-purpose I/O port
Input capture ch.8 input pin (0)
Multi-function serial ch.3 clock I/O pin (0)
I2C bus ch.3 serial clock I/O pin
General-purpose I/O port
Input capture ch.9 input pin (0)
Multi-function serial ch.3 serial chip select 0 I/O pin (0)
Base timer ch.0 TIOA output pin (0)
General-purpose I/O port
Input capture ch.10 input pin (0)
Base timer ch.1 TIOA I/O pin (0)
INT0 external interrupt input pin (1)
General-purpose I/O port
Input capture ch.11 input pin (0)
Base timer ch.2 TIOA output pin (0)
General-purpose I/O port
Base timer ch.3 TIOA I/O pin (0)
Output compare ch.5 output pin (0)
General-purpose I/O port
Base timer ch.4 TIOA output pin (0)
Output compare ch.6 output pin (0)
General-purpose I/O port
Base timer ch.5 TIOA I/O pin (0)
Output compare ch.7 output pin (0)
General-purpose I/O port
Base timer ch.6 TIOA output pin (0)
Output compare ch.8 output pin (0)
General-purpose I/O port
Base timer ch.7 TIOA I/O pin (0)
Output compare ch.9 output pin (0)
General-purpose I/O port
Base timer ch.8 TIOA output pin (0)
Output compare ch.10 output pin (0)
General-purpose I/O port
Output compare ch.11 output pin (0)
Base timer ch.0 TIOB input pin (0)
Free-run timer 0 clock input pin (0)
Page 7 of 92
S6J311A, S6J3119, S6J3118
Pin No.
S6J311xHAC
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Pin Name
P020
SOT0_0
SDA0_0
TIOB1_0
TEXT1_0
P021
SCK0_0
SCL0_0
TIOB2_0
P022
SIN0_0
TIOB3_0
INT3_0
P023
SCS0_0
TIOB4_0
P024
TIOB5_0
P027
TIOA4_1
TIOB6_0
INT1_1
TEXT0_1
P028
SIN1_0
TIOB7_0
INT4_0
OUT0_1
P029
SOT1_0
SDA1_0
AN0
OUT1_1
P030
OUT2_1
P031
SCS1_0
AN1
OUT3_1
P100
SCK1_0
SCL1_0
AN2
OUT4_1
P101
AN3
OUT5_1
P103
AN5
OUT6_1
P105
TIOA9_0
OUT7_1
P106
OUT8_1
P107
TIOA10_0
INT2_1
OUT9_1
Document Number: 002-04632 Rev.*B
Polarity
-
I/O
Circuit
Type
P
P
P
P
P
P
P
A
P
A
A
A
A
P
P
P
Function
General-purpose I/O port
Multi-function serial ch.0 serial data output pin (0)
I2C bus ch.0 serial data I/O pin
Base timer ch.1 TIOB input pin (0)
Free-run timer 1 clock input pin (0)
General-purpose I/O port
Multi-function serial ch.0 clock I/O pin (0)
I2C bus ch.0 serial clock I/O pin
Base timer ch.2 TIOB input pin (0)
General-purpose I/O port
Multi-function serial ch.0 serial data input pin (0)
Base timer ch.3 TIOB input pin (0)
INT3 external interrupt input pin (0)
General-purpose I/O port
Multi-function serial ch.0 serial chip select I/O pin (0)
Base timer ch.4 TIOB input pin (0)
General-purpose I/O port
Base timer ch.5 TIOB input pin (0)
General-purpose I/O port
Base timer ch.4 TIOA output pin (1)
Base timer ch.6 TIOB input pin (0)
INT1 external interrupt input pin (1)
Free-run timer 0 clock input pin (1)
General-purpose I/O port
Multi-function serial ch.1 serial data input pin (0)
Base timer ch.7 TIOB input pin (0)
INT4 external interrupt input pin (0)
Output compare ch.0 output pin (1)
General-purpose I/O port
Multi-function serial ch.1 serial data output pin (0)
I2C bus ch.1 serial data I/O pin
ADC analog 0 input pin
Output compare ch.1 output pin (1)
General-purpose I/O port
Output compare ch.2 output pin (1)
General-purpose I/O port
Multi-function serial ch.1 serial chip select I/O pin (0)
ADC analog 1 input pin
Output compare ch.3 output pin (1)
General-purpose I/O port
Multi-function serial ch.1 clock I/O pin (0)
I2C bus ch.1 serial clock I/O pin
ADC analog 2 input pin
Output compare ch.4 output pin (1)
General-purpose I/O port
ADC analog 3 input pin
Output compare ch.5 output pin (1)
General-purpose I/O port
ADC analog 5 input pin
Output compare ch.6 output pin (1)
General-purpose I/O port
Base timer ch.9 TIOA I/O pin (0)
Output compare ch.7 output pin (1)
General-purpose I/O port
Output compare ch.8 output pin (1)
General-purpose I/O port
Base timer ch.10 TIOA output pin (0)
INT2 external interrupt input pin (1)
Output compare ch.9 output pin (1)
Page 8 of 92
S6J311A, S6J3119, S6J3118
Pin No.
S6J311xHAC
34
35
39
40
41
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
Pin Name
Polarity
P108
AN6
TIOA11_0
INT3_1
OUT10_1
P109
TIOA12_0
OUT11_1
P112
AN9
TIOA13_0
P113
TIOA5_1
P114
AN10
TIOA6_1
-
P115
-
P117
AN12
INT4_1
P118
AN13
INT5_1
P119
AN14
P120
AN15
P122
AN17
TIOA11_1
P123
AN18
TIOA12_1
P126
AN19
P127
AN20
TEXT1_1
P128
AN21
TEXT2_1
P129
IN6_1
AN22
P130
IN7_1
AN23
INT5_0
P131
IN8_1
AN24
P202
IN9_1
INT6_1
P203
IN10_1
-
Document Number: 002-04632 Rev.*B
I/O
Circuit
Type
A
P
A
P
A
P
A
A
A
A
A
A
A
A
A
A
A
A
P
P
Function
General-purpose I/O port
ADC analog 6 input pin
Base timer ch.11 TIOA I/O pin (0)
INT3 external interrupt input pin (1)
Output compare ch.10 output pin (1)
General-purpose I/O port
Base timer ch.12 TIOA output pin (0)
Output compare ch.11 output pin (1)
General-purpose I/O port
ADC analog 9 input pin
Base timer ch.13 TIOA I/O pin (0)
General-purpose I/O port
Base timer ch.5 TIOA I/O pin (1)
General-purpose I/O port
ADC analog 10 input pin
Base timer ch.6 TIOA output pin (1)
General-purpose I/O port
General-purpose I/O port
ADC analog 12 input pin
INT4 external interrupt input pin (1)
General-purpose I/O port
ADC analog 13 input pin
INT5 external interrupt input pin (1)
General-purpose I/O port
ADC analog 14 input pin
General-purpose I/O port
ADC analog 15 input pin
General-purpose I/O port
ADC analog 17 input pin
Base timer ch.11 TIOA I/O pin (1)
General-purpose I/O port
ADC analog 18 input pin
Base timer ch.12 TIOA output pin (1)
General-purpose I/O port
ADC analog 19 input pin
General-purpose I/O port
ADC analog 20 input pin
Free-run timer 1 clock input pin (1)
General-purpose I/O port
ADC analog 21 input pin
Free-run timer 2 clock input pin (1)
General-purpose I/O port
Input capture ch.6 input pin (1)
ADC analog 22 input pin
General-purpose I/O port
Input capture ch.7 input pin (1)
ADC analog 23 input pin
INT5 external interrupt input pin (0)
General-purpose I/O port
Input capture ch.8 input pin (1)
ADC analog 24 input pin
General-purpose I/O port
Input capture ch.9 input pin (1)
INT6 external interrupt input pin (1)
General-purpose I/O port
Input capture ch.10 input pin (1)
Page 9 of 92
S6J311A, S6J3119, S6J3118
Pin No.
S6J311xHAC
60
61
62
63
64
65
66
67
68
69
70
71
74
75
76
77
Pin Name
P204
IN11_1
AN27
P205
AN28
TEXT3_1
P206
AN29
TEXT4_1
P207
AN30
INT7_1
TEXT5_1
P208
AN31
TIOA19_0
P209
AN32
TIOA20_0
P210
IN0_2
AN33
TIOA21_0
INT6_0
P211
IN1_2
AN34
TIOA22_0
P212
IN2_2
AN35
TIOA13_1
P213
IN3_2
TIOA14_1
INT8_1
P214
IN4_2
TIOA15_1
P215
IN5_2
TIOA16_1
INT9_1
P218
AN36
TEXT2_0
P219
AN37
TEXT3_0
P220
IN6_2
AN38
P222
IN7_2
AN39
INT7_0
Document Number: 002-04632 Rev.*B
Polarity
-
I/O
Circuit
Type
A
A
A
A
A
A
A
A
A
P
P
P
A
A
A
A
Function
General-purpose I/O port
Input capture ch.11 input pin (1)
ADC analog 27 input pin
General-purpose I/O port
ADC analog 28 input pin
Free-run timer 3 clock input pin (1)
General-purpose I/O port
ADC analog 29 input pin
Free-run timer 4 clock input pin (1)
General-purpose I/O port
ADC analog 30 input pin
INT7 external interrupt input pin (1)
Free-run timer 5 clock input pin (1)
General-purpose I/O port
ADC analog 31 input pin
Base timer ch.19 TIOA I/O pin (0)
General-purpose I/O port
ADC analog 32 input pin
Base timer ch.20 TIOA output pin (0)
General-purpose I/O port
Input capture ch.0 input pin (2)
ADC analog 33 input pin
Base timer ch.21 TIOA I/O pin (0)
INT6 external interrupt input pin (0)
General-purpose I/O port
Input capture ch.1 input pin (2)
ADC analog 34 input pin
Base timer ch.22 TIOA output pin (0)
General-purpose I/O port
Input capture ch.2 input pin (2)
ADC analog 35 input pin
Base timer ch.13 TIOA I/O pin (1)
General-purpose I/O port
Input capture ch.3 input pin (2)
Base timer ch.14 TIOA output pin (1)
INT8 external interrupt input pin (1)
General-purpose I/O port
Input capture ch.4 input pin (2)
Base timer ch.15 TIOA I/O pin (1)
General-purpose I/O port
Input capture ch.5 input pin (2)
Base timer ch.16 TIOA output pin (1)
INT9 external interrupt input pin (1)
General-purpose I/O port
ADC analog 36 input pin
Free-run timer 2 clock input pin (0)
General-purpose I/O port
ADC analog 37 input pin
Free-run timer 3 clock input pin (0)
General-purpose I/O port
Input capture ch.6 input pin (2)
ADC analog 38 input pin
General-purpose I/O port
Input capture ch.7 input pin (2)
ADC analog 39 input pin
INT7 external interrupt input pin (0)
Page 10 of 92
S6J311A, S6J3119, S6J3118
Pin No.
S6J311xHAC
78
79
80
81
85
86
87
88
89
90
91
92
Pin Name
P223
IN8_2
AN40
PWU_AN0
P224
IN9_2
TX0_2
AN41
PWU_AN1
P225
IN10_2
RX0_2
AN42
PWU_AN2
INT0_0
P226
IN11_2
AN43
PWU_AN3
TIOA17_1
P227
AN44
PWU_AN4
TIOA23_0
P228
TX0_1
AN45
PWU_AN5
TIOA24_0
P229
RX0_1
AN46
PWU_AN6
TIOA25_0
INT8_0
OUT0_0
P230
AN47
PWU_AN7
TIOA26_0
OUT1_0
P231
AN48
TIOA27_0
OUT2_0
P300
AN49
TIOA28_0
OUT3_0
P301
AN50
TIOA18_1
OUT4_0
P302
AN51
TIOA19_1
Document Number: 002-04632 Rev.*B
Polarity
-
I/O
Circuit
Type
A
A
A
A
A
A
A
A
A
A
A
A
Function
General-purpose I/O port
Input capture ch.8 input pin (2)
ADC analog 40 input pin
Partial wakeup ADC analog 0 input pin
General-purpose I/O port
Input capture ch.9 input pin (2)
CAN transmission data 0 output pin (2)
ADC analog 41 input pin
Partial wakeup ADC analog 1 input pin
General-purpose I/O port
Input capture ch.10 input pin (2)
CAN reception data 0 input pin (2)
ADC analog 42 input pin
Partial wakeup ADC analog 2 input pin
INT0 external interrupt input pin (0)
General-purpose I/O port
Input capture ch.11 input pin (2)
ADC analog 43 input pin
Partial wakeup ADC analog 3 input pin
Base timer ch.17 TIOA I/O pin (1)
General-purpose I/O port
ADC analog 44 input pin
Partial wakeup ADC analog 4 input pin
Base timer ch.23 TIOA I/O pin (0)
General-purpose I/O port
CAN transmission data 0 output pin (1)
ADC analog 45 input pin
Partial wakeup ADC analog 5 input pin
Base timer ch.24 TIOA output pin (0)
General-purpose I/O port
CAN reception data 0 input pin (1)
ADC analog 46 input pin
Partial wakeup ADC analog 6 input pin
Base timer ch.25 TIOA I/O pin (0)
INT8 external interrupt input pin (0)
Output compare ch.0 output pin (0)
General-purpose I/O port
ADC analog 47 input pin
Partial wakeup ADC analog 7 input pin
Base timer ch.26 TIOA output pin (0)
Output compare ch.1 output pin (0)
General-purpose I/O port
ADC analog 48 input pin
Base timer ch.27 TIOA I/O pin (0)
Output compare ch.2 output pin (0)
General-purpose I/O port
ADC analog 49 input pin
Base timer ch.28 TIOA output pin (0)
Output compare ch.3 output pin (0)
General-purpose I/O port
ADC analog 50 input pin
Base timer ch.18 TIOA output pin (1)
Output compare ch.4 output pin (0)
General-purpose I/O port
ADC analog 51 input pin
Base timer ch.19 TIOA I/O pin (1)
Page 11 of 92
S6J311A, S6J3119, S6J3118
Pin No.
S6J311xHAC
Pin Name
I/O
Circuit
Type
Polarity
Function
P304
AN52
TIOA20_1
TEXT4_0
P305
AN53
TIOA29_0
TEXT5_0
-
NMIX
N
P306
TX0_0
AN54
P307
RX0_0
AN55
INT1_0
P308
IN0_1
AN56
TIOA28_1
P309
IN1_1
AN57
TIOA29_1
P312
IN2_1
AN58
P313
IN3_1
AN59
INT10_1
P314
IN4_1
AN60
TIOA7_1
P315
IN5_1
AN61
TIOA8_1
P317
AN62
TIOA9_1
INT11_1
P321
PWUTRG
TRST
P322
TDO
P323
TDI
P324
N
-
113
TMS
-
E
JTAG test mode state input pin
114
TCK
-
E
JTAG test clock input pin
115
P327
-
P
General-purpose I/O port
116
P330
-
P
General-purpose I/O port
93
94
95
96
97
98
99
100
101
102
103
104
107
110
111
112
Document Number: 002-04632 Rev.*B
A
A
F
A
A
A
A
A
A
A
A
A
R
J
I
D
General-purpose I/O port
ADC analog 52 input pin
Base timer ch.20 TIOA output pin (1)
Free-run timer 4 clock input pin (0)
General-purpose I/O port
ADC analog 53 input pin
Base timer ch.29 TIOA I/O pin (0)
Free-run timer 5 clock input pin (0)
Non-maskable interrupt input pin
General-purpose I/O port
CAN transmission data 0 output pin (0)
ADC analog 54 input pin
General-purpose I/O port
CAN reception data 0 input pin (0)
ADC analog 55 input pin
INT1 external interrupt input pin (0)
General-purpose I/O port
Input capture ch.0 input pin (1)
ADC analog 56 input pin
Base timer ch.28 TIOA output pin (1)
General-purpose I/O port
Input capture ch.1 input pin (1)
ADC analog 57 input pin
Base timer ch.29 TIOA I/O pin (1)
General-purpose I/O port
Input capture ch.2 input pin (1)
ADC analog 58 input pin
General-purpose I/O port
Input capture ch.3 input pin (1)
ADC analog 59 input pin
INT10 external interrupt input pin (1)
General-purpose I/O port
Input capture ch.4 input pin (1)
ADC analog 60 input pin
Base timer ch.7 TIOA I/O pin (1)
General-purpose I/O port
Input capture ch.5 input pin (1)
ADC analog 61 input pin
Base timer ch.8 TIOA output pin (1)
General-purpose I/O port
ADC analog 62 input pin
Base timer ch.9 TIOA I/O pin (1)
INT11 external interrupt input pin (1)
General-purpose output port
Partial wakeup trigger output pin
JTAG test reset input pin
General-purpose output port
JTAG test data output pin
General-purpose output port
JTAG test data input pin
General-purpose output port
Page 12 of 92
S6J311A, S6J3119, S6J3118
Pin No.
S6J311xHAC
Pin Name
Polarity
I/O
Circuit
Type
Function
117
MD
-
C
Mode pin
118
X0
-
G
Main clock oscillation input pin
119
X1
-
G
Main clock oscillation output pin
121
P331
-
P
General-purpose I/O port
122
P400
-
P
General-purpose I/O port
123
RSTX
N
F
External reset input pin
P401
IN0_0
P402
IN1_0
INT2_0
P403
IN2_0
TRACEDATA0
P404
IN3_0
TRACEDATA1
P405
IN4_0
INT11_0
TRACEDATA2
P406
TRACEDATA3
P407
TRACEDATA4
P408
SIN2_0
INT12_0
TRACEDATA5
P409
SOT2_0
SDA2_0
TIOA24_1
TRACEDATA6
P411
SCK2_0
SCL2_0
INT13_1
TRACEDATA7
P413
SCS20_0
INT14_1
P414
SCS21_0
P416
IN5_0
TIOA22_1
P417
TIOA23_1
INT15_1
P418
SCS22_0
INT14_0
-
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
Document Number: 002-04632 Rev.*B
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
General-purpose I/O port
Input capture ch.0 input pin (0)
General-purpose I/O port
Input capture ch.1 input pin (0)
INT2 external interrupt input pin (0)
General-purpose I/O port
Input capture ch.2 input pin (0)
Trace data 0 output pin
General-purpose I/O port
Input capture ch.3 input pin (0)
Trace data 1 output pin
General-purpose I/O port
Input capture ch.4 input pin (0)
INT11 external interrupt input pin (0)
Trace data 2 output pin
General-purpose I/O port
Trace data 3 output pin
General-purpose I/O port
Trace data 4 output pin
General-purpose I/O port
Multi-function serial ch.2 serial data input pin (0)
INT12 external interrupt input pin (0)
Trace data 5 output pin
General-purpose I/O port
Multi-function serial ch.2 serial data output pin (0)
I2C bus ch.2 serial data I/O pin
Base timer ch.24 TIOA output pin (1)
Trace data 6 output pin
General-purpose I/O port
Multi-function serial ch.2 clock I/O pin (0)
I2C bus ch.2 serial clock I/O pin
INT13 external interrupt input pin (1)
Trace data 7 output pin
General-purpose I/O port
Multi-function serial ch.2 serial chip select 0 I/O pin (0)
INT14 external interrupt input pin (1)
General-purpose I/O port
Multi-function serial ch.2 serial chip select 1 output pin (0)
General-purpose I/O port
Input capture ch.5 input pin (0)
Base timer ch.22 TIOA output pin (1)
General-purpose I/O port
Base timer ch.23 TIOA I/O pin (1)
INT15 external interrupt input pin (1)
General-purpose I/O port
Multi-function serial ch.2 serial chip select 2 output pin (0)
INT14 external interrupt input pin (0)
Page 13 of 92
S6J311A, S6J3119, S6J3118
Pin No.
S6J311xHAC
Pin Name
I/O
Circuit
Type
Polarity
Function
P420
SCK2_1
TRACECLK
P421
SIN2_1
TRACECTL
-
42
AVCC0
-
-
Analog power supply pin for AD converter unit 0
84
AVCC1
-
-
Analog power supply pin for AD converter unit 1
43
AVRH0
-
-
Upper-limit reference voltage pin for AD converter unit 0
83
AVRH1
-
-
Upper-limit reference voltage pin for AD converter unit 1
AVSS0
AVRL0
AVSS1
AVRL1
-
C
-
-
External capacity connection output pin
VCC
-
-
Power supply pin
VSS
-
-
GND
142
143
44
82
38
126
Q
Q
-
General-purpose I/O port
Multi-function serial ch.2 clock I/O pin (1)
Trace clock
General-purpose I/O port
Multi-function serial ch.2 serial data input pin (1)
Trace control
GND pin for AD converter unit 0
Lower-limit reference voltage pin for AD converter unit 0
GND pin for AD converter unit 1
Lower-limit reference voltage pin for AD converter unit 1
36
72
105
109
124
144
1
37
73
106
108
120
125
Document Number: 002-04632 Rev.*B
Page 14 of 92
S6J311A, S6J3119, S6J3118
4. I/O Circuit Types
This section explains I/O circuit types.
Type
A
Circuit
Pull-up control
Digital output
Digital output
Overview
General-purpose I/O port with analog input
Output of 1 mA or 2 mA selectable
50 kΩ with pull-up resistor control
50 kΩ with pull-down resistor control
CMOS hysteresis input
Pull-down control
CMOS input
PSS control
Analog input
B
Pull-up control
Digital output
Digital output
General-purpose I/O port with analog input
Output of 1 mA or 2 mA selectable
50 kΩ with pull-up resistor control
50 kΩ with pull-down resistor control
Automotive/CMOS hysteresis input selectable
Pull-down control
Automotive/
CMOS input
PSS control
Analog input
C
Mode input
CMOS hysteresis input
Mode
input
D
Pull-up control
Digital output
JTAG
General-purpose output port
Output of 2 mA
50 kΩ with pull-up resistor control
TTL input
Digital output
TTL input
Document Number: 002-04632 Rev.*B
Page 15 of 92
S6J311A, S6J3119, S6J3118
Type
E
Circuit
Pull-up control
Overview
JTAG
50 kΩ with pull-up resistor control
TTL input
TTL input
F
CMOS hysteresis input
50 kΩ with pull-up resistor
CMOS-hys input
G
Input
Main oscillation I/O
Standby
control
I
Digital output
JTAG
Output of 2 mA
Digital output
J
Digital output
Digital output
JTAG
General-purpose output port
Output of 2 mA
50 kΩ with pull-down resistor control
TTL input
Pull-down control
TTL input
P
Pull-up control
Digital output
Digital output
General-purpose I/O port
Output of 1 mA or 2 mA selectable
50 kΩ with pull-up resistor control
50 kΩ with pull-down resistor control
CMOS hysteresis input
Pull-down control
CMOS input
PSS control
Document Number: 002-04632 Rev.*B
Page 16 of 92
S6J311A, S6J3119, S6J3118
Type
Q
Circuit
Pull-up control
Digital output
Digital output
Overview
General-purpose I/O port
Output of 1 mA or 2 mA selectable
50 kΩ with pull-up resistor control
50 kΩ with pull-down resistor control
Automotive/CMOS hysteresis input selectable
Pull-down control
Automotive/
CMOS input
PSS control
Output of 2 mA
R
Digital output
Digital output
Document Number: 002-04632 Rev.*B
Page 17 of 92
S6J311A, S6J3119, S6J3118
5. Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in
which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to
minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.
5.1
Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical
characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely
affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their sales representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output
functions.
1.
Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device,
and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at
the design stage.
2. Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows.
Such conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.
3. Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be
connected through an appropriate resistance to a power supply pin or ground pin.
Document Number: 002-04632 Rev.*B
Page 18 of 92
S6J311A, S6J3119, S6J3118
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally
high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of
several hundred mA to flow continuously at the power supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or
damage from high heat, smoke or flame. To prevent this from happening, do the following:
1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal
noise, surge levels, etc.
2. Be sure that abnormal current flows do not occur during the power-on sequence.
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic
interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Precautions Related to Usage of Devices
Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office
equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.)
are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
5.2
Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you
should only mount under Cypress recommended conditions. For detailed information about mount conditions, contact your sales
representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or
mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow
soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected
to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress
recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact
deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be
verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed
or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections
caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of
mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended
conditions.
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength
may be reduced under some conditions of use.
Document Number: 002-04632 Rev.*B
Page 19 of 92
S6J311A, S6J3119, S6J3118
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of
moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing
moisture resistance and causing packages to crack. To prevent, do the following:
%ׁ◌ Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product.
Store products in locations where temperature changes are slight.
2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5 ˚C
and 30 ˚C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica
gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.
4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended
conditions for baking.
Condition: 125 ˚C/24 h
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions:
1. Maintain relative humidity in the working environment between 40% and 70%.
Use of an apparatus for ion generation may be needed to remove electricity.
2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1
MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is
recommended.
4. Ground all fixtures and instruments, or protect with anti-static measures.
5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.
5.3
Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
1. Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are
anticipated, consider anti-humidity processing.
2. Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases,
use anti-static measures or processing to prevent discharges.
3. Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If
you use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
4. Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide
shielding as appropriate.
5. Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices
begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with sales
representatives.
Document Number: 002-04632 Rev.*B
Page 20 of 92
S6J311A, S6J3119, S6J3118
6. Handling Devices
For Latch-up Prevention
The latch-up phenomenon may occur on a CMOS IC in the following cases: the voltage applied to an input or output pin is higher
than VCC or lower than VSS; or the voltage applied between a VCC pin and a VSS pin exceeds the rating. A latch-up causes a rapid
increase in the power supply current, possibly resulting in thermal damage to an element. When using the device, take sufficient
care not to exceed the maximum rating.
Also be careful that analog power supplies (AVCC0, AVCC1, AVRH0, and AVRH1) and analog inputs do not exceed the digital
power supply (VCC) at the analog system power-on and power-off times.
The power-on sequence is as follows. Simultaneously turn on the digital supply voltage (VCC) and analog supply voltages (AVCC0,
AVCC1, AVRH0, and AVRH1), or turn on the digital supply voltage (VCC) and then the analog supply voltages (AVCC0, AVCC1,
AVRH0, and AVRH1).
About Handling Unused Pins
Leaving unused input pins open may cause permanent damage from a malfunction or latch-up. Take measures for unused pins,
such as pulling up or pulling down the voltage with resistors of 2 kiloohms or higher.
If there are any unused input/output pins, set them to the output state and then open them, or set them to the input state and handle
them in the same way as input pins.
About Power Supply Pins
If the device has multiple VCC and VSS pins, the device is designed in such a way that the pins that should be at the same potential
are connected to each other inside the device to prevent malfunctions such as latch-up. However, to reduce unwanted emissions,
prevent malfunctions of strobe signals caused by an increase of the ground level, and observe standards on total output current, be
sure to connect all the VCC and VSS pins to the power source and ground externally. Also handle all the VSS power supply pins in
this way as shown in the following diagram. If there are multiple VCC or VSS systems, the device does not operate normally even
within the guaranteed operating range.
Figure 6-1. Pin Assignment
In addition, consider connecting with low impedance from the power supply source to the VCC and VSS of this device.
In the area close to this device, a ceramic capacitor having the capacitance larger than the capacitor of C pin is recommended to
use as a bypass capacitor between the VCC pin and the VSS pin.
About the Crystal Oscillation Circuit
Noise entering the X0 or X1 pin may cause a malfunction. Design the printed circuit board in such a way that the X0 and X1 pins, the
crystal oscillator (or ceramic resonator), and a bypass capacitor to ground are located very close to the device.
We recommend that the printed circuit board artwork have the X0 and X1 pins enclosed by ground.
Document Number: 002-04632 Rev.*B
Page 21 of 92
S6J311A, S6J3119, S6J3118
About the Mode Pin (MD)
Use mode pin MD by directly connecting it to a VCC or VSS pin. To prevent noise from causing the device to accidentally enter test
mode, reduce the pattern length between each mode pin and a VCC or VSS pin on the printed circuit board, and connect them with
low impedance.
About the Power-on Time
To prevent a malfunction of the voltage step-down circuit built in the device, the voltage rising must be monotonic during power-on.
Point to Note during PLL Clock Operation
While a PLL clock is selected, if the oscillator breaks off or input stops, the PLL clock may continue operating with the free running
frequency of the internal self-oscillator circuit. This operation is outside of the guaranteed range.
Power Supply Pin Processing of an A/D Converter
Even when no A/D converter is used, establish a connection such that AVCC=AVRH=VCC and AVSS/AVRL=VSS.
Points to Note about Using External Clocks
External clocks are not supported.
External direct clock input cannot be used.
Power-on Sequence of the Power Supply Analog Inputs of an A/D Converter
Be sure to turn on the digital power supply (VCC) before the application of the power supplies (AVCC, AVRH, and AVRL) and analog
inputs (AN0 to AN3, AN5, AN6, AN9, AN10, AN12 to AN15, AN17 to AN24, and AN27 to AN62) of an A/D converter.
At the power-off time, turn off the power supplies and analog inputs of the A/D converter, and then turn off the digital power supply
(VCC). Perform these power-on and power-off operations without AVRH exceeding AVCC. Even when using a pin shared with an
analog input as an input port, do not allow the input voltage to exceed AVCC. (Turning on or off the analog supply voltage and digital
supply voltage simultaneously is not a problem.)
About C Pin Processing
This device has a built-in voltage step-down circuit. Be sure to connect a capacitor to the C pin (pin 126 in S6J311xHzC*
specifications) for internal stabilization of the device. For the standard values, see "Recommended operating conditions" in the
latest data sheet.
*x: A/9/8, z: A/B
Precautions on Designing a Mounting Substrate
Measures against heat generation from the package must be taken for the mounting substrate to observe the absolute maximum
rating (operating temperature). Design a mounting substrate with 4 or more layers. Connect the back of the package stage and the
substrate pad with solder paste. Arrange thermal via holes on the substrate pad. For detailed information about mount conditions,
contact your sales representative.
Notes on Writing to a Register Containing a Status Flag
In writing to a register containing a status flag (particularly an interrupt request flag, etc.) to control a function, it is important to take
care not to accidentally clear the status flag.
Therefore, before the write operation, configure the status bit such that the flag is not cleared, and then set the control bit to the
desired value.
Especially for control bits configured as a set of multiple bits, bit instructions cannot be used (bit instructions have only 1-bit access).
In such cases, byte, half-word, or word access is used to write to the control bits and a status flag simultaneously. However, at this
time, be careful not to accidentally clear bits other than the intended ones (the status flag bit in this case).
Note: Bit instructions take this point into account for registers that support bit-band units, so it does not need to be a concern. You
need to take care when using bit instructions for registers that do not support bit-band units.
Document Number: 002-04632 Rev.*B
Page 22 of 92
S6J311A, S6J3119, S6J3118
7. Block Diagram
This section provides block diagrams of the S6J3110 series.
Figure 7-1. S6J311xHzC* Block Diagram
* x: A/9/8, z: A/B
Trace I/F(8Pin)
Debug I/F (JTAG/SWD)
Power Domain 2
JTAG_SWCLKTCK
JTAG Wakeup
Debug Group
(CoreSightTM)
Bus Config Group
From/To PPU-SLAVEs
- Bus Performance Counters
- Misc Register Module
DAP
CLK_DBG
CLK_LLPBM2
Security
APB-M
PPU Master
APB-S
AHB-M
CLK_HPM
Debug APB
CLK_HPM
Trace Group
CLK_CPU
CLK_DBG
ATB
CLK_ATB
Core Group (1-Core)
Power Domain 3
Security
Checker
ETB (Trace Buffer)
16KB
CLK_TRC
From/To
CommonPERI#2
From/To
CommonPERI#2
AHB2APB
(Priviledge
Protection)
APB-32
CLK_LLPBM2
Debug APB
TCFLASH #0
1MB/768KB/521KB + 64KB
+
WORK FLASH #0
48KB
WorkFlash
TCF
AHB-64
AHB-64
(Reg & Data) (Reg)
AHB-64
CLK_MEMC
AXI-64
CLK_SHE
CLK_SHE
TCF
AXI-64
(data)
CLK_MEMC
CLK_FCLK
CLK_SHE
CLK_CPU
Flash Group
SHE Group
AHB-32
From/To
Memory Config Grp.
ETMTM
#0
TCF
ATCM #0
TCRAM #0
(2bank)
64KB
(32KB×2)/
48KB
(24KB×2)/
32KB
(16KB×2)
AXI-64
CPU #0
B0TCM
- DMAC 16.ch
- ReloadTimer 4ch
CLK_DMA
MPU
#0
AXI-64
CLK_CPU
D$
#0
I$
#0
16KB
16KB
CLK_HPM
LLPP
AXI32-M AHB32
AXI-M AXI-S
CLK_CPU
DMAC Complex #0
CortexTM -R5
B1TCM
#0
ATCM
#0
AHB-64
CLK_MEMC
From/To
Memory Config Grp.
Procceser
AXI-64
CLK_CPU
AXI-32
CLK_CPU
From/To CommonPERI#2
DMAC Config
AHB-32
CLK_CPU
AHB-64
CLK_HPM
AHB-32
CLK_HPM2
AHB-32
CLK_HPM2
High Performance Matrix (HPM)
AXI-64
CLK_HPM
System SRAM
16KB
AHB-32
AXI-64
AHB-32
CLK_HPM
CLK_SYSC1
EAM
CLK_MEMC
CLK_HPM
AHB-32
CLK_CPU
AHB-64
CLK_HPM
From/To
Flash Group
BBU
BBU
AHB-32
CLK_LLPBM
Low Latency Peripheral Bus Matrix (LLPBM)
AHB-32
CLK_LLPBM
AHB-32
BBU
BBU
CLK_SYSC0H
Power Domain 6_0
System
Controller(SYSC)
（CLK_CAN）
CLK_LCP
BootROM
16KB
SW-Watchdog
CSV(for PLL)
Timing
Protection
(TPU) #0
SYSC1
CLK_SYSC1
Power manage
Source Clock
Timer
LVD
CSV
Fast-CR
Slow-CR
PLL0
SSCG PLL0
CLK_MEMC
State manage
CANFD_CCLK
CLK_LCP0A
Base Timer
30ch
P
M.F.S
4ch
Wakeup
Request #0
From/To
DMAC Complex
#0
32Bit FRT
6ch
#0 TCRAM
(Config)
32Bit ICU
12ch
From/To
PPU Master
32Bit OCU
12ch
Memory & Config Group
CLK_MEMC
Power Domain 3
C
Peripheral
Bus Bridge
RAM
RAM
PONR
CLK_LCP0A
CAN-FD
1ch
IRC #0
512 Vectors
Clock manage
EICU 16ch
Backup RAM 4KB
(8+5 bit width RAM x 4)
Power CLK_RAM1H
Domain 4_1
CAN prescaler
Backup RAM 4KB
(8+5 bit width RAM x 4)
Power CLK_RAM0H
Domain 4_0
Reset manage
CLK_LLPBM
CLK_LLPBM
Flash Group I/F
Clock divide
and distribution
CLK_COMH
ECC-ed RAM I/F
State manage (2)
From/To
Core-Group
AHB-32
CLK_LLPBM
BBU
Common PERI #0
Group
12Bit A/DC
Unit0×25ch
Common PERI
#1
Group
Peripheral
Bus Bridge
Peripheral
Bus Bridge
CLK_HPM
CLK_LLPBM2
CRC
4ch
BusPConfig
Group
(Config)
GPIO
DMAC
Complex #0
(Config)
From/To
Bus Config Group
PPU Master
(Cnofig)
Common PERI #2
Group
Wakeup-detect
RTC
Clock Calibration
H/W Watchdog
EXT-IRQ
16ch
Partial Wake up
12Bit A/DC
Unit1×31ch
Common PERI #0
Group
Power Domain 1 (Always on)
NMI
MCU Config Group
Power Domain 1
(Always on)
Document Number: 002-04632 Rev.*B
Page 23 of 92
S6J311A, S6J3119, S6J3118
8. Memory Map
This section explains the memory map.
Figure 8-1. Memory Map (S6J311AHzC/9HzC/8HzC*)
* z: A/B
S6J311AHzC*
Address
START
END
group
0x0000_0000
0x0000_7FFF
0x0000_8000
0x0000_BFFF
0x0000_C000
0x0000_FFFF
0x0001_0000
0x007F_FFFF
0x0080_0000
0x009E_FFFF
part
TCRAM
(Main 64KByte)
(Main 48KByte)
(Main 32KByte)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
TCM_FLASH
TCM_FLASH
TCM_FLASH
0x009F_FFFF
(Small Sector 8KByte×8)
(Small Sector 8KByte×8)
(Small Sector 8KByte×8)
TCM_FLASH
TCM_FLASH
TCM_FLASH
0x00A7_FFFF
(Code 1MByte)
(Code 768KByte)
(Code 512KByte)
0x00A0_0000
0x00A8_0000
0x00AB_FFFF
0x00AC_0000
0x00AF_FFFF
Reserved
Internal area for CR5
Complex
0x00B0_0000
0x00DF_FFFF
0x00E0_0000
0x00FF_FFFF
0x0100_0000
0x019E_FFFF
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
AXI_FLASH_MEMORY
AXI_FLASH_MEMORY
AXI_FLASH_MEMORY
0x019F_FFFF
(Small Sector 8KByte×8 *Mirror)
(Small Sector 8KByte×8 *Mirror)
(Small Sector 8KByte×8 *Mirror)
AXI_FLASH_MEMORY
AXI_FLASH_MEMORY
AXI_FLASH_MEMORY
0x01A7_FFFF
(Code 1MByte *Mirror)
(Code 768KByte *Mirror)
(Code 512KByte *Mirror)
0x019F_0000
0x01A0_0000
0x01A8_0000
0x01AB_FFFF
0x01AC_0000
0x01AF_FFFF
Reserved
0x01B0_0000
0x01DF_FFFF
0x01FF_FFFF
0x0200_0000
0x0200_3FFF
0x0200_4000
S6J3118HzC*
part
TCRAM
Reserved
0x009F_0000
0x01E0_0000
S6J3119HzC*
part
TCRAM
0x0203_FFFF
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SYSTEM SRAM
SYSTEM SRAM
SYSTEM SRAM
(16KByte)
(16KByte)
(16KByte)
Reserved
Reserved
Reserved
0x0204_0000
0x027F_FFFF
Reserved
Reserved
Reserved
0x0280_0000
0x0280_002F
Exclusive Access Memory
Exclusive Access Memory
Exclusive Access Memory
0x0280_0030
0x03FF_FFFF
Reserved
Reserved
Reserved
0x0400_0000
0x05FF_FFFF
AXI_SLAVE_CORE0
AXI_SLAVE_CORE0
AXI_SLAVE_CORE0
Reserved
Reserved
Reserved
0x0600_0000
0x0DFF_FFFF
0x0E00_0000
WORK_FLASH
WORK_FLASH
WORK_FLASH
0x0E00_BFFF
(48KByte mirror area 1)
(48KByte mirror area 1)
(48KByte mirror area 1)
0x0E00_C000
0x0E01_BFFF
Reserved
Reserved
Reserved
0x0E01_C000
0x0E0F_FFFF
Reserved
Reserved
0x0E10_0000
0x0E1F_FFFF
Reserved
Reserved
Reserved
WORK_FLASH
WORK_FLASH
WORK_FLASH
(48KByte mirror area 3)
0x0E20_0000
Shared Flash and memory
area
Reserved
0x0E20_BFFF
(48KByte mirror area 3)
(48KByte mirror area 3)
0x0E20_C000
0x0E21_BFFF
Reserved
Reserved
0x0E21_C000
0x0E2F_FFFF
Reserved
Reserved
Reserved
WORK_FLASH
WORK_FLASH
WORK_FLASH
0x0E30_0000
Reserved
0x0E30_BFFF
(48KByte mirror area 4)
(48KByte mirror area 4)
(48KByte mirror area 4)
0x0E30_C000
0x0E31_BFFF
Reserved
Reserved
Reserved
0x0E31_C000
0x0E3F_FFFF
Reserved
Reserved
0x0E40_0000
0x0E7F_FFFF
Reserved
Reserved
Reserved
Reserved
Backup RAM
Backup RAM
Backup RAM
0x0E80_1FFF
8KByte
8KByte
8KByte
0x0E80_2000
0x0E80_FFFF
Reserved
Reserved
Reserved
0x0E81_0000
0x0E87_FFFF
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x0E80_0000
0x0E88_0000
0x0FFF_FFFF
0x1000_0000
Reserved
0xAFFF_FFFF
0xB000_0000
0xB483_FFFF
Peri_area
Peri_area
Peri_area
0xB484_0000
0xB484_FFFF
APPS#5
APPS#5
APPS#5
Peri_area
Peri_area
Peri_area
Reserved
Reserved
Reserved
0xB485_0000
Peri area
0xB7FF_FFFF
0xB800_0000
Reserved
0xFFFE_DFFF
0xFFFE_E000
0xFFFE_FFFF
0xFFFF_0000
0xFFFF_3FFF
0xFFFF_4000
0xFFFF_FFFF
Document Number: 002-04632 Rev.*B
ERRCFG
BootROM
ERRCFG
ERRCFG
ERRCFG
BootROM
BootROM
BootROM
Reserved
Reserved
Reserved
Page 24 of 92
S6J311A, S6J3119, S6J3118
Only the CPU core can access 0000_0000 ~ 01FF_FFFF. Bus masters other than the CPU core cannot access the region.
Internal area of CR5 complex (0000_0000 ~ 01FF_FFFF) is mapped to AXI_SLAVE_CORE0. All bus masters can access to internal
area of CR5 complex via AXI_SLAVE_CORE0.
In each of the following memory area combinations, the areas are physically the same memory area.
1. TCM FLASH (0x00A0_0000 -) and AXI FLASH MEMORY (0x01A0_0000 -)
2. TCM FLASH Small Sector (0x009F_0000 -) and AXI FLASH MEMORY Small Sector (0x019F_0000 -)
3. WORKFLASH (0x0E00_0000 -), WORKFLASH (0x0E20_0000 -), and WORKFLASH (0x0E30_0000 -)
The ECC movement in TCM port is based on ECC setting inside the CPU.
The differences between the TCM FLASH and AXI FLASH include the following.
Function
High-speed Access Using Dedicated Bus
Write and Erase
Read
TCM FLASH
Applicable
Not applicable
(Read-only)
Applicable
AXI FLASH
Not applicable
Applicable
Applicable
The differences between WORKFLASH areas include the following.
Area
WORKFLASH Area 1
WORKFLASH Area 3
WORKFLASH Area 4
Terms are as follows.
TCM RAM
TCM FLASH
AXI FLASH
Term
SYSTEM RAM
AXI SLAVE CORE
WORKFLASH
BACKUP RAM
Peri area
APPS#5
ERRCFG
BootROM
Document Number: 002-04632 Rev.*B
Function
Used in write operation (with ECC)
Used in write operation (without ECC)
Used in read operation
Description
Main RAM
Program FLASH (TCM area)
Program FLASH (AXI area)
This is physically the same as the TCM FLASH.
System RAM
AXI CPU control area
FLASH for work
Backup RAM
Entire area for peripheral functions
Part of area for peripheral functions
Error configuration area
ROM for reset boot
Page 25 of 92
S6J311A, S6J3119, S6J3118
S6J311xHzC* Peripheral Map
* x: A/9/8, z:A/B
START
Address
B000_0000
B010_8000
B010_8100
B030_0000
B030_8000
B040_0000
B040_8000
B041_0000
B041_1000
B041_2000
B041_2100
B050_0000
B060_0000
B060_0080
B060_0100
B060_0180
B060_0200
B060_0280
B060_0300
B060_0380
B060_0400
B060_0480
B060_0500
B060_0600
B060_0680
B060_0700
B060_0800
B060_C000
B061_0000
B061_8000
B062_0000
B064_0000
B066_0000
B068_0000
B068_8000
B068_8400
B068_8800
B068_8C00
B069_0000
B070_0000
B080_0000
B100_0000
B110_0000
B120_0000
B200_0000
B210_0000
B470_0000
B470_4000
B471_0000
B471_1000
B471_4000
B471_5000
B471_8000
B471_8400
B471_8800
B471_8C00
B471_9000
B473_8000
B474_0000
B474_8000
B475_0000
B475_8000
B478_FC00
B479_0000
END
Address
B010_7FFF
B010_80FF
B02F_FFFF
B030_7FFF
B03F_FFFF
B040_7FFF
B040_FFFF
B041_0FFF
B041_1FFF
B041_20FF
B04F_FFFF
B05F_FFFF
B060_007F
B060_00FF
B060_017F
B060_01FF
B060_027F
B060_02FF
B060_037F
B060_03FF
B060_047F
B060_04FF
B060_05FF
B060_067F
B060_06FF
B060_07FF
B060_BFFF
B060_FFFF
B061_7FFF
B061_FFFF
B063_FFFF
B065_FFFF
B067_FFFF
B068_7FFF
B068_83FF
B068_87FF
B068_8BFF
B068_FFFF
B06F_FFFF
B07F_FFFF
B0FF_FFFF
B10F_FFFF
B11F_FFFF
B1FF_FFFF
B20F_FFFF
B46F_FFFF
B470_3FFF
B470_FFFF
B471_0FFF
B471_3FFF
B471_4FFF
B471_7FFF
B471_83FF
B471_87FF
B471_8BFF
B471_8FFF
B473_7FFF
B473_FFFF
B474_7FFF
B474_FFFF
B475_7FFF
B478_FBFF
B478_FFFF
B47F_FFFF
Group
SystemSRAM
SYSC1
SYSC1
MEMORY_CONFIG_GROUP
MEMORY_CONFIG_GROUP
MEMORY_CONFIG_GROUP
MEMORY_CONFIG_GROUP
MEMORY_CONFIG_GROUP
MCU_CONFIG_GROUP
MCU_CONFIG_GROUP
MCU_CONFIG_GROUP
MCU_CONFIG_GROUP
MCU_CONFIG_GROUP
MCU_CONFIG_GROUP
MCU_CONFIG_GROUP
MCU_CONFIG_GROUP
MCU_CONFIG_GROUP
MCU_CONFIG_GROUP
MCU_CONFIG_GROUP
MCU_CONFIG_GROUP
MCU_CONFIG_GROUP
MCU_CONFIG_GROUP
MCU_CONFIG_GROUP
MCU_CONFIG_GROUP
MCU_CONFIG_GROUP
MCU_CONFIG_GROUP
MCU_CONFIG_GROUP
MCU_CONFIG_GROUP
MCU_CONFIG_GROUP
MCU_CONFIG_GROUP
MCU_CONFIG_GROUP
Bit RMW alias
Bit RMW alias
Bit RMW alias
SHE
CommonPERI #2
CommonPERI #2
CommonPERI #2
CommonPERI #2
CommonPERI #2
CommonPERI #2
CommonPERI #2
CommonPERI #2
CommonPERI #2
CommonPERI #2
CommonPERI #2
Document Number: 002-04632 Rev.*B
Function
Reserved
SystemSRAM registers
Reserved
System Controller #1
SWDT
IRC0
TPU0
TCRAM Control Status Register
TCFlash Control Status Register
WFlash Control Status Register
Reserved
Reserved
Protection register area
RUN profile register area
PSS profile register area
APP profile register area
STS profile register area
System register area
CSV
RESET
SCT(Fast CR)
SCT(Slow CR)
SCT(Main clock)
Clock System
Special register area
Debug register area
Mode
HWDT
Reserved
RTC
EIC
Reserved
Reserved
BURAMIF
EICU
CR_Calibration
IRQ all
CAN Prescaler
Reserved
Reserved
Bit RMW alias for MCU config Gr (Covers B060_0000 -- B06F_FFFF)
Bit RMW alias for SYSC1 (Covers B030_0000 -- B031_FFFF)
Bit RMW alias for MEMC (Covers B040_0000 -- B041_FFFF)
Reserved
SHE configuration registers
Reserved
DMAC #0 registers
Reserved
MPU for DMAC#0
Reserved
DMA Complex #0 registers (Additional registers, RLTs)
Reserved
CRC#0
CRC#1
CRC#2
CRC#3
Reserved
GPIO
PPC
RIC
PPU
Reserved
Reserved
Reserved
PPU No
21
19
16
17
18
34
33
35
32
37
38
42
43
63
64
66
68
70
71
72
73
74
75
76
-
Page 26 of 92
S6J311A, S6J3119, S6J3118
START
Address
B480_0000
B480_0400
B480_0800
B480_0C00
B480_1000
B480_8000
B480_8400
B480_8800
B480_8C00
B480_9000
B480_9400
B480_9800
B480_9C00
B480_A000
B480_A400
B480_A800
B480_AC00
B480_B000
B482_0000
B482_0400
B482_0800
B482_0C00
B482_1000
B482_1400
B482_1800
B482_8000
B482_8400
B482_8800
B482_8C00
B482_9000
B482_9400
B482_9800
B483_0000
B483_0400
B483_0800
B483_0C00
B483_1000
B483_1400
B483_1800
B483_FC00
B484_0000
B485_0000
B48A_0000
B48B_1000
B48B_FC00
B48C_0000
B490_0000
B491_0000
B4C0_0000
B500_0000
B600_0000
B700_0000
B780_0000
B7C0_0000
B800_0000
FFFE_E000
FFFE_FC00
END
Address
B480_03FF
B480_07FF
B480_0BFF
B480_0FFF
B480_7FFF
B480_83FF
B480_87FF
B480_8BFF
B480_8FFF
B480_93FF
B480_97FF
B480_9BFF
B480_9FFF
B480_A3FF
B480_A7FF
B480_ABFF
B480_AFFF
B481_FFFF
B482_03FF
B482_07FF
B482_0BFF
B482_0FFF
B482_13FF
B482_17FF
B482_7FFF
B482_83FF
B482_87FF
B482_8BFF
B482_8FFF
B482_93FF
B482_97FF
B482_FFFF
B483_03FF
B483_07FF
B483_0BFF
B483_0FFF
B483_13FF
B483_17FF
B483_FBFF
B483_FFFF
B484_FFFF
B489_FFFF
B48B_0FFF
B48B_FBFF
B48B_FFFF
B48F_FFFF
B490_FFFF
B4BF_FFFF
B4FF_FFFF
B5FF_FFFF
B6FF_FFFF
B77F_FFFF
B7BF_FFFF
B7FF_FFFF
FFFE_DFFF
FFFE_FBFC
FFFE_FFFF
Group
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
CommonPERI #0
APPS #5
CommonPERI #0
Bit RMW alias
Bit RMW alias
Bit RMW alias
Error Config
Error Config
Document Number: 002-04632 Rev.*B
Function
M.F.Serial ch.0
M.F.Serial ch.1
M.F.Serial ch.2
M.F.Serial ch.3
Reserved
BaseTimer ch.0
BaseTimer ch.1
BaseTimer ch.2
BaseTimer ch.3
BaseTimer ch.4
BaseTimer ch.5
BaseTimer ch.6
BaseTimer ch.7
BaseTimer ch.8
BaseTimer ch.9
BaseTimer ch.10
BaseTimer ch.11
Reserved
FRT ch.0
FRT ch.1
FRT ch.2
FRT ch.3
FRT ch.4
FRT ch.5
Reserved
ICU ch.0 / ch.1
ICU ch.2 / ch.3
ICU ch.4 / ch.5
ICU ch.6 / ch.7
ICU ch.8 / ch.9
ICU ch.10 / ch.11
Reserved
OCU ch.0 / ch.1
OCU ch.2 / ch.3
OCU ch.4 / ch.5
OCU ch.6 / ch.7
OCU ch.8 / ch.9
OCU ch.10 / ch.11
Reserved
Reserved
APPS#5 area
Reserved
Reserved
Reserved
Reserved
Reserved
CAN_FD ch.0
Reserved
Bit RMW alias for CPERI#0(Covers B490_0000 -- B497_FFFF)
Reserved
Reserved
Bit RMW alias for CPERI#2 (Covers B470_0000 -- B47F_FFFF)
Bit RMW alias for CPERI#0 (Covers B480_0000 -- B487_FFFF)
Reserved
Reserved
IRC
BootROM I/F
PPU No
176
177
178
179
88
89
90
91
92
93
94
95
96
97
98
99
208
209
210
211
212
213
224
225
226
227
228
229
240
241
242
243
244
245
256
20
Page 27 of 92
S6J311A, S6J3119, S6J3118
APPS#5 area
START
Address
B484_0000
B484_3800
B484_3C00
B484_4000
B484_4400
B484_4800
B484_4C00
B484_5000
B484_5400
B484_5800
B484_5C00
B484_6000
B484_6400
B484_6800
B484_6C00
B484_7000
B484_7400
B484_7800
B484_7C00
B484_8000
B484_8400
B484_8800
B484_8C00
B484_9000
B484_9400
END
Address
B484_37FF
B484_3BFF
B484_3FFF
B484_43FF
B484_47FF
B484_4BFF
B484_4FFF
B484_53FF
B484_57FF
B484_5BFF
B484_5FFF
B484_63FF
B484_67FF
B484_6BFF
B484_6FFF
B484_73FF
B484_77FF
B484_7BFF
B484_7FFF
B484_83FF
B484_87FF
B484_8BFF
B484_8FFF
B484_93FF
B484_FFFF
Group
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
APPS #5
Function
Reserved
BaseTimer ch.12
BaseTimer ch.13
BaseTimer ch.14
BaseTimer ch.15
BaseTimer ch.16
BaseTimer ch.17
BaseTimer ch.18
BaseTimer ch.19
BaseTimer ch.20
BaseTimer ch.21
BaseTimer ch.22
BaseTimer ch.23
BaseTimer ch.24
BaseTimer ch.25
BaseTimer ch.26
BaseTimer ch.27
BaseTimer ch.28
BaseTimer ch.29
A/D unit0
A/D unit1 , Partial Wake Up
A/D analog input control
Reserved
Global Timer
Reserved
PPU No
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
300
-
When MPU attribute of Cortex®-R5 is configured as "Normal", store buffer inside Cortex®-R5 can operate and write data can be
merged. To avoid influence of this data merger, MPU attribute "Device" or "Strongly Ordered" should be used.
MPU attribute "Device" or "Strongly Ordered" must be used for areas below, to avoid this influence.
−
Backup RAM area (BACKUP_RAM) [0E80_0000 ~ 0E87_FFFF]
−
Peripheral area (Peri area) [B000_0000 ~ B7FF_FFFF]
−
Error Config area (ERRCFG) [FFFE_E000 ~ FFFE_FFFF]
MPU attribute "Device" or "Strongly Ordered" is required for accesses to areas below, in particular situation.
−
FLASH Memory (when writing commands)
SHE OFF product is prohibited to access SHE area (B200_0000 to B20F_FFFF)
Document Number: 002-04632 Rev.*B
Page 28 of 92
S6J311A, S6J3119, S6J3118
9. Pin Status in CPU Status
Table 9-1. Pin State Table (1/2)
External Reset Factor 2
2
P000/SOT2_1
3
P001/SCS20_1
4
P003/SCS22_1
5
P005/IN6_0/SIN3_0
6
P006/SOT3_0/SDA3_0/IN7_0
7
P007/SCK3_0/SCL3_0/IN8_0
8
P008/IN9_0/SCS30_0/TIOA0_0
9
P009/IN10_0/TIOA1_0/INT0_1
10
P010/IN11_0/TIOA2_0
11
P012/OUT5_0/TIOA3_0
12
P013/OUT6_0/TIOA4_0
13
P015/OUT7_0/TIOA5_0
14
P016/OUT8_0/TIOA6_0
15
P017/OUT9_0/TIOA7_0
16
P018/OUT10_0/TIOA8_0
17
P019/OUT11_0/TIOB0_0/TEXT0_0
18
P020/SOT0_0/SDA0_0/TEXT1_0/TIOB1_0
19
P021/SCK0_0/SCL0_0/TIOB2_0
20
P022/SIN0_0/TIOB3_0/INT3_0
21
P023/SCS0_0/TIOB4_0
22
P024/TIOB5_0
23
P027/TIOA4_1/TIOB6_0/INT1_1/TEXT0_1
24
P028/OUT0_1/SIN1_0/TIOB7_0/INT4_0
25
P029/AN0/SOT1_0/SDA1_0/OUT1_1
26
P030/OUT2_1
27
P031/OUT3_1/SCS1_0/AN1
28
P100/AN2/SCK1_0/SCL1_0/OUT4_1
29
P101/OUT5_1/AN3
30
P103/OUT6_1/AN5
31
P105/OUT7_1/TIOA9_0
32
P106/OUT8_1
33
P107/OUT9_1/TIOA10_0/INT2_1
34
P108/OUT10_1/AN6/TIOA11_0/INT3_1
35
P109/OUT11_1/TIOA12_0
39
P112/AN9/TIOA13_0
40
P113/TIOA5_1
41
P114/AN10/TIOA6_1
45
P115
46
P117/AN12/INT4_1
47
P118/AN13/INT5_1
48
P119/AN14
49
P120/AN15
50
P122/AN17/TIOA11_1
51
P123/AN18/TIOA12_1
52
P126/AN19
53
P127/AN20/TEXT1_1
54
P128/AN21/TEXT2_1
55
P129/IN6_1/AN22
56
P130/IN7_1/AN23/INT5_0
57
P131/IN8_1/AN24
58
P202/IN9_1/INT6_1
59
P203/IN10_1
60
P204/IN11_1/AN27
61
P205/AN28/TEXT3_1
62
P206/AN29/TEXT4_1
63
P207/AN30/INT7_1/TEXT5_1
64
P208/AN31/TIOA19_0
65
P209/AN32/TIOA20_0
66
P210/IN0_2/AN33/TIOA21_0/INT6_0
67
P211/IN1_2/AN34/TIOA22_0
68
P212/IN2_2/AN35/TIOA13_1
69
P213/IN3_2/TIOA14_1/INT8_1
70
P214/IN4_2/TIOA15_1
71
P215/IN5_2/TIOA16_1/INT9_1
With control
Document Number: 002-04632 Rev.*B
Hi-Z/Input blocked
Hi-Z/
Last status
retained
Hi-Z/Input
blocked
Hi-Z/Input blocked
Hi-Z/Input blocked
Status immediately
before the shutdown
retaine
Last state
retained
Last state
retained (*3)
Timer mode *4
High impedance enabled
(SYSC0_SPECFGR.
PSSPADCTRL=1)
High impedance disabled
(SYSC0_SPECFGR.
PSSPADCTRL=0)
High impedance enabled
(SYSC0_SPECFGR.
PSSPADCTRL=1)
Stop mode *4
High impedance disabled
(SYSC0_SPECFGR.
PSSPADCTRL=0)
CPU Sleep
Sleep mode
Internal Reset Factor
*2
After internal reset
issuance
(Before GPORT setting)
External Reset
Factor 3
Internal reset issuance
in progress
After Releasing
External Factor
After internal reset
issuance
(Before GPORT setting)
Internal reset issuance
in progress
While Generating External
Factor
Before internal reset
issuance
After internal reset
issuance
(Before GPORT setting)
Internal reset issuance
in progress
GPORTEN
Control
Internal reset issuance
in progress
Pin No.
Pin Name
After external
factor releasing
Internal reset issuance
in progress
External Reset Factor 1
External
factor
generation
in progress
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Hi-Z/Input
blocked (*1)
Hi-Z/Input
blocked (*1)
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Hi-Z/Input
blocked (*1)
Hi-Z/Input
blocked (*1)
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Hi-Z/Input
blocked (*1)
Hi-Z/Input
blocked (*1)
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Hi-Z/Input
blocked (*1)
Hi-Z/Input
blocked (*1)
Hi-Z/Input
blocked
Last state
retained (*3)
Hi-Z/Input
blocked
Hi-Z/Input
blocked (*1)
Hi-Z/Input
blocked (*1)
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Hi-Z/Input
blocked (*1)
Hi-Z/Input
blocked (*1)
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Hi-Z/Input
blocked (*1)
Hi-Z/Input
blocked (*1)
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Hi-Z/Input
blocked (*1)
Hi-Z/Input
blocked (*1)
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Hi-Z/Input
blocked (*1)
Hi-Z/Input
blocked (*1)
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Hi-Z/Input
blocked (*1)
Hi-Z/Input
blocked (*1)
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Hi-Z/Input
blocked (*1)
Hi-Z/Input
blocked (*1)
Page 29 of 92
S6J311A, S6J3119, S6J3118
Table 9-2. Pin State Table (2/2)
74
P218/AN36/TEXT2_0
75
P219/AN37/TEXT3_0
76
P220/IN6_2/AN38
77
P222/IN7_2/AN39/INT7_0
78
P223/IN8_2/AN40/PWU_AN0
79
P224/IN9_2/TX0_2/AN41/PWU_AN1
80
P225/IN10_2/RX0_2/AN42/INT0_0/PWU_AN2
81
P226/IN11_2/AN43/TIOA17_1/PWU_AN3
85
P227/AN44/TIOA23_0/PWU_AN4
86
P228/TX0_1/AN45/TIOA24_0/PWU_AN5
87
P229/OUT0_0/RX0_1/AN46/TIOA25_0/INT8_0/PWU_AN6
88
P230/OUT1_0/AN47/TIOA26_0/PWU_AN7
89
P231/OUT2_0/AN48/TIOA27_0
90
P300/OUT3_0/AN49/TIOA28_0
91
P301/OUT4_0/AN50/TIOA18_1
92
P302/AN51/TIOA19_1
93
P304/AN52/TIOA20_1/TEXT4_0
94
P305/AN53/TIOA29_0/TEXT5_0
95
NMIX
96
P306/TX0_0/AN54
97
P307/RX0_0/AN55/INT1_0
98
P308/IN0_1/AN56/TIOA28_1
99
P309/IN1_1/AN57/TIOA29_1
100
P312/IN2_1/AN58
101
P313/IN3_1/AN59/INT10_1
102
P314/IN4_1/AN60/TIOA7_1
103
P315/IN5_1/AN61/TIOA8_1
104
P317/AN62/TIOA9_1/INT11_1
107
P321/PWUTRG
110
TRST/P322
111
TDO/P323
112
TDI/P324
113
TMS
114
TCK
115
P327
116
P330
117
MD
118
X0
119
X1
121
P331
122
P400
123
RSTX
127
P401/IN0_0
128
P402/IN1_0/INT2_0
129
P403/IN2_0/TRACEDATA0
130
P404/IN3_0/TRACEDATA1
P405/IN4_0/INT11_0/TRACEDATA2
132
P406/TRACEDATA3
133
P407/TRACEDATA4
134
P408/SIN2_0/INT12_0/TRACEDATA5
135
P409/SOT2_0/SDA2_0/TIOA24_1/TRACEDATA6
136
P411/INT13_1/SCK2_0/SCL2_0/TRACEDATA7
137
P413/SCS20_0/INT14_1
138
P414/SCS21_0
139
P416/IN5_0/TIOA22_1
140
P417/TIOA23_1/INT15_1
141
P418/SCS22_0/INT14_0
142
P420/SCK2_1/TRACECLK
143
P421/SIN2_1/TRACECTL
High impedance enabled
(SYSC0_SPECFGR.
PSSPADCTRL=1)
High impedance enabled
(SYSC0_SPECFGR.
PSSPADCTRL=1)
Timer mode *4
High impedance disabled
(SYSC0_SPECFGR.
PSSPADCTRL=0)
Stop mode *4
High impedance disabled
(SYSC0_SPECFGR.
PSSPADCTRL=0)
CPU Sleep
Sleep mode
Internal Reset Factor
*2
After internal reset
issuance
(Before GPORT setting)
External Reset
Factor 3
Internal reset issuance
in progress
After Releasing
External Factor
After internal reset
issuance
(Before GPORT setting)
Internal reset issuance
in progress
Before internal reset
issuance
After internal reset
issuance
(Before GPORT setting)
External Reset Factor 2
While Generating External
Factor
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Hi-Z/Input
blocked (*1)
Hi-Z/Input
blocked (*1)
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Hi-Z/Input
blocked (*1)
With control
-
With control
Hi-Z/Input blocked
Input enabled
Hi-Z/Input blocked
Hi-Z/
Last status
retained
Hi-Z/Input
blocked
Input enabled
Hi-Z
/Last status
retained
Hi-Z/Input
blocked
Hi-Z/Input blocked
Input enabled
Hi-Z/Input blocked
Hi-Z/Input blocked
Input enabled
Hi-Z/Input blocked
Status immediately
before the shutdown
retaine
Input enabled
Status immediately
before the shutdown
retaine
Last state
retained
Input enabled
Last state
retained
Last state
retained (*3)
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Hi-Z/Input
blocked (*1)
Hi-Z/Input
blocked (*1)
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Input enabled
Input enabled
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Hi-Z/Input
blocked (*1)
Hi-Z/Input
blocked (*1)
Hi-Z/Input
blocked
Last state
retained (*3)
Hi-Z/Input
blocked (*1)
Last state
retained (*3)
Hi-Z/Input
blocked (*1)
Hi-Z/Input
blocked
Last state
retained (*3)
Hi-Z/Input
blocked (*1)
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Hi-Z/Input
blocked (*1)
-
With control
131
Internal reset issuance
in progresst
GPORTEN
Control
Internal reset issuance
in progress
Pin No.
Pin Name
After external
factor releasing
Internal reset issuance
in progress
External Reset Factor 1
External
factor
generation
in progress
-
Hi-Z/Input blocked
Hi-Z/Input blocked
Hi-Z/Input blocked
Hi-Z/Input blocked
Input enabled
Input enabled
Input enabled
Input enabled
-
-
-
-
Input enabled
Input enabled
Input enabled
Input enabled
Hi-Z/Input blocked
Hi-Z/Input
blocked *7
(Last state
retained) *6
(PWUTRG
output/Input
blocked *5)
Input enabled (Status Input enabled Input enabled
immediately before the (Last state
(Last state
shutdown retaine) *6
retained) *6 retained (*3)) *6
Input enabled
Input enabled
Last state
retained
Hi-Z/Input blocked
Hi-Z/Input blocked
Status immediately
before the shutdown
retaine
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Input enabled
(Hi-Z/Input
blocked) (*6)
Input enabled
(Last state
retained (*3)) *6
Input enabled
(Hi-Z/Input
blocked) (*6)
Input enabled
Last state
retained (*3)
Hi-Z/Input
blocked
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
-
-
-
-
-
-
Hi-Z/Input blocked
Hi-Z/Input blocked
Status immediately
before the shutdown
retaine
Last state
retained
Input enabled
Input enabled
Input enabled
Input enabled
-
Input enabled
Hi-Z/Input blocked
Hi-Z
/Last status
retained
Hi-Z/Input
blocked
Input enabled
Hi-Z
/Last status
retained
Hi-Z/Input
blocked
Hi-Z/Input blocked
Hi-Z/Input blocked
Status immediately
before the shutdown
retaine
Last state
retained (*3)
Hi-Z/Input
blocked (*1)
Hi-Z/Input
blocked *7
(Last state
retained) *3 *6
(*5)
-
Hi-Z/Input blocked
Document Number: 002-04632 Rev.*B
Hi-Z/Input
blocked
Hi-Z/Input
blocked *7
(Last state
retained) *6
(PWUTRG
output/Input
blocked *5)
Input enabled
With control
With control
Hi-Z
/Last status
retained
Hi-Z/Input blocked *7
(Status immediately
before the shutdown
retaine) *6
(PWUTRG output/Input
blocked *5)
Input enabled
Last state
retained (*3)
Input enabled
-
Hi-Z/Input
blocked
Input enabled
Last state
retained (*3)
Last state
retained (*3)
Hi-Z/Input
blocked
Input enabled
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Hi-Z/Input
blocked (*1)
Hi-Z/Input
blocked (*1)
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Hi-Z/Input
blocked (*1)
Hi-Z/Input
blocked (*1)
Hi-Z/Input
blocked
Last state
retained
Hi-Z/Input
blocked
Hi-Z/Input
blocked (*1)
Hi-Z/Input
blocked
Last state
retained (*3)
Hi-Z/Input
blocked (*1)
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Hi-Z/Input
blocked (*1)
Hi-Z/Input
blocked (*1)
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Hi-Z/Input
blocked (*1)
Hi-Z/Input
blocked (*1)
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Page 30 of 92
S6J311A, S6J3119, S6J3118
*1: Input disable is not valid when external interrupts are enabled.
*2: Recovery from standby (power off) becomes a factor.
*3: The pin state from the time that HOLDIO_PD2 was set (SYSC0_SPECFGR.HOLDIO_PD2=1) is retained. If power-off has not
occurred and HOLDIO_PD2 has not been set (SYSC0_SPECFGR.HOLDIO_PD2=0), the last state is retained.
*4: To power off power domains 2 and 3, be sure to set HOLDIO_PD2 (SYSC0_SPECFGR.HOLDIO_PD2=1).
*5: When the PWU function is enabled, a change to output occurs.
*6: The pin state when the PORT function is enabled is shown.
*7: When PPC_PCFGRijj:POF[2:0] is set to initial value.
External Reset Factor 1
Power-on reset (PONR)
RAM retention low-voltage detection reset (RVD)
Internal power supply low-voltage detection reset (LVDL1R)
RSTX pin + MD pin simultaneous assert reset (INITX)
External Reset Factor 2
RSTX pin input reset (RSTX)
External Reset Factor 3
Hardware watchdog reset (HWDR)
Software watchdog reset (SWDR)
PLL clock supervisor reset (CSVPRn)
SSCG clock supervisor reset (CSVSRn)
Profile error reset (PRFERR)
Software trigger hard reset (SHRST)
Software reset (SRST)
Internal Reset Factor
Standby transition reset/ Power domain reset
Document Number: 002-04632 Rev.*B
Page 31 of 92
S6J311A, S6J3119, S6J3118
10. Electrical Characteristics
10.1 Absolute Maximum Ratings
Parameter
*1, *2
Power supply voltage
*1, *2
Analog supply voltage
*1
Analog reference voltage
*1
Input voltage
*1
Analog pin input voltage
*1
Output voltage
Maximum clamp current
Total maximum clamp current
"L"-level maximum output current
"L"-level average output current
"L"-level total output current
Rating
Symbol
*3
*4
*5
"H"-level maximum output current
"H"-level average output current
*4
*3
Min
Max
Unit
VCC
AVCC
AVRH
VI
VIA
VO
|ICLAMP |
Σ|ICLAMP |
VSS-0.3
VSS-0.3
VSS-0.3
VSS-0.3
VSS-0.3
VSS-0.3
-
VSS+6.0
VSS+6.0
VSS+6.0
VCC+0.3
VCC+0.3
VCC+0.3
4
20
V
V
V
V
V
V
mA
mA
IOL1
-
3.5
mA
IOL2
-
7
mA
IOLAV1
-
1
mA
IOLAV2
ΣIOL
-
2
40
mA
mA
IOH1
-
-3.5
mA
IOH2
-
-7
mA
IOHAV1
-
-1
mA
-2
-40
1300
+125
+150
mA
mA
mW
°C
°C
IOHAV2
*5
"H"-level total output current
ΣIOH
Power consumption
PD
Operating temperature
TA
-40
Storage temperature
Tstg
-55
*1: These parameters are based on the condition that VSS=AVSS=0.0V.
Remarks
AVCC=VCC
AVRH≤AVCC
*7
*7
When setting is 1
*6
mA
When setting is 2 mA
When setting is 1
*6
mA
When setting is 2 mA
*6
When setting is 1
*6
mA
When setting is 2 mA
When setting is 1
*6
mA
When setting is 2 mA
*6
S6J311xHzC
*8
*2: AVCC and VCC must be set to the same voltage. It is required that AVCC does not exceed
VCC and that the voltage at the analog inputs does not exceed AVCC when the power is switched on.
*3: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins.
*4: The average output current is defined as the value of the average current flowing through any one of the corresponding pins for a
10 ms period. The average value is the operation current X the operation ratio.
*5: The total output current is defined as the maximum current value flowing through all of corresponding pins.
*6: Corresponding pins: general-purpose ports
Document Number: 002-04632 Rev.*B
Page 32 of 92
S6J311A, S6J3119, S6J3118
*7: Corresponding pins: All general-purpose ports and analog input pins
•
•
•
•
Use the device within the recommended operating conditions.
Use the device with direct voltage (current).
The + B signal should always be applied by connecting a limiting resistor between the + B signal and the microcontroller.
The value of the limiting resistor should be set so that the current input to the microcontroller pin does not exceed rated values
at any time regardless of instantaneously or constantly when the + B signal is input.
• Note that when the microcontroller drive current is low, such as in the low-power consumption modes, the + B input potential
can increase the potential at the VCC pin via a protective diode, possibly affecting other devices.
• Note that if the + B signal is input when the microcontroller is off (not fixed at 0 V), since the power is supplied through the pin,
the microcontroller may operate incompletely.
• Note that if the +B signal is input at power-on, since the power is supplied through the pin, the power-on reset may not function
in the power supply voltage.
• Do not leave + B input pins open.
*8: It is standard when four-layer substrate is used. x : A/9/8, z:A/B
Example of a recommended circuit
WARNING:
• Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or
temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings.
Document Number: 002-04632 Rev.*B
Page 33 of 92
S6J311A, S6J3119, S6J3118
10.2 Recommended Operating Conditions
Parameter
Supply voltage
Value
Symbol
VCC
AVCC
VCC
AVCC
(VSS=AVSS=0.0 V)
Min
4.5
4.5
3.5
3.5
Max
5.25
5.25
5.25
5.25
Unit
V
V
V
V
Remarks
Recommended operation assurance range
Operation assurance range
Tolerance of up to ±40%, 126pin
Use a ceramic capacitor or a capacitor that has
*
Smoothing capacitor
CS1
4.7
µF
the similar frequency characteristics.
Use a capacitor with a capacitance greater than
CS as the smoothing capacitor on the VCC pin.
S6J311xHzC*
Operating temperature
TA
-40
+125
°C
* x:A/9/8, z:A/B
*:
For the connections of smoothing capacitor CS1, see the following diagram.
· C pin connection diagram
C(126pin)
CS1
VSS
VSS
C(38pin)
open
AVSS
WARNING:
1. The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of
the device's electrical characteristics are warranted when the device is operated under these conditions.
2. Any use of semiconductor devices will be under their recommended operating condition.
3. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device
failure.
4. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you
are considering application under any conditions other than listed herein, please contact sales representatives beforehand.
Document Number: 002-04632 Rev.*B
Page 34 of 92
S6J311A, S6J3119, S6J3118
Notes:
The following condition should be satisfied in order to facilitate heat dissipation.
−
1. 4 or more layers PCB should be used.
2. The area of PCB should be 114.3 mm x 76.2 mm or more, and the thickness should be 1.6 mm or
more. (JEDEC standard)
3. 1 layer of middle layers at least should be used for dedicated layer to radiate heat with residual
copper rate 90% or more. The layer can be used for system ground.
4. 35~50% of the die stage area which is exposed at back surface of package should be soldered to a
st
part of 1 layer.
st
5. The part of 1 layer should be connected to the dedicated heat radiation layer with more than 10
thermal via holes.
Figure10.2-1: Example thermal via holes on PCB.
Notes:
Figure 10.2-1 is a schematic diagram showing PCB in section.
−
Figure 10.2-2 in the following pages are recommended land patterns for each package series.
Thermal via holes should closely be placed and aligned with lands.
−
−
If you are considering application under any conditions other than listed herein, please contact sales
representatives beforehand.
Document Number: 002-04632 Rev.*B
Page 35 of 92
S6J311A, S6J3119, S6J3118
Figure 10.2-2: Land Pattern and Thermal Via LEU144
Document Number: 002-04632 Rev.*B
Page 36 of 92
S6J311A, S6J3119, S6J3118
10.3 DC Characteristics
Parameter
Symbol
VIH1
"H" level
input
voltage
VIH2
(TA: Recommended operating conditions, VCC=5.0 V +5%/-10%, VSS=AVSS=0.0 V)
Pin Name
P000 to P001,
P003,
P005 to P010,
P012 to P013,
P015 to P024,
P027 to P031,
P100 to P101,
P103,
P105 to P109,
P112 to P115,
P117 to P120,
P122 to P123,
P126 to P131,
P202 to P215,
P218 to P220,
P222 to P231,
P300 to P302,
P304 to P309,
P312 to P315,
P317,
P327, P330 to
P331,
P400 to P409,
P411,
P413 to P414,
P416 to P418,
P420 to P421
P401 to P409,
P411,
P413 to P414,
P416 to P418,
P420 to P421
Value
Condition
s
Min
Typ
Unit
Max
CMOS
Schmitt
input level
selected
0.7×VCC
-
VCC+0.3
V
Automotive
input level
selected
0.8×VCC
-
VCC+0.3
V
VIH4
RSTX, NMIX
-
0.7×VCC
-
VCC+0.3
V
VIH5
MD
-
0.7×VCC
-
VCC+0.3
V
VIH6
TRST, TCK, TDI,
TMS
TTL input
level
2.3
-
VCC+0.3
V
Document Number: 002-04632 Rev.*B
Remarks
Page 37 of 92
S6J311A, S6J3119, S6J3118
Parameter
Symbol
VIL1
"L" level
input
voltage
VIL2
Pin Name
P000 to P001,
P003,
P005 to P010,
P012 to P013,
P015 to P024,
P027 to P031,
P100 to P101,
P103,
P105 to P109,
P112 to P115,
P117 to P120,
P122 to P123,
P126 to P131,
P202 to P215,
P218 to P220,
P222 to P231,
P300 to P302,
P304 to P309,
P312 to P315,
P317,
P327, P330 to
P331,
P400 to P409,
P411,
P413 to P414,
P416 to P418,
P420 to P421
P401 to P409,
P411,
P413 to P414,
P416 to P418,
P420 to P421
Condition
s
Value
Min
Typ
Unit
Max
CMOS
Schmitt
input level
selected
VSS-0.3
-
0.3×VCC
V
Automotive
input level
selected
VSS-0.3
-
0.5×VCC
V
VIL4
RSTX, NMIX
-
VSS-0.3
-
0.3×VCC
V
VIL5
MD
-
VSS-0.3
-
0.3×VCC
V
VIL6
TRST, TCK, TDI,
TMS
TTL input
level
VSS-0.3
-
0.8
V
Document Number: 002-04632 Rev.*B
Remarks
Page 38 of 92
S6J311A, S6J3119, S6J3118
(TA: Recommended operating conditions, VCC=5.0 V +5%/-10%, VSS=AVSS=0.0 V)
Parameter
Symbol
"H" level
output
voltage
VOH1
"H" level
output
voltage
VOH2
Pin Name
P000 to P001,
P003,
P005 to P010,
P012 to P013,
P015 to P024,
P027 to P031,
P100 to P101,
P103,
P105 to P109,
P112 to P115,
P117 to P120,
P122 to P123,
P126 to P131,
P202 to P215,
P218 to P220,
P222 to P231,
P300 to P302,
P304 to P309,
P312 to P315,
P317,
P321 to P324,
P327, P330 to
P331,
P400 to P409,
P411,
P413 to P414,
P416 to P418,
P420 to P421
P000 to P001,
P003,
P005 to P010,
P012 to P013,
P015 to P024,
P027 to P031,
P100 to P101,
P103,
P105 to P109,
P112 to P115,
P117 to P120,
P122 to P123,
P126 to P131,
P202 to P215,
P218 to P220,
P222 to P231,
P300 to P302,
P304 to P309,
P312 to P315,
P317,
P321 to P324,
P327, P330 to
P331,
P400 to P409,
P411,
P413 to P414,
P416 to P418,
P420 to P421
Document Number: 002-04632 Rev.*B
Conditions
Value
Min
Typ
Unit
Max
VCC=4.5 V
IOH=-2.0 mA
VCC-0.5
-
VCC
V
VCC=4.5 V
IOH=-1.0 mA
VCC-0.5
-
VCC
V
Remarks
Page 39 of 92
S6J311A, S6J3119, S6J3118
Parameter
Symbol
"L" level
output
voltage
VOL1
"L" level
output
voltage
VOL2
Pin Name
P000 to P001,
P003,
P005 to P010,
P012 to P013,
P015 to P024,
P027 to P031,
P100 to P101,
P103,
P105 to P109,
P112 to P115,
P117 to P120,
P122 to P123,
P126 to P131,
P202 to P215,
P218 to P220,
P222 to P231,
P300 to P302,
P304 to P309,
P312 to P315,
P317,
P321 to P324,
P327, P330 to
P331,
P400 to P409,
P411,
P413 to P414,
P416 to P418,
P420 to P421
P000 to P001,
P003,
P005 to P010,
P012 to P013,
P015 to P024,
P027 to P031,
P100 to P101,
P103,
P105 to P109,
P112 to P115,
P117 to P120,
P122 to P123,
P126 to P131,
P202 to P215,
P218 to P220,
P222 to P231,
P300 to P302,
P304 to P309,
P312 to P315,
P317,
P321 to P324,
P327, P330 to
P331,
P400 to P409,
P411,
P413 to P414,
P416 to P418,
P420 to P421
Document Number: 002-04632 Rev.*B
Value
Conditions
Min
Typ
Unit
Max
VCC=4.5 V
IOL=2.0 mA
0
-
0.4
V
VCC=4.5 V
IOL=1.0 mA
0
-
0.4
V
Remarks
Page 40 of 92
S6J311A, S6J3119, S6J3118
(TA: Recommended operating conditions, VCC=5.0 V +5%/-10%, VSS=AVSS=0.0 V)
Parameter
Input leakage
current
Pull-up
resistor
Symbol
Pin Name
IIL
All input pins
RUP1
RSTX, NMIX
P000 to P001,
P003,
P005 to P010,
P012 to P013,
P015 to P024,
P027 to P031,
P100 to P101,
P103,
P105 to P109,
P112 to P115,
P117 to P120,
P122 to P123,
P126 to P131,
P202 to P215,
P218 to P220,
P222 to P231,
P300 to P302,
P304 to P309,
P312 to P315,
P317
P327, P330 to
P331,
P400 to P409,
P411,
P413 to P414,
P416 to P418,
P420 to P421
TDI(P324), TMS,
TCK
RUP2
RUP3
Document Number: 002-04632 Rev.*B
Value
Conditions
VCC=AVCC=5.25 V
VSS < VI < VCC
-
Min
Typ
Max
Unit
-5
-
+5
µA
25
-
100
kΩ
Pull-up resistor
selected
25
-
100
kΩ
-
25
-
100
kΩ
Remarks
Page 41 of 92
S6J311A, S6J3119, S6J3118
Parameter
Pull-down
resistor
Symbol
RDOWN1
RDOWN2
Input
capacitance
CIN
Pin Name
P000 to P001,
P003,
P005 to P010,
P012 to P013,
P015 to P024,
P027 to P031,
P100 to P101,
P103,
P105 to P109,
P112 to P115,
P117 to P120,
P122 to P123,
P126 to P131,
P202 to P215,
P218 to P220,
P222 to P231,
P300 to P302,
P304 to P309,
P312 to P315,
P317
P327, P330 to
P331,
P400 to P409,
P411,
P413 to P414,
P416 to P418,
P420 to P421
TRST(P322)
Pins other than
VCC, VSS,
AVCC0, AVCC1,
AVSS0, AVSS1
Document Number: 002-04632 Rev.*B
Value
Conditions
Min
Typ
Max
Unit
Pull-down resistor
selected
25
-
100
kΩ
-
25
-
100
kΩ
-
-
5
15
pF
Remarks
Page 42 of 92
S6J311A, S6J3119, S6J3118
(TA: Recommended operating conditions, VCC=5.0 V +5%/-10%, VSS=AVSS=0.0 V)
Parameter
Power
supply
current
S6J311xHz
C*
*x: A/9/8,
z:A/B
Symbol
Pin
Name
ICC5
Normal
operation
Flash
write/erase
ICCS5
ICCT5
ICCH5
VCC
ICCP
Value
Conditions
Min
Typ
Max
Unit
Remarks
-
80
175
mA
Operating at 96MHz
-
100
200
mA
Operating at 96MHz
CPU Sleep
-
65
150
mA
Operating at 96 MHz
Timer mode
-
480
1450
µA
TA=25°C
Slow-CR source Oscillation
Stop mode
-
480
1450
µA
TA=25°C
-
52.5
129.7
µA
TA=25°C
(PWU operation cycle 16ms)
-
46.2
115.5
µA
TA=25°C
(PWU operation cycle 32ms)
PWU mode
(Shutdown)
Timer mode
TA=25°C
40
100
µA
Slow-CR source Oscillation
(Shutdown)
Stop mode
ICCH52
40
100
µA
TA=25°C
(Shutdown)
Refer to Hardware manual "APPENDIX State transition" for Internal clock frequency setting / Setting of the power domain /
Regulator setting.
ICCT52
Document Number: 002-04632 Rev.*B
Page 43 of 92
S6J311A, S6J3119, S6J3118
10.4 AC Characteristics
10.4.1 Source Clock Timing
Parameter
Symbol
(TA: Recommended operating conditions, VCC=5.0 V +5%/-10%, VSS=AVSS=0.0 V)
Pin
Name
Conditions
Value
Min
Typ
Max
Unit
Remarks
Source oscillation
clock
FC
X0, X1
4
MHz
frequency
Source oscillation
clock
tCYL
X0, X1
250
ns
cycle time
CAN PLL jitter
tPJ
-10
+10
ns
*
(during lock)
Built-in slow-CR
FCRS
50
100
150
kHz
oscillation frequency
Built-in fast-CR
FCRF
2.4
4
6.0
MHz
oscillation frequency
PLL input clock
FPLLI
4
MHz
frequency
PLL macro oscillation
FPLLO
400
576
MHz
clock frequency
SSCG-PLL input clock
FSSCGPLLI
4
MHz
frequency
SSCG-PLL macro
FSSCGPLLO
400
576
MHz
oscillation clock
frequency
*:
The maximum/minimum values have been standardized with the main clock and PLL clock in use.
• X0 and X1 clock timing
tCYL
X0
• CAN PLL jitter
A time difference from the ideal clock is guaranteed for each cycle period within 20,000 cycles.
t1
t2
t3
tn-1
tn
Ideal clock
Slow
PLL output
t1
t2
t3
tn-1
tn
Fast
Document Number: 002-04632 Rev.*B
Page 44 of 92
S6J311A, S6J3119, S6J3118
10.4.2 Internal Clock Timing
Parameter
Internal
Clock
Frequency
Internal
Clock
Cycle Time
Internal
Clock
Cycle Time
(TA: Recommended operating conditions, VCC=5.0 V +5%/-10%, VSS=AVSS=0.0 V)
Symbol
FCLK_CPU
FCLK_FCLK
FCLK_ATB
FCLK_DBG
FCLK_HPM
FCLK_HPM2
FCLK_DMA
FCLK_MEMC
FCLK_EXTBUS
FCLK_SYSC1
FCLK_HAPP0A0
FCLK_HAPP0A1
FCLK_HAPP1B0
FCLK_HAPP1B1
FCLK_LLPBM
FCLK_LLPBM2
FCLK_LCP
FCLK_LCP0
FCLK_LCP0A
FCLK_LCP1
FCLK_LCP1A
FCLK_LAPP0
FCLK_LAPP0A
FCLK_LAPP1
FCLK_LAPP1A
FCLK_TRC
FCLK_HSSPI
FCLK_SYSC0H
FCLK_COMH
FCLK_RAM0H
FCLK_RAM1H
FCLK_SYSC0P
FCLK_COMP
FCANFD_CCLK
tCLK_CPU
tCLK_FLASH
tCLK_ATB
tCLK_DBG
tCLK_HPM
tCLK_HPM2
tCLK_DMA
tCLK_MEMC
tCLK_EXTBUS
tCLK_SYSC1
tCLK_HAPP0A0
tCLK_HAPP0A1
tCLK_HAPP1B0
tCLK_HAPP1B1
tCLK_LLPBM
tCLK_LLPBM2
tCLK_LCP
tCLK_LCP0
Pin Name
-
Document Number: 002-04632 Rev.*B
Conditions
-
S6J311xHzC* Value
* x:A/9/8, z:A/B
Min
10.4
20.8
20.8
20.8
41.6
83.3
41.6
41.6
41.6
41.6
41.6
41.6
41.6
41.6
10.4
20.8
20.8
41.6
Typ
-
Max
96
48
48
48
24
12
24
24
24
24
24
24
24
24
96
48
48
24
24
24
24
24
24
24
24
48
24
24
24
24
24
24
24
40
-
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Remarks
CLK_CPU
CLK_FCLK
CLK_ATB
CLK_DBG
CLK_HPM
CLK_HPM2
CLK_DMA
CLK_MEMC
CLK_EXTBUS
CLK_SYSC1
CLK_HAPP0A0
CLK_HAPP0A1
CLK_HAPP1B0
CLK_HAPP1B1
CLK_LLPBM
CLK_LLPBM2
CLK_LCP
CLK_LCP0
CLK_LCP0A
CLK_LCP1
CLK_LCP1A
CLK_LAPP0
CLK_LAPP0A
CLK_LAPP1
CLK_LAPP1A
CLK_TRC
CLK_HSSPI
CLK_SYSC0H
CLK_COMH
CLK_RAM0H
CLK_RAM1H
CLK_SYSC0P
CLK_COMP
CANFD_CCLK
CLK_CPU
CLK_FCLK
CLK_ATB
CLK_DBG
CLK_HPM
CLK_HPM2
CLK_DMA
CLK_MEMC
CLK_EXTBUS
CLK_SYSC1
CLK_HAPP0A0
CLK_HAPP0A1
CLK_HAPP1B0
CLK_HAPP1B1
CLK_LLPBM
CLK_LLPBM2
CLK_LCP
CLK_LCP0
Page 45 of 92
S6J311A, S6J3119, S6J3118
Parameter
Symbol
tCLK_LCP0A
tCLK_LCP1
tCLK_LCP1A
tCLK_LAPP0
tCLK_LAPP0A
tCLK_LAPP1
tCLK_LAPP1A
tCLK_TRC
tCLK_HSSPI
tCLK_SYSC0H
tCLK_COMH
tCLK_RAM0H
tCLK_RAM1H
tCLK_SYSC0P
tCLK_COMP
tCANFD_CCLK
Pin Name
-
Conditions
-
S6J311xHzC* Value
* x:A/9/8, z:A/B
Min
41.6
41.6
41.6
41.6
41.6
41.6
41.6
20.8
41.6
41.6
41.6
41.6
41.6
41.6
41.6
25.0
Typ
-
Unit
Max
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Remarks
CLK_LCP0A
CLK_LCP1
CLK_LCP1A
CLK_LAPP0
CLK_LAPP0A
CLK_LAPP1
CLK_LAPP1A
CLK_TRC
CLK_HSSPI
CLK_SYSC0H
CLK_COMH
CLK_RAM0H
CLK_RAM1H
CLK_SYSC0P
CLK_COMP
CANFD_CCLK
• Guaranteed operation range
Internal operation clock frequency vs. Power supply voltage
3.5
2
4
96
Internal clock frequency FCPU_CLK(MHz)
Note: A supply voltage that is equal to or less than the set voltage for low-voltage detection causes a reset.
Document Number: 002-04632 Rev.*B
Page 46 of 92
S6J311A, S6J3119, S6J3118
Relationship between the oscillation clock frequency and internal clock frequency
Oscillation Clock
Frequency
4 MHz
4 MHz
−
PLL Multiplier
Setting
144
120
Main Clock
4 MHz
4 MHz
PLL Output
Division Setting
6
6
PLL Clock
96 MHz
80 MHz
Oscillation circuit example
X0
X1
R
C1
C2
Notes:
· When configuring the oscillator circuit, it is recommended to ask matching evaluation of the circuit to oscillator
manufacturers for the design.
· The maximum PLL clock frequency must be 96MHz.
Output division configuration can be set by the following.
- PLLDIVM bit in SYSC0_RUNPLL0CNTR register
- PLLDIVM bit in SYSC0_PSSPLL0CNTR register
- SSCGDIVM bit in SYSC0_RUNSSCG0CNTR0 register
- SSCGDIVM bit in SYSC0_PSSSSCG0CNTR0 register
(e.g. If PLLout is 576MHz, these settings must be configured as "multiply by 6" and over multiplication
setting)
AC characteristics are specified by the following measurement reference voltage values.
−
Input signal waveform
Hysteresis input pin (Automotive)
−
Output signal waveform
Output pin
0.8VCC
2.4V
0.5VCC
0.8V
Hysteresis input pin (CMOS Schmitt)
0.7VCC
0.3VCC
Hysteresis input pin (TTL)
2.3V
0.8V
Document Number: 002-04632 Rev.*B
Page 47 of 92
S6J311A, S6J3119, S6J3118
10.4.3 Reset Input
Parameter
Reset
input time
Width for reset
input removal
Symbol
tRSTL
(TA: Recommended operating conditions, VCC=5.0 V +5%/-10%, VSS=AVSS=0.0 V)
Pin Name
RSTX
Value
Conditions
-
Min
Unit
Max
10
-
µs
1
-
µs
Remarks
tRSTL
RSTX
0.2VCC
Document Number: 002-04632 Rev.*B
0.2VCC
Page 48 of 92
S6J311A, S6J3119, S6J3118
10.4.4 Power-on Conditions
Parameter
Level detection
voltage
Level release
voltage
Level detection
hysteresis width
Level detection
time
Power off time
(TA: Recommended operating conditions, VSS=0.0 V)
Pin
Name
Symbol
Value
Condition
s
Min
Typ
Unit
Max
Remarks
-
VCC
-
2.15
2.35
2.55
V
-
VCC
-
2.25
2.45
2.65
V
-
VCC
-
-
100
-
mV
-
-
-
-
-
30
μs
*1
tOFF
VCC
-
1
-
-
ms
*2
VCC:
*3
0.2V to
–
–
6
mV/µs
2.55V
Maximum ramp
VCC:
rate guaranteed to
Between
4
|dV/dt|
Vcc
–
–
50
mV/µs
*
not generate
2.6V and
power-on reset
4.5V
*1:
The specified level detection time applies only for power ramp rate of 6mV/μs or less.
*2:
Vcc must be held below 0.2V for a minimum period of tOFF.
*3:
Power-on can detect by satisfying power ramp rate when power off time is not satisfied.
*4:
This specification is specified the power supply fluctuation after power on detection. When VCC voltage is between 2.6V and
4.5V, the power supply fluctuation is below 50mV/us, the detection of power-on is suppressed. The power-on does not detect in
any power fluctuation between 4.5V and 5.5V.
Power ramp rate
Note:
dV/dt
*2
When neither nor
brownout event.
* x: A/9/8, z: A/B
VCC
*3
can be satisfied, use S6J311xHzC* and assert external reset (RSTX) at power-up and at any
Power off time, Power ramp rate at Power-on
tOFF
VCC
0.2V
dV/dt
0.2V
Maximum ramp rate guaranteed to not generate power-on reset
5.5V
4.5V
VCC
|dV/dt|
|dV/dt|
Document Number: 002-04632 Rev.*B
2.6V
Page 49 of 92
S6J311A, S6J3119, S6J3118
10.4.5 Multi-function Serial
10.4.5.1 CSIO Timing (SMR:MD[2:0]=010B)
(5-1-1) Normal Synchronous Transfer (SCR:SPI=0) and Serial Clock Output Signal Detect Level "H"
(SMR:SCINV=0)
(TA: Recommended operating conditions, VCC=5.0 V +5%/-10%, VSS=AVSS=0.0 V)
Parameter
Symbol
Pin Name
Serial clock
cycle time
tSCYC
SCK0 to SCK3
SCK ↓ → SOT
delay time
tSLOVI
SCK0 to SCK3,
SOT0 to SOT3
Valid SIN → SCK ↑
setup time
tIVSHI
SCK ↑→ Valid SIN
hold time
tSHIXI
Serial clock
"H" pulse width
tSHSL
Serial clock
"L" pulse width
tSLSH
SCK ↓→ SOT
delay time
tSLOVE
Valid SIN → SCK ↑
setup time
tIVSHE
SCK ↑ → Valid SIN
hold time
tSHIXE
SCK fall time
tF
SCK rise time
tR
Value
Conditions
Min
Max
Unit
4tCLK_LCP0A
-
ns
-30
+30
ns
30
-
ns
0
-
ns
tCLK_LCP0A
+10
-
ns
2tCLK_LCP0A
-10
-
ns
-
45
ns
10
-
ns
20
-
ns
SCK0 to SCK3
-
5
ns
SCK0 to SCK3
-
5
ns
SCK0 to SCK3,
SIN0 to SIN3
Master
mode
(CL=50pF,
IOL=-2mA,
IOH=2mA),
(CL=20pF,
IOL=-1mA,
IOH=1mA)
SCK0 to SCK3
SCK0 to SCK3,
SOT0 to SOT3
SCK0 to SCK3,
SIN0 to SIN3
Slave
mode
(CL=50pF,
IOL=-2mA,
IOH=2mA),
(CL=20pF,
IOL=-1mA,
IOH=1mA)
Remarks
Notes:
• This is the AC characteristic in CLK synchronized mode.
• CL is the load capacitance applied to pins during testing.
• The maximum baud rate is limited by the internal operating clock used and other parameters.
For details, see the hardware manual.
Document Number: 002-04632 Rev.*B
Page 50 of 92
S6J311A, S6J3119, S6J3118
tSCYC
SCK
VOH
VOL
tSLOVI
VOH
VOL
SOT
tIVSHI
tSHIXI
VIH
VIL
SIN
VIH
VIL
Master mode
tSLSH
SCK
VIH
tF
SOT
VIL
tSHSL
VIL
tR
tSLOVE
VOH
VOL
tIVSHE
SIN
VIH
VIH
tSHIXE
VIH
VIL
VIH
VIL
Slave mode
Document Number: 002-04632 Rev.*B
Page 51 of 92
S6J311A, S6J3119, S6J3118
(5-1-2) Normal Synchronous Transfer (SCR:SPI=0) and Serial Clock Output Signal Detect Level "L"
(SMR:SCINV=1)
(TA: Recommended operating conditions, VCC=5.0 V +5%/-10%, VSS=AVSS=0.0 V)
Parameter
Symbol
Serial clock
cycle time
tSCYC
SCK ↑ → SOT
delay time
tSHOVI
Valid SIN → SCK ↓
setup time
tIVSLI
SCK ↓ → Valid SIN
hold time
tSLIXI
Serial clock
"H" pulse width
tSHSL
Serial clock
"L" pulse width
tSLSH
SCK ↑ → SOT
delay time
tSHOVE
Valid SIN → SCK ↓
setup time
tIVSLE
SCK ↓ → Valid SIN
hold time
tSLIXE
SCK fall time
tF
SCK rise time
tR
Pin Name
SCK0 to SCK3
Value
Conditions
Min
Max
Unit
4tCLK_LCP0A
-
ns
-30
+30
ns
30
-
ns
0
-
ns
tCLK_LCP0A
+10
-
ns
2tCLK_LCP0A
-10
-
ns
-
45
ns
10
-
ns
20
-
ns
SCK0 to SCK3
-
5
ns
SCK0 to SCK3
-
5
ns
SCK0 to SCK3,
SOT0 to SOT3
SCK0 to SCK3,
SIN0 to SIN3
Master
mode
(CL=50pF,
IOL=-2mA,
IOH=2mA),
(CL=20pF,
IOL=-1mA,
IOH=1mA)
SCK0 to SCK3
SCK0 to SCK3,
SOT0 to SOT3
SCK0 to SCK3,
SIN0 to SIN3
Slave
mode
(CL=50pF,
IOL=-2mA,
IOH=2mA),
(CL=20pF,
IOL=-1mA,
IOH=1mA)
Remarks
Notes:
• This is the AC characteristic in CLK synchronized mode.
• CL is the load capacitance applied to pins during testing.
• The maximum baud rate is limited by the internal operating clock used and other parameters.
For details, see the hardware manual.
Document Number: 002-04632 Rev.*B
Page 52 of 92
S6J311A, S6J3119, S6J3118
tSCYC
VOH
SCK
VOL
tSHOVI
VOH
VOL
SOT
tIVSLI
tSLIXI
VIH
VIL
SIN
VIH
VIL
Master mode
tSHSL
SCK
VIL
tR
SOT
VIH
tSLSH
VIH
tSHOVE
VIL
VOH
VOL
tIVSLE
SIN
VIL
tF
VIH
VIL
tSLIXE
VIH
VIL
Slave mode
Document Number: 002-04632 Rev.*B
Page 53 of 92
S6J311A, S6J3119, S6J3118
(5-1-3) SPI Supported (SCR:SPI=1), and Serial Clock Output Signal Detect Level "H" (SMR:SCINV=0)
(TA: Recommended operating conditions, VCC=5.0 V +5%/-10%, VSS=AVSS=0.0 V)
Parameter
Symbol
Pin Name
Serial clock
cycle time
tSCYC
SCK0 to SCK3
SCK ↑ → SOT
delay time
tSHOVI
SCK0 to SCK3,
SOT0 to SOT3
Valid SIN → SCK ↓
setup time
tIVSLI
SCK ↓ → Valid SIN
hold time
tSLIXI
SOT → SCK ↓
delay time
tSOVLI
Serial clock
"H" pulse width
tSHSL
Serial clock
"L" pulse width
tSLSH
SCK ↑ → SOT
delay time
tSHOVE
Valid SIN → SCK ↓
setup time
tIVSLE
SCK ↓ → Valid SIN
hold time
tSLIXE
SCK fall time
tF
SCK rise time
tR
Value
Conditions
Min
Max
Unit
4tCLK_LCP0A
-
ns
-30
+30
ns
30
-
ns
0
-
ns
2tCLK_LCP0A
-30
-
ns
tCLK_LCP0A
+10
-
ns
2tCLK_LCP0A
-10
-
ns
-
45
ns
10
-
ns
20
-
ns
SCK0 to SCK3
-
5
ns
SCK0 to SCK3
-
5
ns
SCK0 to SCK3,
SIN0 to SIN3
Master
mode
(CL=50pF,
IOL=-2mA,
IOH=2mA),
(CL=20pF,
IOL=-1mA,
IOH=1mA)
SCK0 to SCK3,
SOT0 to SOT3
SCK0 to SCK3
SCK0 to SCK3,
SOT0 to SOT3
SCK0 to SCK3,
SIN0 to SIN3
Slave
mode
(CL=50pF,
IOL=-2mA,
IOH=2mA),
(CL=20pF,
IOL=-1mA,
IOH=1mA)
Remarks
Notes:
• This is the AC characteristic in CLK synchronized mode.
• CL is the load capacitance applied to pins during testing.
• The maximum baud rate is limited by the internal operating clock used and other parameters.
For details, see the hardware manual.
Document Number: 002-04632 Rev.*B
Page 54 of 92
S6J311A, S6J3119, S6J3118
tSCYC
SCK
VOH
VOL
VOL
tSHOVI
tSOVLI
VOH
VOL
SOT
VOH
VOL
tIVSLI
tSLIXI
VIH
VIL
VIH
VIL
SIN
Master mode
tSHSL
tSLSH
VIH
SCK
tR
VIH
VIH
VIL
tSHOVE
VOH
VOL
VOH
VOL
tIVSLE
SIN
VIL
tF
*
SOT
VIL
tSLIXE
VIH
VIL
VIH
VIL
* Changes when writing to the TDR register
Slave mode
Document Number: 002-04632 Rev.*B
Page 55 of 92
S6J311A, S6J3119, S6J3118
(5-1-4) SPI Supported (SCR:SPI=1), and Serial Clock Output Signal Detect Level "L" (SMR:SCINV=1)
(TA: Recommended operating conditions, VCC=5.0 V +5%/-10%, VSS=AVSS=0.0 V)
Parameter
Symbol
Pin Name
Serial clock
cycle time
tSCYC
SCK0 to
SCK3
SCK ↓ → SOT
delay time
tSLOVI
SCK0 to SCK3,
SOT0 to SOT3
Valid SIN → SCK ↑
setup time
tIVSHI
SCK ↑→ Valid SIN
hold time
tSHIXI
SOT → SCK ↑
delay time
tSOVHI
Serial clock
"H" pulse width
tSHSL
Serial clock
"L" pulse width
tSLSH
SCK ↓ → SOT
delay time
tSLOVE
Valid SIN → SCK ↑
setup time
tIVSHE
SCK ↑ → Valid SIN
hold time
tSHIXE
SCK fall time
tF
SCK rise time
tR
Value
Conditions
Min
Max
Unit
4tCLK_LCP0A
-
ns
-30
+30
ns
30
-
ns
0
-
ns
2tCLK_LCP0A -30
-
ns
tCLK_LCP0A +10
-
ns
2tCLK_LCP0A -10
-
ns
-
45
ns
10
-
ns
20
-
ns
SCK0 to SCK3
-
5
ns
SCK0 to
SCK3
-
5
ns
SCK0 to SCK3,
SIN0 to SIN3
Master
mode
(CL=50pF,
IOL=-2mA,
IOH=2mA),
(CL=20pF,
IOL=-1mA,
IOH=1mA)
SCK0 to SCK3,
SOT0 to SOT3
Remarks
SCK0 to SCK3
SCK0 to SCK3,
SOT0 to SOT3
SCK0 to SCK3,
SIN0 to SIN3
Slave
mode
(CL=50pF,
IOL=-2mA,
IOH=2mA),
(CL=20pF,
IOL=-1mA,
IOH=1mA)
Notes:
• This is the AC characteristic in CLK synchronized mode.
• CL is the load capacitance applied to pins during testing.
• The maximum baud rate is limited by the internal operating clock used and other parameters.
For details, see the hardware manual.
Document Number: 002-04632 Rev.*B
Page 56 of 92
S6J311A, S6J3119, S6J3118
tSCYC
VOH
VOH
SCK
VOL
tSOVHI
tSLOVI
VOH
VOL
SOT
VOH
VOL
tIVSHI
tSHIXI
VIH
VIL
SIN
VIH
VIL
Master mode
tSLSH
tSHSL
SCK
VIL
VOH
VOL
VIL
VIL
VIH
tSLOV
VOH
VOL
tSHIXE
tIVSHE
SIN
VIH
tF
tR
*
SOT
VIH
VIH
VIL
VIH
VIL
* Changes when writing to the TDR register
Slave mode
Document Number: 002-04632 Rev.*B
Page 57 of 92
S6J311A, S6J3119, S6J3118
(5-1-5) Serial Chip Select Used (SCSCR:CSEN=1)
Mark level "H" of serial clock output (SMR, SCSFR:SCINV=0)
Inactive level "H" of serial chip select (SCSCR, SCSFR:CSLVL=1)
(TA: Recommended operating conditions, VCC=5.0 V +5%/-10%, VSS=AVSS=0.0 V)
Parameter
Symbol
SCS ↓ → SCK ↓
setup time
tCSSI
SCK ↑ → SCS ↑
hold time
tCSHI
SCS
deselect time
tCSDI
SCS ↓ → SCK ↓
setup time
tCSSE
SCK ↑ → SCS ↑
hold time
tCSHE
SCS
deselect time
tCSDE
SCS ↓ → SOT
delay time
tDSE
SCS ↑ → SOT
delay time
tDEE
SCK ↓ → SCS ↓
clock switching
time
Pin Name
SCK0 to SCK3,
SCS0x to SCS3x
SCS0x to SCS3x
SCK0 to SCK3,
SCS0x to SCS3x
SCS0x to SCS3x
SCS0x to SCS3x,
SOT0 to SOT3
SCK0 to SCK3,
SCS0x to SCS3x
tSCC
Master
mode
(CL=50pF,
IOL=-2mA,
IOH=2mA),
(CL=20pF,
IOL=-1mA,
IOH=1mA)
Slave
mode
(CL=50pF,
IOL=-2mA,
IOH=2mA),
(CL=20pF,
IOL=-1mA,
IOH=1mA)
Master
mode
round
operation
(CL=50pF,
IOL=-2mA,
IOH=2mA),
(CL=20pF,
IOL=-1mA,
IOH=1mA)
*1:
tCSSU=SCSTR:CSSU[7:0] x serial chip select timing operating clock
*2:
tCSHD=SCSTR:CSHD[7:0] x serial chip select timing operating clock
*3:
tCSDS=SCSTR:CSDS[15:0] x serial chip select timing operating clock
*1 *2
For details on , , and
*3
Value
Conditions
Min
Max
Unit
tCSSU*1-50
-
ns
tCSHD*2+0
-
ns
tCSDS*3-50
+5tCLK_LCP0A
-
ns
3tCLK_LCP0A
+30
-
ns
0
-
ns
3tCLK_LCP0A
+30
-
ns
-
50
ns
0
-
ns
3tCLK_LCP0A +0
3tCLK_LCP0A +50
ns
Remarks
above, see the hardware manual.
Notes:
• This is the AC characteristic in CLK synchronized mode.
• CL is the load capacitance applied to pins during testing.
• The maximum baud rate is limited by the internal operating clock used and other parameters.
For details, see the hardware manual.
Document Number: 002-04632 Rev.*B
Page 58 of 92
S6J311A, S6J3119, S6J3118
VOH
SCS output
VOL
VOL
tCSHI
tCSSI
SCK output
VOH
tCSDI
VOH
VOL
SOT
(Normal synchronous
transfer)
SOT
(SPI compatible)
Master mode
SCS input
VIH
VIL
VIL
tCSHE
tCSSE
SCK input
VIH
VIL
SOT
(Normal synchronous
transfer)
SOT
(SPI compatible)
VIH
tCSDE
tDEE
VOL
tDSE
VOH
VOL
Slave mode
SCSx output
tSCC
SCSy output
SCK output
VOL
VOL
Clock switching example by master mode round operation
(x,y=0,1,2 : x and y are different value)
Document Number: 002-04632 Rev.*B
Page 59 of 92
S6J311A, S6J3119, S6J3118
(5-1-6) Serial Chip Select Used (SCSCR:CSEN=1)
Serial clock output signal detect level "L" (SMR, SCSFR:SCINV=1)
Serial chip select inactive level "H" (SCSCR, SCSFR:CSLVL=1)
(TA: Recommended operating conditions, VCC=5.0 V +5%/-10%, VSS=AVSS=0.0 V)
Parameter
SCS ↓→ SCK ↑
setup time
Symbol
Pin Name
tCSSI
SCK ↓→ SCS ↑
hold time
tCSHI
SCS
deselect time
tCSDI
SCS ↓ → SCK ↑
setup time
tCSSE
SCK ↓ → SCS ↑
hold time
tCSHE
SCS
deselect time
tCSDE
SCS ↓ → SOT
delay time
tDSE
SCS ↑ → SOT
delay time
tDEE
SCK ↑ → SCS ↓
clock switching
time
tSCC
SCK0 to SCK3,
SCS0x to SCS3x
SCS0x to SCS3x
SCK0 to SCK3,
SCS0x to SCS3x
SCS0x to SCS3x
SCS0x to
SCS3x,
SOT0 to SOT3
SCK0 to SCK3,
SCS0x to SCS3x
Master
mode
(CL=50pF,
IOL=-2mA,
IOH=2mA),
(CL=20pF,
IOL=-1mA,
IOH=1mA)
Slave
mode
(CL=50pF,
IOL=-2mA,
IOH=2mA),
(CL=20pF,
IOL=-1mA,
IOH=1mA)
Master
mode
round
operation
(CL=50pF,
IOL=-2mA,
IOH=2mA),
(CL=20pF,
IOL=-1mA,
IOH=1mA)
*1:
tCSSU=SCSTR:CSSU[7:0] x serial chip select timing operating clock
*2:
tCSHD=SCSTR:CSHD[7:0] x serial chip select timing operating clock
*3:
tCSDS=SCSTR:CSDS[15:0] x serial chip select timing operating clock
*1 *2
For details on , , and
*3
Value
Conditions
Min
Max
Unit
tCSSU*1-50
-
ns
tCSHD*2+0
-
ns
tCSDS*3-50+5
tCLK_LCP0A
-
ns
3tCLK_LCP0A +30
-
ns
0
-
ns
3tCLK_LCP0A +30
-
ns
-
50
ns
0
-
ns
3tCLK_LCP0A +0
3tCLK_LCP0A +50
ns
Remarks
above, see the hardware manual.
Notes:
• This is the AC characteristic in CLK synchronized mode.
• CL is the load capacitance applied to pins during testing.
• The maximum baud rate is limited by the internal operating clock used and other parameters.
For details, see the hardware manual.
Document Number: 002-04632 Rev.*B
Page 60 of 92
S6J311A, S6J3119, S6J3118
SCS output
VOH
VOL
tCSHI
VOL
tCSSI
VOH
tCSDI
VOH
SCK output
VOL
SOT
(Normal synchronous
transfer)
SOT
(SPI compatible)
Master mode
SCS input
VIH
VIL
tCSSE
VIH
SCK input
SOT
(Normal synchronous
transfer)
SOT
(SPI compatible)
VIH
VIL
tCSHE
tCSDE
VIL
tDEE
VOL
tDSE
VOH
VOL
Slave mode
Document Number: 002-04632 Rev.*B
Page 61 of 92
S6J311A, S6J3119, S6J3118
tSCC
SCSx output
SCSy output
VOL
VOH
SCK output
Clock switching example by master mode round operation
(x,y=0,1,2 : x and y are different value)
Document Number: 002-04632 Rev.*B
Page 62 of 92
S6J311A, S6J3119, S6J3118
(5-1-7) Serial Chip Select Used (SCSCR:CSEN=1)
Serial clock output signal detect level "H" (SMR, SCSFR:SCINV=0)
Serial Chip select inactive level "L" (SCSCR, SCSFR:CSLVL=0
(TA: Recommended operating conditions, VCC=5.0 V +5%/-10%, VSS=AVSS=0.0 V)
Parameter
Symbol
SCS ↑ → SCK ↓
setup time
tCSSI
SCK ↑ → SCS ↓
hold time
tCSHI
SCS
deselect time
tCSDI
SCS ↑ → SCK ↓
setup time
tCSSE
SCK ↑ → SCS ↓
hold time
tCSHE
SCS
deselect time
tCSDE
SCS ↑ → SOT
delay time
tDSE
SCS ↓ → SOT
delay time
tDEE
SCK ↓ → SCS ↑
clock switching
time
tSCC
Pin Name
SCK0 to SCK3,
SCS0x to SCS3x
SCS0x to SCS3x
SCK0 to SCK3,
SCS0x to SCS3x
SCS0x to SCS3x
SCS0x to SCS3x,
SOT0 to SOT3
SCK0 to SCK3,
SCS0x to SCS3x
Master
mode
(CL=50pF,
IOL=-2mA,
IOH=2mA),
(CL=20pF,
IOL=-1mA,
IOH=1mA)
Slave
mode
(CL=50pF,
IOL=-2mA,
IOH=2mA),
(CL=20pF,
IOL=-1mA,
IOH=1mA)
Master
mode
round
operation
(CL=50pF,
IOL=-2mA,
IOH=2mA),
(CL=20pF,
IOL=-1mA,
IOH=1mA)
*1:
tCSSU=SCSTR:CSSU[7:0] x serial chip select timing operating clock
*2:
tCSHD=SCSTR:CSHD[7:0] x serial chip select timing operating clock
*3:
tCSDS=SCSTR:CSDS[15:0] x serial chip select timing operating clock
*1 *2
For details on , , and
*3
Value
Conditions
Min
Max
Unit
tCSSU*1-50
-
ns
tCSHD*2+0
-
ns
tCSDS*3-50+5
tCLK_LCP0A
-
ns
3tCLK_LCP0A +30
-
ns
0
-
ns
3tCLK_LCP0A +30
-
ns
-
50
ns
0
-
ns
3tCLK_LCP0A +0
3tCLK_LCP0A +50
ns
Remarks
above, see the hardware manual.
Notes:
• This is the AC characteristic in CLK synchronized mode.
• CL is the load capacitance applied to pins during testing.
• The maximum baud rate is limited by the internal operating clock used and other parameters.
For details, see the hardware manual
Document Number: 002-04632 Rev.*B
Page 63 of 92
S6J311A, S6J3119, S6J3118
SCS output
tCSDI
VOH
VOH
SCK output
VOL
tCSHI
tCSSI
VOH
VOL
SOT
(Normal Sync transfer)
SOT
(SPI compatible)
Master mode
SCS input
tCSDE
VIH
VIH
VIL
tCSHE
tCSSE
VIH
SCK input
VIL
SOT
(Normal Sync
transfer)
tDEE
VOL
tDSE
VOH
VOL
SOT
(SPI compatible)
Slave mode
tSCC
SCSx output
SCSy output
VOL
SCK output
Clock switching example by master mode round operation
(x,y=0,1,2 : x and y are different value.)
Document Number: 002-04632 Rev.*B
Page 64 of 92
S6J311A, S6J3119, S6J3118
(5-1-8) Serial Chip Select Used (SCSCR:CSEN=1)
Serial clock output signal detect level "L" (SMR, SCSFR:SCINV=1)
Serial Chip select inactive level "L" (SCSCR, SCSFR:CSLVL=0)
(TA: Recommended operating conditions, VCC=5.0 V +5%/-10%, VSS=AVSS=0.0 V)
Parameter
Symbol
SCS ↑ → SCK ↑
setup time
tCSSI
SCK ↓ → SCS ↓
hold time
tCSHI
SCS
deselect time
tCSDI
SCS ↑ → SCK ↑
setup time
tCSSE
SCK ↓ → SCS ↓
hold time
tCSHE
SCS
deselect time
tCSDE
SCS ↑ → SOT
delay time
tDSE
SCS ↓ → SOT
delay time
tDEE
SCK ↑ → SCS ↑
clock switching
time
tSCC
Pin Name
SCK0 to SCK3,
SCS0x to SCS3x
SCS0x to SCS3x
SCK0 to SCK3,
SCS0x to SCS3x
SCS0x to SCS3x
SCS0x to SCS3x,
SOT0 to SOT3
SCK0 to SCK3,
SCS0x to SCS3x
Value
Conditions
Master
mode
(CL=50pF,
IOL=-2mA,
IOH=2mA),
(CL=20pF,
IOL=-1mA,
IOH=1mA)
Slave
mode
(CL=50pF,
IOL=-2mA,
IOH=2mA),
(CL=20pF,
IOL=-1mA,
IOH=1mA)
Master
mode
round
operation
(CL=50pF,
IOL=-2mA,
IOH=2mA),
(CL=20pF,
IOL=-1mA,
IOH=1mA)
*1:
tCSSU=SCSTR:CSSU[7:0] x serial chip select timing operating clock
*2:
tCSHD=SCSTR:CSHD[7:0] x serial chip select timing operating clock
Min
Max
Unit
tCSSU*1-50
-
ns
tCSHD*2+0
-
ns
tCSDS*3-50+5
tCLK_LCP0A
-
ns
3tCLK_LCP0A+30
-
ns
0
-
ns
3tCLK_LCP0A+30
-
ns
-
50
ns
0
-
ns
3tCLK_LCP0A+0
3tCLK_LCP0A
+50
ns
Remarks
*3:
tCSDS=SCSTR:CSDS[15:0] x serial chip select timing operating clock
*1 *2
*3
For details on , , and above, see the hardware manual.
Notes:
• This is the AC characteristic in CLK synchronized mode.
• CL is the load capacitance applied to pins during testing.
• The maximum baud rate is limited by the internal operating clock used and other parameters.
For details, see the hardware manual.
Document Number: 002-04632 Rev.*B
Page 65 of 92
S6J311A, S6J3119, S6J3118
tCSDI
VOH
SCS output
VOH
VOH
SCK output
VOL
tCSHI
tCSSI
VOL
SOT
(Normal synchronous transfer)
SOT
(SPI compatible)
Master mode
tCSDE
SCS input
VIH
VIH
SCK input
VIL
SOT
(Normal synchronous
transfer)
SOT
(SPI compatible)
VIL
tCSHE
tCSSE
tDEE
VOL
tDSE
VOH
VOL
Slave mode
SCSx output
tSCC
VOH
SCSy output
VOH
SCK output
Clock switching example by master mode round operation
(x,y=0,1,2 : x and y are different value)
Document Number: 002-04632 Rev.*B
Page 66 of 92
S6J311A, S6J3119, S6J3118
10.4.5.2
UART (Async Serial Interface) Timing
(SMR:MD[2:0]=000B, 001B)
(5-2-1) External clock selected (BGR:EXT=1)
(TA: Recommended operating conditions, VCC=5.0 V +5%/-10%, VSS=AVSS=0.0 V)
Parameter
Symbol
Serial clock
"L" pulse width
tSLSH
Serial clock
"H" pulse width
tSHSL
SCK fall time
tF
SCK rise time
tR
Pin Name
SCK0 to SCK3
tR
SCK
VIL
(CL=50pF,
IOL=-2mA,
IOH=2mA),
(CL=20pF,
IOL=-1mA,
IOH=1mA)
tF
tSHSL
VIH
Value
Conditions
VIH
Min
Max
Unit
tCLK_LCP0A +10
-
ns
tCLK_LCP0A +10
-
ns
-
5
ns
-
5
ns
Remarks
tSLSH
VIL
VIL
VIH
External clock selected
Document Number: 002-04632 Rev.*B
Page 67 of 92
S6J311A, S6J3119, S6J3118
10.4.5.3
LIN Interface (v2.1) (LIN Communication Control Interface (v2.1)) Timing (SMR:MD[2:0]=011B)
(5-3-1) External Clock Selected (BGR:EXT=1)
(TA: Recommended operating conditions, VCC=5.0 V +5%/-10%, VSS=AVSS=0.0 V)
Parameter
Symbol
Serial clock
"L" pulse width
tSLSH
Serial clock
"H" pulse width
tSHSL
SCK fall time
tF
SCK rise time
tR
Pin Name
SCK0 to SCK3
(CL=50pF,
IOL=-2mA,
IOH=2mA),
(CL=20pF,
IOL=-1mA,
IOH=1mA)
tR
SCK
VIL
Value
Conditions
VIH
Max
Unit
tCLK_LCP0A+10
-
ns
tCLK_LCP0A+10
-
ns
-
5
ns
-
5
ns
tF
tSHSL
VIH
Min
VIL
Remarks
tSLSH
VIL
VIH
External clock selected
Document Number: 002-04632 Rev.*B
Page 68 of 92
S6J311A, S6J3119, S6J3118
10.4.5.4
2
I C timing (SMR:MD[2:0]=100B)
(TA: Recommended operating conditions, Vcc=5.0 V +5%/-10%, Vss=AVss=0.0 V)
Parameter
Symbol
Pin Name
SCL clock frequency
fSCL
SCL0 to SCL3
Repeat "start"
condition hold time
SDA↓ → SCL↓
tHDSTA
Conditions
SDA0 to SDA3
SCL0 to SCL3
Standard Mode
Unit
Min
Max
0
100
kHz
4.0
-
µs
4.7
-
µs
Period of "L" for
SCL clock
tLOW
Period of "H" for
SCL clock
tHIGH
4.0
-
µs
Repeat "start"
condition setup time
SCL↑ → SDA↓
tSUSTA
4.7
-
µs
0
3.45*2
µs
250
-
ns
4.0
-
µs
SCL0 to SCL3
CL=50pF,
Data hold time
SCL↓ → SDA↓↑
tHDDAT
Data setup time
SDA↓↑ → SCL↑
tSUDAT
"Stop" condition
setup time
SCL↑ → SDA↑
Bus-free time
between "stop"
condition and "start"
condition
Noise filter
Remarks
R=(Vp/IOL)*1
SDA0 to SDA3
SCL0 to SCL3
tSUSTO
tBUF
-
4.7
-
µs
tSP
-
tNFT*3
-
ns
*1:
R and CL represent the pull-up resistance and load capacitance of the SCL and SDA output lines, respectively Vp shows that the
power-supply voltage of the pull-up resistor and IOL shows the VOL guarantee current.
*2:
The maximum tHDDAT only has to be met if the device does not extend the "L" width (tLOW) of the SCL signal.
*3:
tNFT=(NFCR:NFT[4:0]+1) x 2 x tCLK_LCP0A
Notes:
• In this device, Standard mode ( Max. 100kbps ) is supported only.
• This model does not support high-speed mode. ( Max. 400kbps ).
• This model does not support Min. IOL = 3mA with VOL = 0.4V.
Document Number: 002-04632 Rev.*B
Page 69 of 92
S6J311A, S6J3119, S6J3118
Document Number: 002-04632 Rev.*B
Page 70 of 92
S6J311A, S6J3119, S6J3118
10.5 Timer Input Timing
(TA: Recommended operating conditions, VCC=5.0 V +5%/-10%, VSS=AVSS=0.0 V)
Parameter
Symbol
Pin Name
Value
Conditions
Min
Max
Unit
4tCLK_LCP0
Input pulse
width
tTWH,
tTWL
IN0 to IN11
-
TEXT0 to 5
-
100
-
ns
-
ns
-
ns
4tCLK_LCP0
A
100
4tCLK_LCP0
TIOA0 to TIOA29
TIOB0 to TIOB7
−
A
-
A
100
Remarks
4tCLK_LCP0A ≥100 ns
4tCLK_LCP0A <100 ns
4tCLK_LCP0A ≥100 ns
4tCLK_LCP0A <100 ns
4tCLK_LCP0A ≥100 ns
4tCLK_LCP0A <100 ns
Timer input timing
INx
TEXTx
TIOAx,TIOBx
Document Number: 002-04632 Rev.*B
tTIWH
VIH
tTIWL
VIH
VIL
VIL
Page 71 of 92
S6J311A, S6J3119, S6J3118
10.6 Trigger Input Timing
(TA: Recommended operating conditions, VCC=5.0 V +5%/-10%, VSS=AVSS=0.0 V)
Parameter
Input pulse
width
−
Symbol
tTRGH,
tTRGL
Pin Name
Value
Conditions
INT0 to INT15
INT0 to INT15
Min
Max
Unit
-
100
-
ns
-
1
-
µs
Remarks
Stop mode
Trigger input timing
tTRGH
INTx
Document Number: 002-04632 Rev.*B
VIH
tTRGL
VIH
VIL
VIL
Page 72 of 92
S6J311A, S6J3119, S6J3118
10.7 NMI Input Timing
(TA: Recommended operating conditions, VCC=5.0 V +5%/-10%, VSS=AVSS=0.0 V)
Parameter
Symbol
Input pulse width
−
tNMIL
Pin Name
NMIX
Conditions
-
Value
Min
300
Max
-
Unit
Remarks
ns
NMIX input timing
tNMIL
NMIX
VIH
VIH
VIL
Document Number: 002-04632 Rev.*B
VIL
Page 73 of 92
S6J311A, S6J3119, S6J3118
10.8 Low-Voltage Detection (External Low-Voltage Detection)
(TA: Recommended operating conditions, VSS=AVSS=0.0 V)
Parameter
Power supply
voltage range
Detection voltage
Hysteresis width
Symbol
Pin Name
VDP5
VCC
VDL0
VCC
VDL1
VCC
VDL2
VCC
VHYS
VCC
Value
Conditions
-
Min
Typ
Max
Unit
3.5
-
5.25
V
3.6
3.8
4.0
V
3.8
4.0
4.2
V
*5
4
4.2
4.4
V
-
-
100
-
mV
*1
*3
*1
*4
*1
Remarks
When
power-supply
voltage falls
and detection
level is set
initially
When
power-supply
voltage rises
Low-voltage
Td
30
μs
detection time
Power supply
*2
VCC
-2
2
V/ms
voltage regulation
*1:
If the fluctuation of the power supply has exceeded the detection voltage range within the time less than the low-voltage detection
time (Td), there is the possibility to generate or release after the power supply voltage has exceeded the detection voltage range.
*2:
Please suppress the change of the power supply within the range of the power-supply voltage regulation to do low-voltage
detection by detecting voltage (VDL)
*3:
SYSC0_RUNLVDCFGR.LVDH1V = 0100B or SYSC0_PSSLVDCFGR.LVDH1V = 0100B
*4:
SYSC0_RUNLVDCFGR.LVDH1V = 0101B or SYSC0_PSSLVDCFGR.LVDH1V = 0101B
*5:
SYSC0_RUNLVDCFGR.LVDH1V = 0110B or SYSC0_PSSLVDCFGR.LVDH1V = 0110B
Document Number: 002-04632 Rev.*B
Page 74 of 92
S6J311A, S6J3119, S6J3118
10.9 Low-Voltage Detection (RAM Retention Low-Voltage Detection)
(TA: Recommended operating conditions, VSS=AVSS=0.0 V)
Parameter
Symbol
Pin Name
Value
Conditions
Min
Typ
Max
Unit
Power supply
voltage range
VRDP5
-
-
0.6
-
1.4
V
Detection voltage
VRDL
-
*
0.9
0.95
1.0
V
Hysteresis width
VRHYS
-
-
-
75
-
mV
Remarks
When
power-supply
voltage falls
When
power-supply
voltage rises
Low-voltage
TRd
30
μs
detection time
*:
If the fluctuation of the power supply has exceeded the detection voltage range within the time less than the low-voltage detection
time (TRd), there is the possibility to generate or release after the power supply voltage has exceeded the detection voltage range.
10.10 Low-Voltage Detection (1.2 V Power Supply Low-Voltage Detection)
(TA: Recommended operating conditions, VSS=AVSS=0.0 V)
Parameter
Power supply
voltage range
Symbol
VRDP5
Pin Name
-
-
Min
Typ
Max
Unit
0.6
-
1.4
V
0.92
0.97
1.02
V
1.02
1.07
1.12
V
-
75
-
mV
Remarks
*1
VRDL0
-
Detection voltage
Hysteresis width
Value
Conditions
*2
*4
*1
VRDL1
-
*3
VRHYS
-
-
*4
When
power-supply
voltage falls
When
power-supply
voltage rises
Low-voltage
TRd
30
μs
detection time
*1:
If the fluctuation of the power supply has exceeded the detection voltage range within the time less than the low-voltage detection
time (TRd), there is the possibility to generate or release after the power supply voltage has exceeded the detection voltage range.
*2:
SYSC0_RUNLVDCFGR.LVDL1V = 10B or SYSC0_PSSLVDCFGR.LVDL1V = 10B
*3:
SYSC0_RUNLVDCFGR.LVDL1V = 11B or SYSC0_PSSLVDCFGR.LVDL1V = 11B
4
* : These detection voltage level settings are below the minimum operation voltage.
Between these detection voltages and the minimum operation voltage, MCU functions are not guaranteed except for the low
voltage detector.
Note that although the detection level is below the minimum operation voltage, the LVD reset factor flag is set as the voltage
drops below the detection level.
Document Number: 002-04632 Rev.*B
Page 75 of 92
S6J311A, S6J3119, S6J3118
10.11 A/D Converter
10.11.1 Electrical Characteristics
(TA: Recommended operating conditions, VCC=5.0 V +5%/-10%, VSS=AVSS=0.0 V)
Parameter
Symbol
Value
Pin Name
Min
Typ
Unit
Max
Remarks
Resolution
-
-
-
-
12
bit
Total Error
-
-
-
-
±12
LSB
*3
Integral Nonlinearity
-
-
-
-
±4.0
LSB
*4
Differential Nonlinearity
-
-
-
-
±1.9
LSB
*4
Zero transition voltage
VZT
*6
Full-scale transition
voltage
VFST
*6
Sampling time
tSMP
-
0.3
-
12
µs
*1
Compare time
tCMP
-
0.7
-
28
µs
*1
A/D conversion time
tCNV
-
1.0
-
40
µs
*1
*7
-1.0
-2.0
-3.0
-
1.0
2.0
3.0
µA
AVSS
-
AVRH
V
-
5.25
V
0.0
-
V
500
900
µA
per one unit
*2
Analog port input current
IAIN
*8
Analog input voltage
VAIN
*6
AVRH
Reference voltage
AVRL
IA
Power supply current
IAH
IR
IRH
Variation between
channels
*9
AVRH0,
4.5
AVRH1
AVRL0/AVSS
0,
AVRL1/AVSS
1
AVCC
AVRH
-
-
AVRL
+12.5LSB
AVRH
+10.5LSB
V
*5
V
VAVSS≤
VAIN≤VAVCC
AVCC≥AVRH
-
1.0
100
µA
-
1
2
mA
per one unit
*2
-
-
5.0
µA
-
-
4
LSB
AN32 to AN62 -
-
4
LSB
*10
-
AVRL
-11.5LSB
AVRH
-13.5LSB
*1:
Time for each channel
*2:
The power supply current (VCC=AVCC=5.0V) is specified if the A/D converter is not operating and CPU is stopped.
*3:
Total Error is a comprehensive static error that includes the linearity. 1LSB=(AVRH-AVRL)/4096
*4:
1LSB=(VFST-VZT)/4094
*5:
1LSB=(AVRH-AVRL)/4096
*6:
AN0 to AN3, AN5, AN6, AN9, AN10, AN12 to AN15, AN17 to AN24, and AN27 to AN62
*7
: AN3, AN5, AN6, AN9, AN10, AN12 to AN15, AN17 to AN24, and AN27 to AN42
*8
: AN0 to AN2, and AN43
*9
: AN44 to AN62
*10:
AN0 to AN3, AN5, AN6, AN9, AN10, AN12 to AN15, AN17 to AN24, and AN27 to AN31
Document Number: 002-04632 Rev.*B
Page 76 of 92
S6J311A, S6J3119, S6J3118
10.11.2 Notes on Using A/D Converters
About the output impedance of an external circuit for analog input
When the external impedance is too high, the analog voltage sampling time may become insufficient. In this case, we recommend
attaching a capacitor (about 0.1 µF) to an analog input pin.
Analog Input Circuit Model
Rext
Analog Input
Rint
Source
Comparator
Cext
Cint
Rint : Analog input impedance
3.9 kilo ohms (max) (4.5V≤AVCC≤5.25V)
Cint : Capacitance of MCU input pin
11.0pF (max) (4.5V≤AVCC≤5.25V)
Rext : External driving impedance
Cext : Capacitance of PCB at A/D converter input
The following approximation formula for the replacement model above can be used:
sampling time (minimum) = 9 × ((Rint + Rext) × Cint + Rext × Cext)
Note: Listed values must be considered as reference values.
Document Number: 002-04632 Rev.*B
Page 77 of 92
S6J311A, S6J3119, S6J3118
10.11.3 Definition of terms
Resolution: Analog variation that is recognized by an A/D converter
*
Integral Nonlinearity error : Deviation of the straight line connecting the zero transition point ("0000 0000 0000" <--> "0000 0000
0001") and full-scale transition point ("1111 1111 1110" <--> "1111 1111 1111") from actual conversion characteristics includes zero
transition error, full-scale transition error, and non-linearity error.
Differential Nonlinearity error: Deviation from the ideal value of the input voltage required for changing the output code by 1 LSB
Total error: Difference between the actual value and the theoretical value. The total error includes zero transition error, full-scale
transition error, and non linearity error.
*: Represented as "Linearity error" in the former product series.
Total error
FFF
FFE
Actual conversion
characteristics
1.5LSB
{1 LSB (N - 1) + 0.5LSB}
Digital output
FFD
VNT
(Actually-measured
value)
004
003
Actual conversion
characteristics
002
Ideal characteristics
001
0.5LSB
AVRL
(AVSS)
Analog input
AVRH
Total error of digital output N =
1LSB(Ideal value) =
VNT- {1 LSB × (N-1) + 0.5LSB}
1LSB
AVRH - AVRL
4096
[LSB]
[V]
N: A/D converter digital output value.
VZT(Ideal value) = AVRL + 0.5LSB[V]
VFST(Ideal value) = AVRH - 1.5LSB[V]
VNT: Voltage at which the digital output changes from "(N – 1)" to "N".
Document Number: 002-04632 Rev.*B
Page 78 of 92
S6J311A, S6J3119, S6J3118
Integral Nonlinearity
Differential Nonlinearity
Ideal characteristics
FFE
Actual conversion
characteristics
FFD
{1 LSB (N - 1) + VZT}
N+1
measured
value)
004
VNT
(Actually-measured value)
Actual conversion
characteristics
003
002
Actual conversion
characteristics
VFST (Actually-
Ideal characteristics
Digital output
Digital output
FFF
N
V(N+1)T
(Actuallymeasured
VNT
value)
(Actually-measured value)
Actual conversion
characteristics
N-1
N-2
001
VZT (Actually-measured value)
AVSS
(AVRL)
Analog input
AVRH
Integral Nonlinearity of digital output N =
Differential Nonlinearity of digital output N =
1LSB =
AVSS
(AVRL)
VNT- {1 LSB × (N-1) + VZT}
1LSB
V(N+1) T- VNT
1LSB
VFST - VZT
4094
VZT: Voltage for which digital output changes from "0x000" to "0x001"
VFST: Voltage for which digital output changes from "0xFFE" to "0xFFF".
Document Number: 002-04632 Rev.*B
Analog input
AVRH
[LSB]
-1 LSB [LSB]
[V]
Page 79 of 92
S6J311A, S6J3119, S6J3118
10.12 Flash Memory
Parameter
Sector erase
time
Min
Value
Typ
Remarks
*1
-
300
1100
ms
-
800
3700
ms
288
384
567
945
µs
µs
µs
µs
8-KB sector
Internal preprogramming time included
*1
64-KB sector
Internal preprogramming time included
*1
System-level overhead time excluded
*1
System-level overhead time excluded
*1
System-level overhead time excluded
*1
System-level overhead time excluded
384
µs
System-level overhead time excluded
*1
483
µs
System-level overhead time excluded
*1
651
µs
System-level overhead time excluded
*1
1029
µs
System-level overhead time excluded
*1
-
-
Temperature at write/erase time
Average temperature TA=+85 degrees
Celsius
15
8-bit write time
19
16-bit write time
32-bit write time
27
45
64-bit write time
8-bit (with ECC)
19
write time
16-bit (with ECC)
23
write time
32-bit (with ECC)
31
write time
64-bit (with ECC)
49
write time
*2
Erase count /
1,000/20 years,
Data retention
10,000/10 years,
time
100,000/5 years
*1:
Guaranteed value for up to 100,000 erases
*2:
Unit
Max
Number of erases for each sector
Notes:
• While the Flash memory is written or erased, shutdown of the external power (VCC) is prohibited.
• In the application system where VCC might be shut down while writing or erasing, be sure to turn the power off by using an
external low-voltage detection function.
• To put it concretely, after the external power supply voltage falls below the detection voltage (VDL), hold VCC at 2.7V or more
within the duration calculated by the following expression:
1
2
Td* [µs] + (1 / FCRF* [MHz]) x 1029 + 25 [µs]
*1
: See "10.8 Low-voltage detection (external low-voltage detection)"
*2
: See "10.4.1 Source clock timing"
Document Number: 002-04632 Rev.*B
Page 80 of 92
S6J311A, S6J3119, S6J3118
11. Ordering Information
Part Number
S6J311xHzCSEy0000
Package
144-pin Plastic TEQFP (LEU144)
Note:
• "x"/"y" is a part number option. For the part number option, see the following table.
For details on each package, see "PACKAGE DIMENSIONS."
* z: A/B
12. Part Number Option
Part Number Option "x"
A
9
8
FLASH Memory
1MByte
768KByte
512KByte
Part Number Option "y"
1
2
Sn-Bi & Halogen Free
PureSn & Halogen Free
Part Number Option "z"
A
B
SHE ON
SHE OFF
Document Number: 002-04632 Rev.*B
SHE
Page 81 of 92
S6J311A, S6J3119, S6J3118
13. Package Dimensions
Document Number: 002-04632 Rev.*B
Page 82 of 92
S6J311A, S6J3119, S6J3118
14. Major Changes
Spansion Publication Number: S6J311A_DS708-00004
Page
Section
Revision 0.1
Revision 1.0
1,3
Cover
1,3
Cover
2. Features
6
2.2 Peripheral Functions
2. Features
7
2.2 Peripheral Functions
9
3. Product Lineup
11
4. Pin Assignment
12
5. Pin Description
12~21
5. Pin Description
30
32
33
8. Handling Devices
8. Handling Devices
9. Block Diagram
34
10. Memory Map
36
42,44,52,55
10.Memory Map
12. Electrical Characteristics
12. Electrical Characteristics
12.1 Absolute Maximum Ratings
12. Electrical Characteristics
12.1 Absolute Maximum Ratings
12. Electrical Characteristics
12.1 Absolute Maximum Ratings
12. Electrical Characteristics
12.1 Absolute Maximum Ratings
12. Electrical Characteristics
12.2 Recommended Operating Conditions
12. Electrical Characteristics
12.2 Recommended Operating Conditions
12. Electrical Characteristics
12.2 Recommended Operating Conditions
12. Electrical Characteristics
12.3 DC Characteristics
12. Electrical Characteristics
12.3 DC Characteristics
12. Electrical Characteristics
12.4.2 Internal Clock Timing
12. Electrical Characteristics
12.4.2 Internal Clock Timing
12. Electrical Characteristics
12.4.2 Internal Clock Timing
12. Electrical Characteristics
12.4.2 Internal Clock Timing
12. Electrical Characteristics
12.4.4 Power-on Conditions
12. Electrical Characteristics
12.4.4 Power-on Conditions
42
42
42
43
44
44
44
45
52
55
55
57
58
60
60
Document Number: 002-04632 Rev.*B
Change Results
Initial release
Added the family product names(S6J3119HAA / S6J3118HAA)
Revised the level of this data sheet as full production
Added the information about the memory capacity expansion
Revised the CAN transfer speed to 5Mbps
Added the specifications as full production
Revised the product names of title S6J311AHAA-> S6J311xHAA
Revised the product names of title S6J311AHAA-> S6J311xHAA
Revised the product names of Pin No. S6J311AHAA->
S6J311xHAA
Revised the note of “About power supply pins”
Revised the note of “About C pin processing”(Delete “and pin 38”)
Revised the block diagram of S6J311xHAA as full production
Revised the memory map of S6J311xHAA
(added information of S6J3119HAA / S6J3118HAA)
Revised the product names of title S6J311AHAA-> S6J311xHAA
Added the product names S6J311AHAA-> S6J311xHAA
Revised “Remarks” of Analog supply voltage to “AVCC=VCC”
Revised the note of *2
Revised the symbol of Maximum clamp current
Moved the note of *8 to the bottom of note
Delete the information about CS2
Revised C pin connection diagram
Added “Remarks” of Smoothing capacitor
Revised the minimum value of VIH6
2.0 -> 2.3
Revised the following DC characteristics
ICC5, ICCS5, ICCT52, ICCH52
Revised the product names in the table S6J311AHAA->
S6J311xHAA
Delete the line of FCD0_CLK and tCD0_CLK
Revised the note as follow
FCDO_CLK->FCPU_CLK
Revised the voltage value of Hysteresis input pin (TTL).
2.0V -> 2.3V
Revised the value of Level detection voltage
Added the line of Level release voltage
Page 83 of 92
S6J311A, S6J3119, S6J3118
Page
Section
75
12. Electrical Characteristics
12.4.5.1 CSIO Timing
(SMR:MD[2:0]=010B)
82
12. Electrical Characteristics
12.6 Trigger Input Timing
86
86
89
91
92
92
Revision *A
12. Electrical Characteristics
12.11.1 Electrical Characteristics
12. Electrical Characteristics
12.11.1 Electrical Characteristics
12. Electrical Characteristics
12.11.3 Definition of Terms
12. Electrical Characteristics
12.12 Definition of Terms
13. Ordering Information
14. Part Number Option
1
Features
Cortex-R5 Core
1
Features
Peripheral Functions
1
Features
Peripheral Functions
1
Features
Peripheral Functions
1
Features
Peripheral Functions
1
Features
Peripheral Functions
Document Number: 002-04632 Rev.*B
Change Results
Added the Figure of 5-1-7(1st, 2nd, 3rd)
Deleted the following pin names in the table of “Input pulse width”
and figure of “Trigger input timing”
“RX0”, “RXx”
Revised the value of “Analog port input current” in the table, and
revised the pin name note *7 to *9
Revised the pin name note of “Variation between channels”
*7 -> *10
Revised the note of “Total error”
Deleted the note *3
Revised the note of “Package”
Added the part number options as full production
Revised the following note
(Error)
ECC support for the TCM ports
(Correct)
ECC support for the TCM ports for RAM
Revised the full production and SHE-OFF series as follows:
(Correct)
Built-in flash memory size
−Program: 1024 K + 64 KB (S6J311AHzB*) / 768 K + 64 KB
(S6J3119HzB*) / 512 K + 64 KB (S6J3118HzB*)
−Work: 48 KB (S6J311AHzB*) / 48 KB (S6J3119HzB*) / 48 KB
(S6J3118HzB*)
*z: A/B
Revised the full production and SHE-OFF series as follows:
(Correct)
Built-in RAM size
−TCRAM 64 KB (S6J311AHzB*) / 48 KB (S6J3119HzB*) / 32 KB
(S6J3118HzB*)
−System SRAM 16 KB (S6J311AHzB*) / 16 KB (S6J3119HzB*) / 16
KB (S6J3118HzB*)
−Backup RAM 8 KB (S6J311AHzB*) / Backup RAM 8 KB
(S6J3119HzB*) / Backup RAM 8 KB (S6J3118HzB*)
*z: A/B
Revised the full production and SHE-OFF series as follows:
(Correct)
General-purpose ports: 116 channels (S6J311AHzB*) / 116
channels (S6J3119HzB*) / 116 channels (S6J3118HzB*)
*z: A/B
Revised the full production and SHE-OFF series as follows:
(Correct)
A/D converter (successive approximation type)
12-bit resolution, 2 units mounted: Max 56 channels (25 channels +
31 channels) (S6J311AHzB*) / Max 56 channels (25 channels + 31
channels) (S6J3119HzB*) / Max 56 channels (25 channels + 31
channels) (S6J3118HzB*)
*z: A/B
Revised the full production and SHE-OFF series as follows:
(Correct)
Multi-function serial (transmission and reception FIFOs
mounted) :Max 4 channels (S6J311AHzB*) / Max 4 channels
(S6J3119HzB*) / Max 4 channels (S6J3118HzB*)
*z: A/B
Page 84 of 92
S6J311A, S6J3119, S6J3118
Page
Section
Change Results
Added the following function lists:
2
1
FEATURES
Peripheral Functions
<I C>
- Full-duplex double buffering system, 64-byte transmission FIFO,
64-byte reception FIFO.
−Standard mode ( Max. 100kbps ) is supported only.
−DMA transfer is supported
2
FEATURES
Peripheral Functions
CAN controller: CAN-FD Max 1 channel
2
Features
Peripheral Functions
2
Features
Peripheral Functions
4
1. Product Lineup
4
1. Product Lineup
4
1. Product Lineup
5
1.Product Lineup
Document Number: 002-04632 Rev.*B
Added the following function list:
−32 message buffer/channel (transmission message buffer size)
Revised the full production and SHE-OFF series as follows:
(Correct)
−Package: LEU144 (S6J311xHzB*)
*z: A/B
Added ”−Partial wakeup function”
Revised the full production and SHE-OFF series of “Table 3-1
Memory Size”
(Error)
S6J311AHAA
S6J3119HAA
S6J3118HAA
(Correct)
S6J311AHzB*
S6J3119HzB*
S6J3118HzB*
*z: A/B
Added Table 3-2. SHE option as follows:
Table 1-2. SHE option
S6J311xHAB*
S6J311xHBB*
Security (SHE)
ON
OFF
* x: A/9/8
Revised the full production and SHE-OFF series of “Table 1-3:
Product Lineup”
(Error)
S6J311xHAA
(Correct)
S6J311xHzB*
* x: A/9/8, z: A/B
Added ”Partial wakeup function”
Page 85 of 92
S6J311A, S6J3119, S6J3118
Page
Section
Change Results
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
VCC
P421/SIN2_1/TRACECTL
P420/SCK2_1/TRACECLK
P418/INT14_0/SCS22_0
P417/INT15_1/TIOA23_1
P416/IN5_0/TIOA22_1
P414/SCS21_0
P413/INT14_1/SCS20_0
P411/INT13_1/SCK2_0/SCL2_0/TRACEDATA7
P409/SOT2_0/SDA2_0/TIOA24_1/TRACEDATA6
P408/INT12_0/SIN2_0/TRACEDATA5
P407/TRACEDATA4
P406/TRACEDATA3
P405/INT11_0/IN4_0/TRACEDATA2
P404/IN3_0/TRACEDATA1
P403/IN2_0/TRACEDATA0
P402/INT2_0/IN1_0
P401/IN0_0
C
VSS
VCC
RSTX
P400
P331
VSS
X1
X0
MD
P330
P327
TCK
TMS
TDI/P324
TDO/P323
TRST/P322
VCC
Revised “Figure 2-1 Pin Assignment for S6J311xHzB*” as follows.
(Correct)
* x: A/9/8, z: A/B
6
2. Pin Assignment
VSS
P000/SOT2_1
P001/SCS20_1
P003/SCS22_1
P005/SIN3_0/IN6_0
P006/SDA3_0/SOT3_0/IN7_0
P007/SCK3_0/SCL3_0/IN8_0
P008/SCS30_0/IN9_0/TIOA0_0
P009/INT0_1/IN10_0/TIOA1_0
P010/IN11_0/TIOA2_0
P012/OUT5_0/TIOA3_0
P013/OUT6_0/TIOA4_0
P015/OUT7_0/TIOA5_0
P016/OUT8_0/TIOA6_0
P017/OUT9_0/TIOA7_0
P018/OUT10_0/TIOA8_0
P019/TEXT0_0/OUT11_0/TIOB0_0
P020/SOT0_0/SDA0_0/TEXT1_0/TIOB1_0
P021/SCK0_0/SCL0_0/TIOB2_0
P022/INT3_0/SIN0_0/TIOB3_0
P023/SCS0_0/TIOB4_0
P024/TIOB5_0
P027/INT1_1/TEXT0_1/TIOB6_0/TIOA4_1
P028/INT4_0/SIN1_0/OUT0_1/TIOB7_0
P029/AN0/SOT1_0/SDA1_0/OUT1_1
P030/OUT2_1
P031/AN1/SCS1_0/OUT3_1
P100/AN2/SCK1_0/SCL1_0/OUT4_1
P101/AN3/OUT5_1
P103/AN5/OUT6_1
P105/OUT7_1/TIOA9_0
P106/OUT8_1
P107/INT2_1/OUT9_1/TIOA10_0
P108/INT3_1/AN6/OUT10_1/TIOA11_0
P109/OUT11_1/TIOA12_0
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
●
TOP VIEW
LEU-144
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
VSS
P321/PWUTRG
VSS
VCC
P317/INT11_1/AN62/TIOA9_1
P315/AN61/IN5_1/TIOA8_1
P314/AN60/IN4_1/TIOA7_1
P313/INT10_1/AN59/IN3_1
P312/AN58/IN2_1
P309/AN57/IN1_1/TIOA29_1
P308/AN56/IN0_1/TIOA28_1
P307/INT1_0/AN55/RX0_0
P306/AN54/TX0_0
NMIX
P305/AN53/TEXT5_0/TIOA29_0
P304/AN52/TEXT4_0/TIOA20_1
P302/AN51/TIOA19_1
P301/AN50/OUT4_0/TIOA18_1
P300/AN49/OUT3_0/TIOA28_0
P231/AN48/OUT2_0/TIOA27_0
P230/AN47/PWU_AN7/OUT1_0/TIOA26_0
P229/INT8_0/AN46/PWU_AN6/RX0_1/OUT0_0/TIOA25_0
P228/AN45/PWU_AN5/TX0_1/TIOA24_0
P227/AN44/PWU_AN4/TIOA23_0
AVCC1
AVRH1
AVSS1/AVRL1
P226/AN43/PWU_AN3/IN11_2/TIOA17_1
P225/INT0_0/AN42/PWU_AN2/RX0_2/IN10_2
P224/AN41/PWU_AN1/TX0_2/IN9_2
P223/AN40/PWU_AN0/IN8_2
P222/INT7_0/AN39/IN7_2
P220/AN38/IN6_2
P219/AN37/TEXT3_0
P218/AN36/TEXT2_0
VSS
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
VCC
P215/INT9_1/IN5_2/TIOA16_1
P214/IN4_2/TIOA15_1
P213/INT8_1/IN3_2/TIOA14_1
P212/AN35/IN2_2/TIOA13_1
P211/AN34/IN1_2/TIOA22_0
P210/INT6_0/AN33/IN0_2/TIOA21_0
P209/AN32/TIOA20_0
P208/AN31/TIOA19_0
P207/INT7_1/AN30/TEXT5_1
P206/AN29/TEXT4_1
P205/AN28/TEXT3_1
P204/AN27/IN11_1
P203/IN10_1
P202/INT6_1/IN9_1
P131/AN24/IN8_1
P130/INT5_0/AN23/IN7_1
P129/AN22/IN6_1
P128/AN21/TEXT2_1
P127/AN20/TEXT1_1
P126/AN19
P123/AN18/TIOA12_1
P122/AN17/TIOA11_1
P120/AN15
P119/AN14
P118/INT5_1/AN13
P117/INT4_1/AN12
P115
AVSS0/AVRL0
AVRH0
AVCC0
P114/AN10/TIOA6_1
P113/TIOA5_1
P112/AN9/TIOA13_0
C
VSS
7
7 to 13
3. Pin Description
3. Pin Description
Document Number: 002-04632 Rev.*B
Revised the tables as follows for full production.
(Correct)
Table 3-1 S6J311xHzB* Pin Functions
* x: A/9/8, z: A/B
Added the I2C function to Pin 6,7,18,19,25,28,135,136.
Pin 6
Pin 7
Pin 18
Pin 19
Pin 25
Pin 28
Pin 135
Pin 136
SDA3_0
SCL3_0
SDA0_0
SCL0_0
SDA1_0
SCL1_0
SDA2_0
SCL2_0
2
I C bus ch.3 serial data I/O pin
2
I C bus ch.3 serial clock I/O pin
2
I C bus ch.0 serial data I/O pin
2
I C bus ch.0 serial clock I/O pin
2
I C bus ch.1 serial data I/O pin
2
I C bus ch.1 serial clock I/O pin
2
I C bus ch.2 serial data I/O pin
2
I C bus ch.2 serial clock I/O pin
Page 86 of 92
S6J311A, S6J3119, S6J3118
Page
Section
Change Results
Added the Partial wakeup function from Pin 78to Pin 81, and from
Pin 85 to Pin88.
11
3. Pin Description
78
AN40
PWU_AN0
ADC analog 40 input pin
Partial wakeup ADC analog 0 input pin
79
AN41
PWU_AN1
ADC analog 41 input pin
Partial wakeup ADC analog 1 input pin
80
AN42
PWU_AN2
ADC analog 42 input pin
Partial wakeup ADC analog 2 input pin
81
AN43
PWU_AN3
ADC analog 43 input pin
Partial wakeup ADC analog 3 input pin
85
AN44
PWU_AN4
ADC analog 44 input pin
Partial wakeup ADC analog 4 input pin
86
AN45
PWU_AN5
ADC analog 45 input pin
Partial wakeup ADC analog 5 input pin
87
AN46
PWU_AN6
ADC analog 46 input pin
Partial wakeup ADC analog 6 input pin
88
AN47
ADC analog 47 input pin
PWU_AN7
Partial wakeup ADC analog 7 input pin
Revised the “I/O Circuit Type “and add PWUTRG to Pin 107
(Correct)
12
3.Pin Description
Document Number: 002-04632 Rev.*B
107
P321
PWUTRG
-
R
General-purpose output port
Partial wakeup trigger output pin
Page 87 of 92
S6J311A, S6J3119, S6J3118
Page
Section
Change Results
Revised Type C of “I/O Circuit Type” as follows:
(Correct)
15
4. I/O Circuit Types
Mode
input
Added Type R to “11. I/O Circuit Type”
R
Digital output
17
4. I/O Circuit Types
22
5.Handling Devices
22
5.Handling Devices
23
7.Block Diagram
23
7.Block Diagram
24
8.Memory Map
25
8.Memory Map
Document Number: 002-04632 Rev.*B
Digital output
Output of 2 mA
Revised the following notice.
(Error)
About the Power-on Time
To prevent the internal built-in voltage step-down circuit from
malfunctioning, secure a voltage rising time of 50 μs (between 0.2 V
and 2.7 V) or longer at the power-on time.
(Correct)
About the Power-on Time
To prevent a malfunction of the voltage step-down circuit built in the
device, the voltage rising must be monotonic during power-on.
Revised the item as follows:
(Error)
This device has a built-in voltage step-down circuit. Be sure to
connect a capacitor to the C pin (pin 126 in S6J311xHAA
specifications)
(Correct)
This device has a built-in voltage step-down circuit. Be sure to
connect a capacitor to the C pin (pin 126 in S6J311xHzB*
specifications)
＊
x:A/9/8, z: A/B
Revised the title as follows:
(Error)
Figure 7-1 S6J311xHAA Block Diagram
(Correct)
Figure 7-1 S6J311xHzB* Block Diagram
* x: A/9/8, z: A/B
Added “Partial Wake up” to “Block Diagram”
Revised Figure 8-1 as follows
(Correct)
Figure 8-1 Memory Map (S6J311AHzB/9HzB/8HzB*) * z: A/B
Added item as follows:
“The ECC movement in TCM port is based on ECC setting inside
the CPU.”
Page 88 of 92
S6J311A, S6J3119, S6J3118
Page
Section
26
8.Memory Map
28
8.Memory Map
Change Results
Revised " S6J311xHAA Peripheral Map" as follows
(Correct)
S6J311xHzB* Peripheral Map
* x:A/9/8, z:A/B
Added “Partial Wake Up” to address of “B484_8400 to B484_87FF”.
B484_8400
B484_87FF
APPS #5
A/D unit1 , Partial Wake Up
297
Revised the memory map of APPS#5 as follows.
(Correct)
28
8.Memory Map
B484_8C00
B484_8FFF
B484_9000
B484_93FF
B484_9400
B484_FFFF
Reserved
APPS #5
Global Timer
Reserved
300
-
Added the following comments and restriction under the table of
“APPS#5 area”
28
8. Memory Map
When MPU attribute of Cortex-R5 is configured as "Normal", store
buffer inside Cortex-R5 can operate and write data can be merged.
To avoid influence of this data merger, MPU attribute
"Device" or "Strongly Ordered" should be used.
MPU attribute "Device" or "Strongly Ordered" must be used for
areas below, to avoid this influence.
− Backup RAM area (BACKUP_RAM) [0E80_0000 ~ 0E87_FFFF]
− Peripheral area (Peri area) [B000_0000 ~ B7FF_FFFF]
− Error Config area (ERRCFG) [FFFE_E000 ~ FFFE_FFFF]
MPU attribute "Device" or "Strongly Ordered" is required for
accesses to areas below, in particular situation.
− FLASH Memory (when writing commands)
SHE OFF product is prohibited to access SHE area (B200_0000 to
B20F_FFFF)
2
29,30
9. Pin Status in CPU Status
31
9. Pin Status in CPU Status
32,33
10. Electrical Characteristics
10.1 Absolute Maximum Ratings
10. Electrical Characteristics
10.2 Recommended Operating Conditions
34
Document Number: 002-04632 Rev.*B
Added Pin name about I C and PWU to Table 9-1 Pin State Table
(1/2) and Table 9-2 Pin State Table (2/2).
Added the item as follows
*5: When the PWU function is enabled, a change to output occurs.
*7: When PPC_PCFGRijj:POF[2:0] is set to initial value.
Revised “S6J311xHAA” to “S6J311xHzB”
Added ”* x:A/9/8, z:A/B” to “*8”.
Revised “S6J311xHAA” to “S6J311xHzB”
Added ”* x: A/9/8, z: A/B”.
Page 89 of 92
S6J311A, S6J3119, S6J3118
Page
Section
Change Results
Added the following notes
35
10. Electrical Characteristics
10.2 Recommended operating conditions
35
10. Electrical Characteristics
10.2 Recommended operating conditions
35,36
10. Electrical Characteristics
10.2 Recommended operating conditions
41
10. Electrical Characteristics
10.3 DC Characteristics
10. Electrical Characteristics
10.3 DC Characteristics
10. Electrical Characteristics
10.3 DC Characteristics
10. Electrical Characteristics
10.4.2 Internal Clock Timing
43
43
45
49
10. Electrical Characteristics
10.4.4 Power-on Conditions
69,70
10. Electrical Characteristics
10.4.5.4 I2C timing (SMR:MD[2:0]=100B)
10. Electrical Characteristics
10.9 Low-Voltage Detection (RAM
Retention Low-Voltage Detection)
10. Electrical Characteristics
10.10 Low-Voltage Detection (1.2 V Power
Supply Low-Voltage Detection)
75
75
-The following condition should be satisfied in order to facilitate heat
dissipation.
1.4 or more layers PCB should be used.
2.The area of PCB should be 114.3 mm x 76.2 mm or more, and the
thickness should be 1.6 mm or more. (JEDEC standard)
3.1 layer of middle layers at least should be used for dedicated
layer to radiate heat with residual copper rate 90% or more. The
layer can be used for system ground.
4.35~50% of the die stage area which is exposed at back surface of
package should be soldered to a part of 1st layer.
5.The part of 1st layer should be connected to the dedicated heat
radiation layer with more than 10 thermal via holes.
Added the following notes
−Figure10.2-1 is a schematic diagram showing PCB in section.
−Figure10.2-2 in the following pages are recommended land
patterns for each package series. Thermal via holes should closely
be placed and aligned with lands.
−If you are considering application under any conditions other than
listed herein, please contact sales representatives beforehand.
Added the following figures
Figure 10.2-1: Example thermal via holes on PCB.
Figure 10.2-2: Land Pattern and Thermal Via LEU144
Deleted the pin name “P321” in Rup3 of Pull-up register.
Revised “S6J311xHAA” to “S6J311xHzB”
Added”* x: A/9/8, z: A/B”.
Added the following symbol and value
ICCP
Revised “S6J311xHAA” to “S6J311xHzB”
Added”* x: A/9/8, z: A/B”.
Deleted the Slope detection undetected specification.
Added the Power ramp rate and Maximum ramp rate guaranteed
to not generate power-on reset.
*1, *2: Changed the sentence.
Added *3, *4, Note, Figure at the Power off time, Power ramp rate,
Maximum ramp rate guaranteed to not generate power-on reset.
2
Added”10.4.5.4 I C timing (SMR:MD[2:0]=100B)” as a new item.
Revised the title in 10.9 “Internal Low-Voltage Detection” to “RAM
Retention Low-Voltage Detection”.
Added the notice *4
81
11. Ordering Information
Added SHE option to the part number
81
11. Ordering Information
Revised Package Code “LES144” to “LEU144”
81
12. Part Number Option
Added Part Number Option “z” as SHE option
Document Number: 002-04632 Rev.*B
Page 90 of 92
S6J311A, S6J3119, S6J3118
Document History
Document Title: S6J311A, S6J3119, S6J3118 32-Bit Traveo™ Family S6J3110 Series Microcontroller Datasheet
Document Number: 002-04632
Revision
ECN
**
-
Orig. of
Submission
Change
Date
MNII
01/16/2015
Description of Change
Migrated to Cypress and assigned document number 002-04632.
No change to document contents or format.
Updated to Cypress format.
Adapted to full-production.
*A
5272677
MNII
05/16/2016
Added some characteristics.
For detail, see “Major Changes”.
Page 1,
Revised the title as follows
(error)
S6J3110 Series
32-Bit TraveoTM Family
Microcontroller Datasheet
(correct)
*B
5311072
WECU
06/20/2016
S6J311A, S6J3119, S6J3118
32-Bit Traveo™ Family
S6J3110 Series Microcontroller Datasheet
Page 2, Features
Added “CAN-FD (V3.2.0)” under “CAN controller: CAN-FD Max 1 channel”.
In page of 1,2,4 to 14,22 to 24,26,32,34,43,45,46,49,81
Revised part number from S6J311xxxB to S6J311xxxC.
Document Number: 002-04632 Rev.*B
Page 91 of 92
S6J311A, S6J3119, S6J3118
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© Cypress Semiconductor Corporation, 2015-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress
products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support
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failure of the device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform
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Document Number: 002-04632 Rev.*B
June 20, 2016
Page 92 of 92