LatticeECP3™ Serial Protocol Board – Revision D User’s Guide July 2010 Revision: EB44_01.3 Lattice Semiconductor LatticeECP3 Serial Protocol Board – Revision D User’s Guide Introduction The LatticeECP3 Serial Protocol Board (referred to in this document as “SPB”) allows designers to investigate and experiment with the features of the LatticeECP3 high-speed SERDES transceivers. The SPB is available for full and detailed characterization of the high speed I/O channels and includes interfaces for some of the latest protocol interconnections. The features of the LatticeECP3 Serial Protocol Board can assist engineers with rapid-prototyping and testing their specific designs. The board is an enhanced form-factor of the PCI Express add-in card specification. It allows for x4 PCI Express interconnection that is available for demonstration purposes with some non-standard form-factor issues. The board has several debugging and analyzing features for complete evaluation of the LatticeECP3 device. This guide is intended to be referenced in conjunction with evaluation design tutorials to demonstrate the LatticeECP3 FPGA. The evaluation board includes provisioning to connect high-speed SERDES channels via SMA connectors to test and measurement equipment. The board is manufactured using standard FR4 dielectric and through-hole vias. The nominal impedance is 50-ohm for single-ended traces and 100-ohm for differential traces. Figure 1. LatticeECP3 Serial Protocol Board Board Features • PCI Express x4 edge connector interfaces – Allow demonstration of PCI Express (x4) interfaces – x4 is non-compliant but will demonstrate x4 functionality with an open-frame motherboard • Allow control of SERDES PCS registers using the Serial Client Interface (ORCAstra) • Serial ATA interfaces for host and target configurations 2 Lattice Semiconductor LatticeECP3 Serial Protocol Board – Revision D User’s Guide • RJ45 interface to 10/100/1000 Ethernet • On-board Boot Flash. – 64M Serial SPI Flash – Parallel Flash via MachXO™ Crossover PLD programming bridge • Switches, LEDs, displays for demo purposes • Several debug and analysis connections • Input connection for lab-power supply • Power connections and power sources • ispVM™ programming support • On-board and external reference clock sources The contents of this user’s guide include top-level functional descriptions of the various portions of the evaluation board, descriptions of the on-board connectors, diodes and switches and a complete set of schematics of the board. Figure 2. Serial Protocol Board Outline Drawing LatticeECP3 Device This board features a LatticeECP3 FPGA with a 1.2V core supply. It can accommodate all pin compatible LatticeECP3 devices in the 1156-ball fpBGA (1mm pitch) package. A complete description of this device can be found in the LatticeECP3 Family Data Sheet. Note: The connections referenced in this document refer to the LFE3-95E-FF1156 device. Available I/Os and associated sysIO™ banks may differ for other densities within this device family. 3 LatticeECP3 Serial Protocol Board – Revision D User’s Guide Lattice Semiconductor Applying Power to the Board The LatticeECP3 Serial Protocol Board is ready to power on. The board can be supplied with power from an AC wall-type transformer power supply shipped with the board. Or, it can be supplied from an benchtop supply via terminal screw connections. It also has provisions to be supplied from the PCI Express edge fingers from a host board. To supply power from the factory-supplied wall transformer, simply connect the output connection of the power cord to J1 and plug wall-transformer into an AC wall outlet. Power Supplies (see Appendix A, Figure 20) The evaluation board incorporates an alternate scheme to provide power to the board. The board is equipped to accept a main supply via the TB1 connection. This connection is provided to use with a benchtop supply adjusted to provide a nominal +12V DC. An indicator (D1) will illuminate when 12V is applied to the board. All input power sources and on-board power supplies are fused with surface mounted fuses and have green LEDs to indicate power GOOD status of the intermediate supplies. Table 1. Board Power Supply Fuses and Indicators LEDs (see Appendix A, Figure 20) Fuse Designator Function Power Good LED Designator Function F1 12V Input Supply Fuse D1 12V Input Good Indicator F2 1.5V Fuse D6 1.5V Good Indicator F3 1.2V Core Fuse D3 1.2V Core Good Indicator F4 3.3V Fuse D4 3.3V Good Indicator F5 1.8V Fuse D7 1.8V Good Indicator F6 1.2V Analog Supply D2 1.2V VCCA Good Indicator F7 2.5V Fuse D5 2.5V Good Indicator Power can be supplied with either a wall transformer pack, or another external source. Table 2. External Board Supply Input Terminal (see Appendix A, Figure 20) TB1 Screw terminal for 12V DC Pin 1(square PCB pad) -> +12V DC Pin 2 -> Ground The above-mentioned supplies can be isolated from the on-board regulators by removal of the associated fuse. Surface-mounted test loops are provided to apply alternative power sources to these supplies as required for testing purposes. 4 LatticeECP3 Serial Protocol Board – Revision D User’s Guide Lattice Semiconductor Table 3. Power Supply Test Connections Test Point Designator Supply LP1 2.5V LP2 1.5V LP3 3.3V LP4 1.8V LP5 1.2V VCCA LP6 1.2V VCC Core PCI Express Power Interface Power can be sourced to the board via the PCB edge fingers (CN1). This interface allows the user to provide power from a PCI Express host board. Power Management The evaluation board includes a Lattice ispPAC®-POWR1220AT8 programmable power management IC (U10). This device controls the power sequence and monitors designated board supplies. The POWER GOOD indication LEDS are controlled via this device. The power management device is factory programmed to control the power supplies. A block diagram of the power management is shown in Figure 3. Figure 3. Power Management Block Diagram VCC Core, +1.2v , 10A 12V INPUT POL PCIe Edge 12V Wall Adapter 12V Input Terminal 3.3VIN, +2.5V, 6A POL LDO ispPAC 1_5V, +1.5V, 2A LDO 1_8V, +1.8V, 2A LDO 1_2VA, +1.2V, 1.5A ETH_1_2V, +1.2V, 0.5A LDO LDO 2_5V, +2.5V, 1.5A MOSFET 3_3V, +3.3V, 2A Programming/FPGA Configuration (see Appendix A, Figure 23) A programming header is provided on the evaluation board, providing access to the LatticeECP3 JTAG port. Note: An ispDOWNLOAD™ Cable is included with each ispLEVER®-Base or ispLEVER-Advanced design tool shipment. Cables may also be purchased separately from Lattice. ispVM Download Interface J12 is an 10-pin JTAG connector used in conjunction with the ispVM USB download cable to program and control the device. 5 LatticeECP3 Serial Protocol Board – Revision D User’s Guide Lattice Semiconductor Table 4. Standard ispVM Programming Cable Configuration Pin Description Pin 1 VCC Pin 2 TDO Pin 3 TDI Pin 4 PROGRAMN1 Pin 5 Enable used for alternate programming of the ispPAC-POWR1220AT8 device Pin 6 TMS Pin 7 GND Pin 8 TCK Pin 9 DONE1 Pin 10 INITN1 1. Denotes optional connection to programming cable. After initial board setup, use the following procedure to program the evaluation board. Instructions assume ispVM software has been installed on a local PC. Connect the ispDOWNLOAD cable rainbow-colored flywires to the connector J12. Pin 1 = red, 2 = brown, 3 = orange, 4 = open, 5 = open, 6 = purple, 7 = black, 8 = white, 9 = open, 10 = open. Table 5. ispVM JTAG Connector (see Appendix A, Figure 23) NC NC 10 9 NC 8 7 6 5 4 3 2 1 Pin Function Color 1 PWR Red 2 TDO Brown 3 TDI Orange 5 ISPEN Yellow1 6 TMS Purple 7 GND Black 8 TCK White 1. Only connected for programming the ispPAC-POWR1220AT8 device. Programming the Daisy Chain (see Appendix A, Figure 23) This board includes three Lattice programmable (U1=LFE395, U17= LCMXO1200C, and U13 = POWR1220AT8) devices that can be programmed in a daisy chain. The board also includes a mechanism to daisy chain other Lattice evaluation boards that use the same connector standard. 6 LatticeECP3 Serial Protocol Board – Revision D User’s Guide Lattice Semiconductor Figure 4. JTAG Chain ispVM Cable TCK TCK TMS TMS TDI Daisy Chain Off-Board Buffer TDI TDI TDO TDI TDO TDI TDO J9 ispEN J12 LatticeECP3 MachXO Power Manager II Board Jumpers ATDI An alternative chain can be used when it is desired to only communicate with the ispPAC-POWR1220AT8 device. This alternative method utilizes the ispEN pin to drive the TDISEL input. A logic “1 “driven on the TDISEL of the ispPAC-POWR1220AT8 will enable the ATDI input ignoring the TDI data of the board JTAG chain and receiving TDI data directly from the ispVM input. A 2x3 header(J41) completes the on-board JTAG chain between the LatticeECP3 FPGA, the MachXO1200 CPLD and the ispPAC-POWR1220 devices. These jumpers must be in place for proper operation with ispVM. Figure 5. ALL Devices in Chain Selection (J41) JTAG daisy-chaining across multiple boards is provisioned on board by jumpers. Header J8 controls the data path to and from the evaluation board TDO. The board is factory programmed with a jumper across pins 1 and 2 of J8. If the user needs to build a JTAG daisy-chain to another Lattice evaluation board the user needs to place jumpers between pins 1 and 3 and 2 and 4 respectively. This will alter the data path off-board via J9, which typically can be connected to another ispVM connector of a Lattice Semiconductor evaluation board. J10 and J11 can also be used for off-board daisy-chaining to wire AND the PROGRAMN and INITN pin respectively between the boards. Download Procedure Requirements: • PC with ispVM System v.17.4 (or later) programming management software, installed with appropriate drivers (USB driver for USB Cable, Windows NT/2000/XP parallel port driver for ispDOWNLOAD Cable). Note: An option to install these drivers is included as part of the ispVM System setup. • ispDOWNLOAD Cable (pDS4102-DL2A, HW7265-DL3A, HW-USB-1A, etc.) JTAG Download The LatticeECP3 device can be configured easily via its JTAG port. The device is SRAM-based; it must remain powered on to retain its configuration when programmed in this fashion. 1. Connect the LatticeECP3 Serial Protocol Board to the appropriate power sources and power up board. 2. Connect the ispDOWNLOAD cable to the appropriate header. J12 is used for the 1x10 cable. 3. Start the ispVM System software. 4. Press the SCAN button located in the toolbar. The LatticeECP3 and the MachXO1200 devices will be automatically detected. 7 Lattice Semiconductor LatticeECP3 Serial Protocol Board – Revision D User’s Guide Figure 6. Main Downloading Window 5. Double-click the device to open the device information dialog. In the device information dialog, click the Browse button located under Data File. Locate the desired bitstream file (.bit). Click OK to both dialog boxes. 6. Add the data file from the Browse dialog and select OK when complete. 7. To program only the LatticeECP3-95, place the LCMXO1200C and the ispPAC-POWR1220AT8 devices into BYPASS and the LFE3-95 into Erase, Program, Verify mode, as shown below. Figure 7. Device Information Window 8 Lattice Semiconductor LatticeECP3 Serial Protocol Board – Revision D User’s Guide Figure 8. Successful Programming Session 8. Click the green GO button. This will begin the download process into the device. Upon successful download, the device will be operational. Programming the Power Manager Device The J12 header can be used to isolate and program the ispPAC-POWR1220AT8 Power Manager device. This device can be isolated from the others on the chain using the optional ispEN connection from the ispVM programming cable. Connecting ispEN to pin 5 on J12 and selecting the optional control in ispVM will isolate the Power Manager. The connection is activated from the Options pull-down menu of the ispVM toolbar. The Cable and I/O Port Setup dialog box is used to select the polarity of this connection to SET LOW. 9 Lattice Semiconductor LatticeECP3 Serial Protocol Board – Revision D User’s Guide Figure 9. Setup for ISPEN Usage Figure 10. Programming of ispPAC-POWR1220AT8 Power Manager Device Note: The ispEN connection must be disconnected for complete programming of the other devices on the SPB. Configuration Status Indicators (see Appendix A, Figure 23) These LEDs indicate the status of configuration to the FPGA. • D8 (red) illuminated, this indicates that the programming was aborted or reinitialized driving the INITN output low. • D11 (green) illuminated, this indicates the successful completion of configuration by releasing the open collector DONE output pin. • D12 (green) will flash indicating TDI activity. 10 LatticeECP3 Serial Protocol Board – Revision D User’s Guide Lattice Semiconductor • D10 (red) illuminated, this indicates that PROGRAMN is low. • D9 (red) illuminated, this indicates that GSRN is low. PROGRAMN and GSRN (see Appendix A, Figure 23) • These push-button switches assert/de-assert the logic levels on the PROGRAMN (SW3) and GSRN (SW1). Depressing the button drives a logic level “0” to the device. CFG [2:0] (see Appendix A, Figure 23) • The FPGA CFG pins are set on the board for a particular programming mode via the SW2 DIP switch. • JTAG programming is independent of the MODE pins and is always available to the user. • Pushing in (depressing) the switch is ON and sets the value to 0. Table 6. CFG Mode Selections CFG2 CFG1 CFG0 Configuration Mode 0(ON) 0(ON) 0(ON) SPI Flash 0(ON) 1(OFF) 0(ON) SPIm 1(OFF) 0(ON) 1(OFF) Slave Serial 1(OFF) 1(OFF) 1(OFF) Slave Parallel X (don’t care) X (don’t care) X (don’t care) ispJTAG On-Board Serial SPI Flash Memory (see Appendix A, Figure 23) • One Serial SPI (16-pin TSSOP 64M) Flash memory devices (U11) is on-board for non-volatile configuration memory storage. Either a STMicro M25P64VMF16 or Macronix MX25L6405 device is populated on-board. • The CFG [2:0] need to be [000] all depressed to read the Flash memory at power-up or after toggling the PROGRAMN pin. • J11 must have a jumper between pins 1 and 2. Programming Serial SPI Flash Memory The Serial SPI Flash memory device can be configured easily via its JTAG port. This mode enables the FPGA to be programmed at power-up or assertion of PROGRAMN with a bitstream stored in the memory device. 1. Connect the evaluation board to the appropriate power sources and power up board. 2. Connect the ispDOWNLOAD cable to the appropriate header. J9 is used for the 1x10 cable. 3. Start the ispVM System software. 4. Press the Scan button located in the toolbar. The LFE3-9, LCMXO1200C and ispPOWR1220AT8 devices will be automatically detected. 5. Double-click the Operation column for the LFE3-95 and the Device Dialog box shown below will open. 6. In the dialog box select the SPI Flash Programming Mode in the Device Access Option pull-down menu. This will open the SPI Serial Flash Dialog box. 11 Lattice Semiconductor LatticeECP3 Serial Protocol Board – Revision D User’s Guide Figure 11. Device Information Dialog Screen 7. The SPI Serial Flash Device dialog box will open. In this box select SPI Flash Erase, Program, Verify in the Operation pull-down menu. 8. Select SPI Serial Flash in the Device Family pull-down menu, STMicro under the Vendor pull-down menu, SPI-M2564 under the Device pull-down menu, and 16-lead SOIC under the Package submenu. Figure 12. Select Device Dialog Box 12 Lattice Semiconductor LatticeECP3 Serial Protocol Board – Revision D User’s Guide Figure 13. Sample SPI Serial Flash Device Dialog Box 9. Click OK in the SPI Flash Device Dialog box. Then click OK in Select Device dialog box. You will then return to the main configuration screen. If you do not desire to load the LCMXO1200C and the ispPOWR1220 device, these devices should be placed in Flash Bypass mode by double-clicking the Operation column and selecting the Bypass operation shown below. Figure 14. Flash Bypass for LCMXO1200C Device 10. From the main programming window, Select Go for the top toolbar. This will begin the SPI Serial Flash programming. 13 Lattice Semiconductor LatticeECP3 Serial Protocol Board – Revision D User’s Guide Figure 15. Programming Main Window Figure 16. SPI Serial Flash Programming Status Window Figure 17. Successful SPI Serial Flash Programming Session On-Board Parallel SPI Flash Memory (see Appendix A, Figure 25) • A 16-bit parallel Flash device is also available. This board uses a Lattice MachXO Crossover PLD to act as a programming bridge from the Flash device. • The CFG [2:0] needs to be [111] all up. • The ispVM System programming software can be used directly to program either the serial SPI Flash or the par14 LatticeECP3 Serial Protocol Board – Revision D User’s Guide Lattice Semiconductor allel Flash devices. Application note AN8077, Parallel Flash Programming and FPGA Configuration, addresses the use of the parallel Flash implementation. On-Board Clock Capabilities Dedicated SERDES Reference Clock Inputs (see Appendix A, Figure 26) • A 156.25 MHz, low-jitter (5x7.5mm surface mount) oscillator is included on-board. – Connected via clock mux to PCSB_REFCLK – Clock control CLOCK_CTRL_SEL0 is connected to both the FPGA (ball #A25) or the Crossover PLD (ball #N6). Either of these sources selects the clock source of Y1 oscillator or J29 and J33 SMA inputs. • A 125.00 MHz, low-jitter (5x7.5mm surface mount) oscillator is included on-board. – Connected via clock mux to PCSC_REFCLK – Clock control CLOCK_CTRL_SEL1 is connected to both the FPGA (ball #B25) or the Crossover PLD (ball #M14). Either of these sources selects the clock source of Y2 oscillator or J30 and J34 SMA inputs. ***SMA connections J29 and J33 can provide an external clock source to PCSB. J29 is the true and J33 is the compliment of the differential pair. The description markings on the evaluation board are incorrect. ***SMA connections J30 and J34 can provide an external clock source to PCSC. J30 is the true and J34 is the compliment of the differential pair. The description markings on the evaluation board are incorrect. User Defined General Purpose Clock Oscillator (see Appendix A, Figure 31) A 100 MHz oscillator is included on the board. It is fanned-out to several destinations on the board. They include the following. This oscillator is used for general clocking and should be avoided for jitter sensitive applications. Table 7. 100 MHz Clock Destinations Clock Destination Evaluation Board Designation Destination Pin Crossover PLD U17 A8 FPGA U1 B6 FPGA U1 H17-PCLKT0 FPGA U1 P30-RUM2_GPLLT_IN_A (see Appendix A, Figure 33) An auxiliary SMT oscillator area is included on the board. It includes a 5x7.5mm surface-mount pad for the addition of any user-defined oscillator. This oscillator interconnects to FPGA ball numbers AB28 and AB29 that are specifically general purpose PLL inputs to the FPGA fabric. (see Appendix A, Figure 33) SMA inputs J38 and J39 are provided to drive any externally generated differential clock onto the board. These 50ohm terminated SMAs interconnect to FPGA ball numbers U28 and V28 that are specifically PCLKT3_0 and PCLKC3_0 inputs to the FPGA fabric. SERDES Surface Mounted SMA Connections (see Appendix A, Figure 26) 15 LatticeECP3 Serial Protocol Board – Revision D User’s Guide Lattice Semiconductor DC coupled top-mounted SMA connectors connect to the one quad or four SERDES Tx and Rx channels. These pins are directly coupled to the designated SMA connector creating a path for both input and output differential data. Table 8. SERDES SMA Test Connectors Connector SERDES Signal FPGA Pin Connector SERDES Signal FPGA Pin J13 PCSB_HDINP0 AL17 J21 PCSB_HDOUTP0 AP17 J14 PCSB_HDINN0 AK17 J22 PCSB_HDOUTN0 AN17 J15 PCSB_HDINP1 AL16 J23 PCSB_HDOUTP1 AP16 J16 PCSB_HDINN1 AK16 J24 PCSB_HDOUTN1 AN16 J17 PCSB_HDINP2 AL15 J25 PCSB_HDOUTP2 AP15 J18 PCSB_HDINN2 AK15 J26 PCSB_HDOUTN2 AN15 J19 PCSB_HDINP3 AL14 J27 PCSB_HDOUTP3 AP14 J20 PCSB_HDINN3 AK14 J28 PCSB_HDOUTN3 AN14 Serial ATA Channels (see Appendix A, Figure 26) High-speed connections are included to attach SATA-type cables to SERDES channels for board-to-board or loopback purposes. The connectors are configured using the 7-pin SATA specifications. Figure 18. SATA Connector, Molex Part Number 67800-5050 Table 9. SERDES to SATA Connections Host CN1 Pin SERDES Pin Target FPGA Ball # CN2 Pin SERDES Pin FPGA Ball # 1 — GND 1 — GND 2 PCSC_HDOUTP1 AP24 2 PCSC_HDINP0 AL25 3 PCSC_HDOUTN1 AN24 3 PCSC_HDINN0 AK25 4 — GND 4 — GND 5 PCSC_HDINP1 AL24 5 PCSC_HDOUTP0 AP25 6 PCSC_HDINN1 AK24 6 PCSC_HDOUTN0 AN25 7 — GND 7 — GND SERDES PCI Express Channels (see Appendix A, Figure 26) This board is equipped to communicate directly as an add-on card to a PCI Express host. It is designed with edge fingers (CN3) to fit directly into a PCI Express host receptacle. Power can be supplied directly from the PCI Express host via the edge-finger connections. 16 LatticeECP3 Serial Protocol Board – Revision D User’s Guide Lattice Semiconductor Table 10. x4 PCI Express Connections FPGA Pin PCI Express PCI Express Edge PCSA_HDOUTP_3 AP18 PERp0 A16 PCSA_HDOUTN_3 AN18 PERn0 A17 PCSA_HDINP_3 AL18 PETp0 B14 PCSA_HDINN_3 AK18 PETn0 B15 PCSA_HDOUTP_2 AP19 PERp1 A21 PCSA_HDOUTN_2 AN19 PERn1 A22 PCSA_HDINP_2 AL19 PETp1 B19 PCSA_HDINN_2 AK19 PETn1 B20 PCSA_HDOUTP_1 AP20 PERp2 A25 PCSA_HDOUTN_1 AN20 PERn2 A26 PCSA_HDINP_1 AL20 PETp2 B23 PCSA_HDINN_1 AK20 PETn2 B24 PCSA_HDOUTP_0 AP21 PERp3 A29 PCSA_HDOUTN_0 AN21 PERn3 A30 PCSA_HDINP_0 AL21 PETp3 B27 PCSA_HDINN_0 AK21 PETn3 B28 PCSA_REFCLKP AH19 PCIe_CLKp A13 PCSA_REFCLKN AH20 PCIe_CLKn A14 PCIE_PERSETN D23 PERSTN A11 CML Pin Name Description Integrated end point block transmit pair Integrated end point block receive pair Integrated end point block transmit pair Integrated end point block receive pair Integrated end point block transmit pair Integrated end point block receive pair Integrated End point block transmit pair Integrated End point block receive pair Integrated End point block differential clock pair Fundamental PCI Express reset External SERDES Reference Clock Cleaner (see Appendix A, Figure 27) The Texas Instruments CDC7005 is a high-performance, low-phase noise, and low-skew clock synthesizer and jitter cleaner that synchronizes the voltage controlled crystal oscillator (VCXO) frequency to the reference clock. It is included on the evaluation board to demonstrate the use of an external clock cleaner as a means to reuse the SERDES recovered clock for retransmitting. The interconnection from the FPGA brings a single-ended LVCMOS clock from the SERDES to the CDC7005 input. The CDC7005 has an internal prescaler, phase frequency detector, charge pump, operational amplifier, and a LVPECL clock buffer. Along with an external VCXO and loop filter, the device completes a phase locked loop (PLL). Through the PLL operation, the VCXO input clock synchronizes with the reference clock input and ultimately with all clock outputs. All LVPECL clock outputs are completely synchronized in terms of phase and frequency with the reference clock input. Table 11. Reference Clock Interconnections CDC7005 Outputs 1156 fpBGA Inputs Notes Y0/Y0b P46/P47 PCSB_REFCLKP/N AH15/AH16 Y1/Y1b P3/P4 RLM1_GPLLT_INA/B Y28/Y27 Y2/Y2b P7/P8 RUM0_GDLLT_INA/B AJ34/AK34 CDC7005 Input REFIN Stuffing option R126/R127 must be fitted with 0-ohm resistors for connection to the FPGA reference clock input. 1156 fpBGA Output P37 D22 LVCMOS The jitter cleaning action depends on the PLL loop bandwidth. Up to the loop bandwidth, all noise (jitter) passes through and above the loop bandwidth, all signal noise is cleaned. The ideal loop bandwidth is chosen such that the reference clock source starts exceeding the VCXO noise floor. If the input has lot of jitter, then selecting a low 17 LatticeECP3 Serial Protocol Board – Revision D User’s Guide Lattice Semiconductor loop bandwidth, jitter can be cleaned. For the CDC7005, a low loop (sub 10 Hz) bandwidth can be selected easily. The CDC7005 itself adds a low noise to its outputs. For jitter cleaning operation, the noise performance of VCXO is critical. So, with a proper loop bandwidth and applicable VCXO, the CDC7005 acts as a jitter cleaner. The evaluation board is equipped with an Epson-Toyocom TCO2111-245.76MHZ VCXO that is packaged in a 13.9x9.8mm SMT form-factor. Table 12. CDC7005 Control and Status Signals CDC7005 Pin Board Feature Description 1 NPD SW5 Push-button that asserts LOW when depressed to power-down CDC7005. 14 NRESET SW6 Push-button that asserts LOW when depressed to RESET CDC7005. 22 STATUS_VCXO D13 Amber LED - CDC7005 PLL locked when lit. 23 STATUS REF D14 Amber LED - CDC7005 valid clock on REF_IN when lit. > 3.5 MHz. 25 STATUS LOCK D15 Amber LED - CDC7005 valid VCXO clock on VCXO_IN when lit. > 10 MHz The serial interface of the CDC7005 is a simple SPI-compatible interface for writing to the registers of the device. It consists of three control lines: CTRL_CLK, CTRL_DATA, and CTRL_LE. These pins from the CDC7005 are interconnected to the FPGA to allow for a controller to be built inside the FPGA. Table 13. CDC7005 Serial Interconnections CDC7005 1156 fpBGA Ball Number CTRL_CLK 35 E23 CTRL_DATA 33 C23 CTRL_LE 36 E22 The TI CDC7005 can also be controlled via an interface to header J47. This header can be used in conjunction with the TI programming software required for programming the internal control register of the CDC7005. TI. The software package provides real-time GUI control to the device. The software runs under Windows98, NT, and 2000. Info can be found at www.ti.com/lit/zip/scac037. Table 14. External Programming Interface for TI CDC7005 Clock Cleaner (See Appendix A, Figure 27) J47 Pin DB-25 Parallel Cable Description 1 2 Data 2 3 CLK 3 4 LE 4 18 Enable 5 19 GND FPGA Test Pins (see Appendix A, Figure 31) General Purpose DIP Switch (see Appendix A, Figure 31, SW14) General-purpose FPGA pins are available for user applications. FPGA pins are connected to a switch (SW15) that is a SPST-side actuated DIP switch. The switch is physically located on the secondary side of the board along the back-panel edge. The switches are connected to logic level 0 when depressed toward the board and a 1 when away from the board. The designated pins are connected according to the following table. 18 LatticeECP3 Serial Protocol Board – Revision D User’s Guide Lattice Semiconductor Table 15. FPGA Test Pins (See Appendix A, Figure 33) 1156 fpBGA Ball Number SW14 Switch Position Y34 1 Y33 2 Y30 3 AA29 4 Y32 5 Y31 6 Y26 7 Y25 8 General-Purpose LEDs (see Appendix A, Figure 31) The LEDs on the evaluation board are connected to general-purpose FPGA I/O. The purpose of these LEDs is to provide status for user designs. The LEDs must be included in the FPGA design. Table 16. LED Definitions (See Appendix A, Figure 33) Name 1156 fpBGA Ball Number PCB Designator LED Color LED1 W32 D21 Red LED2 W31 D24 Yellow LED3 V29 D25 Green LED4 W28 D27 Blue LED5 W30 D28 Blue LED6 W29 D26 Green LED7 W27 D23 Yellow LED8 W26 D22 Red General-Purpose Header (see Appendix A, Figure 31, J40) A 2x9 header (J10) provides a general-purpose connection to communicate with general purpose FPGA I/Os. Table 17. General Purpose Header Connections (See Appendix A, Figure 33) Header Pin 1156 fpBGA Ball Number Header Pin 1156 fpBGA Ball Number 1 GND 2 GND 3 A6 4 E11 5 A8 6 J13 7 A9 8 K13 9 A10 10 B11 11 B10 12 A11 13 J12 14 G12 15 K12 16 G11 17 C11 18 D11 19 LatticeECP3 Serial Protocol Board – Revision D User’s Guide Lattice Semiconductor 17-Segment LED Display (see Appendix A, Figure 33, D20) General-purpose FPGA pins are connected to a 17-segment display according to Table 18. These pins can be driven low to illuminate the display segments. Table 18. 17-Segment LED Display Segment 1156 fpBGA Ball Number A C30 B C29 C B31 D A31 E H25 F H26 G A30 H A29 K A27 M A26 N A28 P B28 R G25 S G26 T D25 U C25 DP D28 A H B K M N U G P T S F C R E D DP Logic Analyzer Probe (see Appendix A, Figure 31, LA1) An AMP/TYCO 767004 38-position .025 VERT SMD logic analyzer probe connection is provided for the user to utilize for test points. This connection provides 34 general I/O signals to be observed on Logic Analyzer probes using Mictor connections such as the Agilent 5346A. 20 LatticeECP3 Serial Protocol Board – Revision D User’s Guide Lattice Semiconductor Table 19. Logic Analyzer To FPGA Pin Reference (See Appendix A, Figure 33) Signal 1156 fpBGA Ball # Signal 1156 fpBGA Ball # LA1 G13 LA2 H14 LA3 A13 LA4 B13 LA5 D10 LA6 C10 LA7 C13 LA8 D13 LA9 J15 LA10 H15 LA11 D3 LA12 C2 LA13 C14 LA14 D14 LA15 A14 LA16 B14 LA17 G16 LA18 G17 LA19 D15 LA20 E15 LA21 J16 LA22 H16 LA23 A15 LA24 B15 LA25 E17 LA26 F28 LA27 C16 LA28 D16 LA29 K16 LA30 L16 LA31 A16 LA32 B16 LA33 G18 LA34 F19 10/100/1000Base Ethernet Interface (see Appendix A, Figure 28, U21) The Marvell 88E1111 Gigabit Ethernet transceiver device (U21) is included on the board. This physical layer device supports 1000BASE-T, 100BASE-TX, and 10BASE-T applications via a standard Media interface to an RJ-45 (Bel Stewart “MAGJACK” p/n L829-1J1T-43) connection. The RJ-45 connection includes network magnetics providing the proper signal conditioning, electro-magnetic interference suppression and signal isolation. This connector includes two LEDs and the board includes four status LEDs from the Marvell device. The LEDs are register-programmed and detailed descriptions are included in the Marvell data sheet. Table 20. PHY Status Indicators LED Status Description RJ45- Yellow LED RX RJ45- Orange LED TX PCB Amber (D16) LINK 10 PCB Amber (D17) LINK 100 PCB Green (D18) LINK 100 PCB Amber (D19) DUPLEX The Marvell 88E1111 device communicates via a MAC interface to the LatticeECP3 device via GMII, SGMII, and a standard 10-bit interface. The evaluation board includes the means to setup the required hardware configuration for the PHY to operate in all the supported modes. Hardware configuration options such as PHY address, PHY operating mode, auto-negotiation, and physical connection type must be set up using the configuration switches SW7 to SW13 on the back side of the board. These switches tie the CONFIG[6:0] pins to the control LED output pins. The encoded values of the LED outputs that are tied to the CONFIG[6:0] pins are latched at the de-assertion of the PHY RESETn control. The switch matrix of the PHY CONFIG pins are described below. DIP switches control the hardware settings. Note: Only one switch position per DIP pack should be on for any configuration. 21 LatticeECP3 Serial Protocol Board – Revision D User’s Guide Lattice Semiconductor Table 21. PHY Hardware Configuration Switch Control (see Appendix A, Figure 29) Switch Position 88E1111 LED Output Bit[2:0] 1 VDDO 111 DIP 88E1111 Pin 2 LED_10 110 SW7 CONFIG0 PHYADDR[2] PHYADDR[1] PHYADDR[0] 3 LED_100 101 SW8 CONFIG1 ENE_PAUSE PHYADDR[4] PHYADDR[3] 4 LED_1000 100 SW9 CONFIG2 ANEG[3] ANEG[2] ANEG[1] 5 LED_DUPLEX 011 SW10 CONFIG3 ANEG[0] ENA_XC DIS_125 6 LED_RX 010 SW11 CONFIG4 MODE[2] MODE[1] MODE[0] 7 LED_TX 001 SW12 CONFIG5 DIS_FC DIS_SLEEP MODE[3] 8 VSS 000 SW13 CONFIG6 SEL_BDT INT_POL 75/50 Ohm 88E1111 Hardware Register Map Bit[2] Bit[1] Note: DIP switches SW[7:13] utilize same position mapping. Table 22. Board DIP Switch Designations for Marvell Transceiver Configuration Pins Switch PHY Configuration Pin SW7 CONFIG0 SW8 CONFIG1 SW9 CONFIG2 SW10 CONFIG3 SW11 CONFIG4 SW12 CONFIG5 SW13 CONFIG6 Figure 19. DIP Switch Positions for CONFIG Pins On Off 1 VCC0 2 LED LINK10 3 LED LINK100 4 LED LINK100 5 LED DUPLEX 6 LED RX 7 LED TX 8 VSS 22 Bit[0] LatticeECP3 Serial Protocol Board – Revision D User’s Guide Lattice Semiconductor Table 23. Marvel Transceiver Configuration Defaults DIP Switch PHY Config Pin Position ON Encoded Output Pin Encoded Value SW7 CONFIG0 7 LED TX 001 PHY ADDR[2:0] = 001 SW8 CONFIG1 4 LED LINK1000 100 ENABLE PAUSE, PHY ADDR[4:3] = 00 Description SW9 CONFIG2 1 VCCO 111 Auto Neg., Advertise All, Prefer Slave SW10 CONFIG3 1 VCCO 111 Enable MDI Crossover, Disable 125 CLK SW11 CONFIG4 8 VSS 000 1000 Base-X without clock 1000 Base-X Auto Neg. to copper (GBIC) SW12 CONFIG5 2 LED LINK10 110 Disable fiber/copper, Auto-detect, Enable Sleep SW13 CONFIG6 8 VSS 000 Select MDC/MDIO, INTn Active High, 50-ohm termination Table 24. FPGA/MAC to 88E1111 PHY Interconnections (see Appendix A, Figure 33) MAC Netname 88E1111 Pin 1156 fpBGA Ball Number GTXCLK E2 A18 TX_CLK D1 J17/PCLKT0_0 TX_ER F2 K20 TX_EN E1 B19 TXD7 J2 A19 TXD6 J1 H19 G19 TXD5 H3 TXD4 H1 F18 TXD3 H2 D18 TXD2 G3 H18 TXD1 G2 J18 TXD0 F1 B18 RX_CLK C1 E19/PCLKT1_0 RX_ER D2 L19 RX_DV B1 C19 RXD7 C5 C20 RXD6 A2 G21 RXD5 A1 G20 RXD4 C4 B20 RXD3 B3 A20 RXD2 C3 K19 RXD1 D3 J19 RXD0 B2 D19 CRS B5 A17 COL B6 B17 S_IN+ A3 AP23 S_IN- A4 AN23 S_CLK+ A5 nc S_CLK- A6 nc S_OUT+ A7 AL23 S_OUT- A8 AK23 23 LatticeECP3 Serial Protocol Board – Revision D User’s Guide Lattice Semiconductor Table 25. 88E1111 Control and Status Interconnections to FPGA (see Appendix A, Figure 33) PHY Control/Status 88E1111 Pin 1156 fpBGA Ball Number MDIO M1 D20 MDC L3 F21 RESETn K3 F22 INTn L1 A21 FREQ_SEL H8 B21 CLK25 H9 D21 Crossover PLD Device (see Appendix A, Figure 25, U17) The board includes a Lattice LCMXO-1200C Crossover PLD which is used in conjunction with the parallel Flash device for loading the configuration memory of the FPGA. It is also used for general-purpose board management functions. It has several connections to the FPGA and other devices on the board and includes an active high, push-button (SW4) if needed for user designs. Generic user-defined interconnections are defined in Table 26. Table 26. MachXO to FPGA Interconnections MachXO csBGA Ball Number FPGA fpBGA Ball Number M1 C3 P13 C4 P10 B1 N7 B2 N8 E4 P11 D4 N13 B3 N1 A2 N3 D5 N4 C6 P1 B4 M12 A3 M2 D6 M3 C5 M4 A4 M6 A5 24 LatticeECP3 Serial Protocol Board – Revision D User’s Guide Lattice Semiconductor Ordering Information Description Ordering Part Number LatticeECP3 Serial Protocol Board China RoHS Environment-Friendly Use Period (EFUP) LFE3-95EA-SP-EVN Known Issues SATA Target interface(CN2) channel – Transmit data must be polarity-inverted in FPGA design for correct connection. SATA Host interface(CN1) channel – Receive data must be polarity-inverted in FPGA design for correct connection. Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: [email protected] Internet: www.latticesemi.com Revision History Date Version Change Summary August 2009 01.0 Initial release. September 2009 01.1 Updated Programming the Daisy Chain text section. May 2010 01.2 Added Known Issues section. July 2010 01.3 Updated Ordering Part Number in the Ordering Information table. © 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 25 A B C D 5 User GSRn FPGA PROGRAMn Logic Analyzer Interface to FPGA IO 4 Config Status LEDs 3 (Sheet 4) FPGA Power Pins Power (Sheet 2) Test Pins Logic Analyzer 2 SMAs Bank 6 Bank 7 SERDES (Sheet 7) DQ Test Loops 2 Programming Power Input Date: Size C Title 1 Wednesday, August 26, 2009 Sheet ECP3-SPB Eval Board Project Cover Page (Sheet 5) (Sheet 12, 13) 1 of 15 Rev D 1605 Valley Center Parkway Bethlehem, PA 18017 User IO Header 16 GPIO (Sheet 12) (Sheet 8, 14) 1 8- User IO==> SWITCHES 8- User IO==> LEDS LEDs Switches GPIO- SMAs SGMII SATA Tgt & Host Test SMA X4 PCIe Bank 8 Bank 3 Bank 2 Bank 1 ECP3 FPGA Bank 0 TI CDC (Sheet 9, 12) USB RS232 Ethernet 16-Seg PHY (Sheet 15) Board Layout 3 (Sheet 12, 13) (Sheet 3) Power Mgt. PCIe X4 4-Duplex SERDES Channels 4- Duplex SERDES Channels- Quad PCSB 4 PCSB 5 PCSA 26 PCSC A B C D Lattice Semiconductor LatticeECP3 Serial Protocol Board – Revision D User’s Guide Appendix A. Schematic Figure 20. Cover Page A B C D TestPoint TestPoint TestPoint TestPoint TestPoint TestPoint 1 1 1 1 3 3 8 8 TP11 1 TP9 TP7 TP6 TP3 1_8V_EN 5 ILIM IN CNTL GND OUT SENSE EN SC1592 TAB U5 1_5V_EN 1 2 3 4 5 6 7 1 2 3 4 5 6 7 TestPoint TestPoint TestPoint TestPoint TestPoint TestPoint ILIM IN CNTL GND OUT SENSE EN SC1592 TAB U3 TP12 1 TP10 1 TP8 1 1 TP5 TP4 1 TP2 1 3 R18 12_0V + C421 + 1 1 5016 LP7 1_2V_A 1_8V 1_5V 1 1 5016 1.5V 1 5016 LP6 1 C8 10UF-16V-TANTBSMT R271 OPEN-0603SMT C10 10UF-16V-TANTBSMT 806R-0603SMT R15 3_3VIN 1.8V R270 OPEN-0603SMT 1_8_TRIM 1 5016 LP3 1 LP1 1_13K-0603SMT R6 3_3VIN 1_5_TRIM R358 OPEN-0603SMT 10UF-16V-TANTBSMT R21 OPEN-0603SMT 1 5016 1K-0603SMT C420 1_8V 1_8_TRIM_i R13 100R-0805SMT GND 3 1 R357 OPEN-0603SMT 10UF-16V-TANTBSMT R9 OPEN-0603SMT R5 1 5016 LP5 1 1K-0603SMT 12_0V 1_5V 1_5_TRIM_i R2 100R-0805SMT GND 1 5016 LP4 1 LP2 + 1_8V + 1_5V 4 330UF-FKSMT C15 + F5 F1228CT-ND 5A Fast-Blo SMT Socketed Fuse 330UF-FKSMT C9 + F2 F1228CT-ND 5A Fast-Blo SMT Socketed Fuse VCC_CORE 3_3V 2_5V 1 2 U4 3 3_3VIN J1 GND VIN 2 1 1 2 3 4 5 6 7 2 TB1 1 12_0VIN VOUT SENSE R3 12_0V C422 3 + 3 3 1.2V Analog R269 OPEN-0603SMT C11 10UF-16V-TANTBSMT 2K-0603SMT R19 + 3_3VIN 3_3VIN VCCA_TRIM R359 OPEN-0603SMT 10UF-16V-TANTBSMT R22 OPEN-0603SMT 1K-0603SMT R16 VCCA_TRIM_i 1_2V_A R14 100R-0805SMT GND R11 2K-0603SMT 3_3_TRIM C7 10UF-16V-TANTBSMT 0R-0603SMT F1228CT-ND R268 OPEN-0603SMT 5 6 F4 5A Fast-Blo SMT Socketed Fuse 3.3V + 1_2V_A 8 7 6 5 + 3_3V 3_3V_GATE 1 2 3 4 3_3V_MON + C12 330UF-FKSMT 3 C3 + 3 3 ILIM IN CNTL GND OUT SENSE EN 2 + 1 2 U2 12_0V 1 2 3 4 5 6 7 GND VIN 100UF-FKSMT 5 6 + R20 2.5V Date: Size C Title 3 3 F7 F1228CT-ND 5A Fast-Blo SMT Socketed Fuse + 1 Wednesday, August 26, 2009 Sheet 2 of 15 Rev 3.0 1605 Valley Center Parkway Bethlehem, PA 18017 + C14 330UF-FKSMT ECP3-SPB Eval Board Project Power Generation R272 OPEN-0603SMT + 2_5V VCC_CTRL VCC_TRIM C6 330UF-FKSMT 3 VCC_CORE_MON R356 1K-0603SMT VCC_CORE R314 10K-0603SMT 3_3VIN R267 OPEN-0603SMT C13 10UF-16V-TANTBSMT 464RR-0603SMT 2_5_TRIM R360 OPEN-0603SMT 1K-0603SMT R17 12_0V + R312 OPEN-0603SMT VCC_TRIM_i 3_3VIN R10 12_1K-0603SMT 1 F1228CT-ND 5A Fast-Blo SMT Socketed Fuse R4 F3 1.2V Core R354 1K-0603SMT 12VIN GOOD 0R-0603SMT C5 10UF-16V-TANTBSMT SENSE R265 0R-0603SMT PTH12060L VOUT D35 SCHOTTKY/VISHAY-V12P10 2_5V 3 D1 R1 12_0V 470R-1206SMT LED-SMT1206_GREEN C423 10UF-16V-TANTBSMT R23 10K-0603SMT 2_5_TRIM_i R12 100R-0805SMT GND R311 OPEN-0805SMT R7 OPEN-0805SMT VCC_CORE SC1592 TAB U7 2_5V_EN 8 CORE_EN 330UF-FKSMT C4 10UF-16V-TANTBSMT F6 F1228CT-ND 5A Fast-Blo SMT Socketed Fuse 3 S1 S2 S3 G NTMS4503 SO8 DI D4 D3 D2 D1 Q1 J2 HEADER 2 HD2x1 DI 2 D33 SCHOTTKY/VISHAY-V12P10 + C1 C2 470UF-FKSMT R355 1K-0603SMT POWER INPUT F1251CT-ND 10A Fast-Blo SMT Socketed Fuse F1 1K-0603SMT D34 SCHOTTKY/VISHAY-V12P10 R353 Terminal Block/ED1202DS GND +12VDC MARK TERMINAL BLOCK +12VDC at PIN1 R266 0R-0603SMT PTH12060W ILIM IN CNTL GND OUT SENSE EN SC1592 TAB 1_2VA_EN 8 U6 R310 OPEN-0805SMT R8 OPEN-0805SMT 12_0V Male Power Jack 2.1mm 22HP037-2.1mm 3 2 1 1 3 3_3V_GATE GND Pads Distributed around the board 4 10 MUP 8 TRACK 9 3_3_TRIM_i INHIBIT# 3 MDWN ADJUST 4 GND 7 MUP 8 TRACK 9 MDWN ADJUST 4 10 INHIBIT# 3 G TP1 3_3VIN 3_3VIN 27 3_3VIN GND 7 5 3_3VIN A B C D Lattice Semiconductor LatticeECP3 Serial Protocol Board – Revision D User’s Guide Figure 21. Power Generation A B C 0R-0603SMT 47 46 R315 OPEN-0603SMT 5 TRIM1 R317 TRIM2 OPEN-0603SMT R320 OPEN-0603SMT R322 OPEN-0603SMT R324 OPEN-0603SMT R318 OPEN-0603SMT TRIM4 R316 OPEN-0603SMT TRIM3 R321 OPEN-0603SMT R319 OPEN-0603SMT VMON1+ VMON1GS VMON2+ VMON2GS VMON3+ VMON3GS VMON4+ VMON4GS VMON5+ VMON5GS VMON6+ VMON6GS VMON7+ VMON7GS VMON8+ VMON8GS VMON9+ VMON9GS VMON10+ VMON10GS VMON11+ VMON11GS VMON12+ VMON12GS 2_5V GSRN INITN DONE TP32 5,6 5,6 R27 10K-0402SMT 3_3VIN 10NF-0603SMT C22 100NF-0603SMT C16 100NF-0603SMT C21 10NF-0603SMT C20 R325 OPEN-0603SMT 50 48 3_3V_MON 2 VCC_CORE_MON TRIM6 52 51 1_2V_A TRIM5 54 53 R323 OPEN-0603SMT 56 55 1_5V 62 61 64 63 66 65 68 67 70 69 72 71 1_8V R326 OPEN-0603SMT R47 1K-0603SMT R43 2K-0603SMT 8 7 6 5,6,14 100NF-0603SMT C19 58 57 12_0V R40 1K-0603SMT C18 VCC WP SCL 24AA1025-ISM GND A2 A1 EEPROM 4 3 2 2_5V 2 R24 D29 22UF-16V-TANTBSMT R37 2K-0603SMT + C17 12_0VIN 0R-0603SMT MMBZ5221BLT1/SOT23 D30 MMBZ5221BLT1/SOT23 R25 3_3VIN 2_5V 1UF-16V-0805SMT 5 3_3VIN SDA TP15 TP16 A0 PAC_MCLK U8 PAC_RESETn 1 39 VCCPROG VPS0 VPS1 TEMP TEMP_GND 5 5 R28 10K-0402SMT 4 U10 POWR1220AT8 TQFP100 DI Lattice ispPAC 4 PLDCLK TRIM8 TRIM7 TRIM6 TRIM5 TRIM4 TRIM3 TRIM2 TRIM1 HVOUT4 HVOUT3 HVOUT2 HVOUT1 TRIM8 TRIM7 TRIM6 TRIM5 TRIM4 TRIM3 TRIM2 TRIM1 SDA SCLK OVERT ALERT 2 100R-0603SMT VCC_CTRL R34 TP25 R44 10K-0402SMT 0402 DI PLDCLK HVOUT1 73 74 75 79 80 82 83 84 95 Q2 3 3_3V 2 3 TP17 TP18 TP19 TP20 TP21 TP22 TP23 TP24 3_3V_GATE R33 10K-0402SMT 1 Q3 Q4 Q6 2 2 2 1_5_TRIM 2_5_TRIM 1_8_TRIM 2 2 VCCA 2 VCCA_TRIM 1_2VA_EN 2N2222/SOT23 3_3_TRIM 2 1 3_3VIN R32 10K-0402SMT 2N2222/SOT23 1_8V_EN 2 ispPAC 1_5V_EN 14 I2C_SCL VCC_TRIM 2 1 3_3VIN R31 10K-0402SMT 1 R30 10K-0402SMT 14 I2C_SDA 2N2222/SOT23 TP14 4 3_3VIN TP13 6 7 R301 4_7K-0402SMT Q5 2 CORE_EN 2N2222/SOT23 PCIe Edge 12V Wall Adapter 12V Input Terminal 12V INPUT 8 3_3VIN R300 4_7K-0402SMT 2_5V_EN 5 6 5 5,6 5,6 5 2N2222/SOT23 TDO_PAC TDI_PAC TDI_BUF TMS_BUF TCK_BUF TRSTn PWR_GOOD_VCCA PWR_GOOD_VCC PWR_GOOD_3_3V PWR_GOOD_2_5V PWR_GOOD_1_5V PWR_GOOD_1_8V TP33 TP34 TP35 1 R29 10K-0402SMT 3_3VIN DXN DXP VCC U9 MAX6692 3 2 V_6692 1 2200PF-0402SMT C23 40 42 85 86 25 24 23 21 20 19 18 17 16 15 14 12 11 10 9 8 TDO_PAC TDI_PAC TDI_BUF TMS_BUF TCK_BUF OUT20 OUT19 OUT18 OUT17 OUT16 OUT15 OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 OUT8 OUT7 OUT6 SMBA/OUT5 3_3VIN R26 200R-0402SMT C24 100NF-0402SMT 3_3V GND 5 D TP36 TP37 TP38 5 97 1 2 4 6 7 VCCINP IN1 IN2 IN3 IN4 IN5 IN6 96 MCLK 93 92 SDA SCL 89 90 VPS0 VPS1 VCCD VCCD VCCD 13 38 94 VCCA 33 34 31 30 28 37 32 VCCJ TDO TDI ATDI TMS TCK TDISEL GNDA GNDA 3 2 3 2 3 2 91 RESETb GNDD GNDD GNDD GNDD GNDD GNDD 3 5 D3 LED-SMT1206_GREEN D4 LED-SMT1206_GREEN 2 PWR_GOOD_1_8V 1.8V PWR_GOOD_1_5V 1.5V D5 PWR_GOOD_2_5V LED-SMT1206_GREEN 2.5V PWR_GOOD_3_3V 3.3V PWR_GOOD_VCC VCC CORE 2 MOSFET LDO D6 LED-SMT1206_GREEN D7 LED-SMT1206_GREEN 10K-0402SMT Date: Size C PWR_GOOD_1_8V PWR_GOOD_1_5V PWR_GOOD_2_5V PWR_GOOD_3_3V 1 Wednesday, August 26, 2009 Sheet ECP3 SPB Eval Board Project PWR_GOOD_VCCA PWR_GOOD_VCC Power Management 10K-0402SMT Title R51 330R-0402SMT 10K-0402SMT R50 R49 330R-0402SMT 10K-0402SMT R48 R46 10K-0402SMT 330R-0402SMT R42 330R-0402SMT R45 R41 10K-0402SMT 330R-0402SMT R36 R39 R38 330R-0402SMT 3_3VIN R35 3 of 17 Rev 3.0 1605 Valley Center Parkway Bethlehem, PA 18017 2_5V, +2.5V, 1.5A 3_3V, +3.3V, 2A D A B C ETH_1_2V, +1.2V, 0.5A 1_2VA, +1.2V, 1.5A LDO LDO 1_8V, +1.8V, 2A 1_5V, +1.5V, 2A 1 LDO LDO D2 LED-SMT1206_GREEN PWR_GOOD_VCCA POL 3.3VIN, +2.5V, 6A POL VCC Core, +1.2v , 10A 2 G 3 22 36 43 88 98 G 60 G 87 45 G 3 G 2 G 28 2 Lattice Semiconductor LatticeECP3 Serial Protocol Board – Revision D User’s Guide Figure 22. Power Management A B C Power 5 ECP3-90-1156BGA U1I VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC N13 AB16 N21 N18 AB21 V22 N19 N14 AB15 AB20 N15 U22 AB19 P13 U13 R13 AB14 Y13 N16 AB18 V13 R22 N20 P22 N22 AB13 AB22 AB17 Y22 AA13 AA22 N17 FB7 BLM41PG600SN1 FB10 C71 100NF-0603SMT C49 C33 C72 C34 + C43 C74 C75 10NF-0603SMT C52 C44 PCSA_VCCOB 100NF-0603SMT C51 C73 10NF-0603SMT C50 BLM41PG600SN1(NOB) PCSA_VCCOB C70 C32 PCSA_VCCIB C26 100NF-0603SMT 100NF-0603SMT 10NF-0603SMT 10NF-0603SMT C31 + C25 PCSA_VCCIB C76 FB5 C36 PCSB_VCCIB FB8 C77 PCSB_VCCOB BLM41PG600SN1 FB11 C78 100NF-0603SMT 10NF-0603SMT C54 BLM41PG600SN1(NOB) C53 C90 C91 C92 C93 C94 C95 C96 C97 C98 4 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT C89 VCC_CORE C37 + C27 C38 C28 PCSB_VCCIB 3 ECP3-90-1156BGA C40 PCSC_VCCIB C41 C42 + C29 C30 PCSC_VCCIB AD16 AD18 AE19 AC17 AC18 AD13 AE16 AD17 AC22 AE23 AE12 AD22 AE22 AC13 AE13 AD19 Y23 AA23 P12 AC20 AC14 M20 AA12 Y12 R12 AC15 AC21 M21 R23 M15 M14 P23 T13 W13 T22 W22 + C79 3_3V + C61 C80 C62 10NF-0603SMT C58 1_2V_A 100NF-0603SMT C57 PCSC_VCCOB BLM41PG600SN1 FB12 BLM41PG600SN1(NOB) FB9 PP1 PP2 VCCPLL C64 C65 C66 C85 10NF-0603SMT C100 2 C101 + FB13 BLM41PG600SN1 3_3V PP11 + C341 3_3V C342 100NF-0603SMT 10NF-0603SMT 100NF-0603SMT 100NF-0603SMT C84 100NF-0603SMT C82 C83 10NF-0603SMT 100NF-0603SMT 2 C81 100NF-0603SMT C63 10NF-0603SMT C60 C48 PCSC_VCCOB 100NF-0603SMT C59 + C47 100NF-0603SMT 100NF-0603SMT 10NF-0603SMT 10NF-0603SMT C39 BLM41PG600SN1 1_2V_A 1_5V FB3 FB6 BLM41PG600SN1(NOB) 1_2V_A 1_5V VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCPLL_L VCCPLL_L VCCPLL_R VCCPLL_R Misc Power U1J 10NF-0603SMT C56 C46 PCSB_VCCOB 100NF-0603SMT C55 + C45 100NF-0603SMT 100NF-0603SMT 10NF-0603SMT 10NF-0603SMT C35 BLM41PG600SN1 1_2V_A 1_5V FB2 BLM41PG600SN1(NOB) 1_2V_A 1_5V 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT C69 VCC_CORE PP3 VCC_CORE FB4 BLM41PG600SN1 1_2V_A 1_5V FB1 22UF-16V-TANTBSMT 22UF-16V-TANTBSMT 22UF-16V-TANTBSMT 22UF-16V-TANTBSMT BLM41PG600SN1(NOB) 1UF-16V-0805SMT 1UF-16V-0805SMT 1UF-16V-0805SMT 1UF-16V-0805SMT 22UF-16V-TANTBSMT 22UF-16V-TANTBSMT 1_5V 22UF-16V-TANTBSMT 22UF-16V-TANTBSMT 1 2 1 2 1_2V_A 1UF-16V-0805SMT 1UF-16V-0805SMT 1UF-16V-0805SMT 3 100NF-0603SMT 1UF-16V-0805SMT C99 1UF-16V-0805SMT 4 22UF-16V-TANTBSMT D 1 2 1 2 5 22UF-16V-TANTBSMT 29 C67 Date: Size C Title 10NF-0603SMT 1 Wednesday, February 18, 2009 Sheet 4 of 15 Rev 3.0 1605 Valley Center Parkway Bethlehem, PA 18017 ECP3-SPB Eval Board Project 1 10NF-0603SMT C88 Power Supplies 10NF-0603SMT C68 10NF-0603SMT C87 100NF-0603SMT C86 1UF-16V-0805SMT A B C D Lattice Semiconductor LatticeECP3 Serial Protocol Board – Revision D User’s Guide Figure 23. Power Supplies A B C Q7 2N2222/SOT23 D11 220R-0603SMT G 3 6 6 C102 2 D INITN R59 10K-0603SMT DONE 3,6,14 C103 3_3V LOADER_CK SPI_CLK PROGRAMN GSRN 5 6 3 SW PUSHBUTTON-SPST SW3 PROGRAMN SW PUSHBUTTON-SPST SW1 FPGA GSRN FPGA_CSSPI0N_DI SPI0_Q FLASH_DIS LOADER_CK SPI_CLK 3_3V D10 2Y 1Y 1 2 3 4 5 6 7 8 U11 5 4 2 1 3 1 SN74LVC125A/SO14 2A 2OE_N 1A 1OE_N U14A 3_3V M25P64-FLASH HOLD# CK VCC D DU1 DU8 DU2 DU7 DU3 DU6 DU4 DU5 S# VSS Q W# OUT2 OUT1 MAX6817 IN2 IN1 U12 16 15 14 13 12 11 10 9 4 6 SPI_CLK FPGA_SISPI FPGA_CCLK FPGA_MCLK SPI FLASH 1 2 11 8 3_3V FPGA_CCLK LED-SMT1206_RED 680R-0603SMT R54 R60 R61 R62 10K-0603SMT 10K-0603SMT 10K-0603SMT J7 HEADER 2X2 3 4 GSRN CONFIG Status LEDs 1 D9 LED-SMT1206_RED DONE indicator will light when configuration is successfully completed PROGRAMN & GSRN Pushbuttons 100NF-0603SMT R56 LED-SMT1206_GREEN 10NF-0603SMT LED-SMT1206_RED R66 10K-0603SMT Y R72 R55 D8 680R-0603SMT R C105 R65 10K-0603SMT Y PROGRAMN 680R-0603SMT R53 100NF-0603SMT INITN indicator will light if an error occurs during configuration programming 4_7K-0603SMT 5 VCC GSRN 3_3V 4Y 3Y 6 3_3V R64 10K-0603SMT 3_3V R77 GND 2 R78 100R-0603SMT R70 OPEN-0603SMT R63 10K-0603SMT R71 OPEN-0603SMT 3_3V 100R-0603SMT 4 Configuration CFG2 CFG1 CFG0 R75 10K-0603SMT R76 10K-0603SMT 0(ON) 1(OFF) 1(OFF) X 1(OFF) 0(ON) 0(ON) CFG1 1(OFF) X ON R73 10K-0603SMT ECP3-90-1156BGA TDI TCK TMS TDO VCCJ VCCIO8 VCCIO8 X 1(OFF) 1(OFF) 0(ON) 0(ON) CFG0 SPI0_Q 10K-0603SMT 3_3V TDI_ECP3 TCK_BUF TMS_BUF TDO_ECP3 3_3V DONE FPGA_CCLK INITN PROGRAMN CFG0 CFG1 CFG2 FPGA_D15 FPGA_D14 FPGA_D13 FPGA_D12 FPGA_D11 FPGA_D10 FPGA_D9 FPGA_D8 FPGA_XRES ispJTAG 3 Slave Parallel Slave Serial SPIm SPI Flash Configuration Mode 3 FPGA_SISPI FPGA_D7 FPGA_D6 FPGA_D5 FPGA_D4 FPGA_D3 FPGA_D2 FPGA_D1 FPGA_D0 FPGA_MCLK FPGA_WRITEN FPGA_CSSPI1N_DOUT FPGA_CSSPI0N_DI FPGA_CSN FPGA_CS1N 3,6 3 3 6 1 3 5 4 6 OUT Y2 OUT Y1 TCK_BUF TCK_BUF TMS_BUF 4 6 OUT Y2 OUT Y1 NC7WZ16-MACO6A/Fairchild TinyLogic R74 220R-0603SMT D12 LED-SMT1206_GREEN This LED indicates activity on TDI. TDI_BUF U13 3 IN A2 2 U15 IN A1 3 1 TDO_PAC TDI_XO TDO TDI TMS TCK IN A2 3_3VIN 2 3 1 TRSTn 3 6 J4 TDO ECP3 TDI 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 PROGRAMN HEADER 2X2 1 2 4.7K 3_3VIN LOCAL_TMS LOCAL_TCK DONE INITN LOCAL_TDI PROGRAMN INITN 4.7K 4.7K TDO 4.7K Date: Size C Title TDO TDO TDI FPGA_D[0..7] Board Jumpers VCC TCK TMS NC ispEN_N TDI TDO 7 1 VCC INITN DONE TCK TMS NC GND ispEN_N TDI TDO 7 1 3_3VIN 3_3VIN Programming 6 1 Wednesday, August 26, 2009 Sheet ECP3 SPB Eval Board 5 of 15 Rev 3.0 1605 Valley Center Parkway Bethlehem, PA 18017 FROM ISPVM CABLE TMS GND TCK DONE INITn +3.3V TDO TDI PROGRAMn HEADER 10 2 3 4 5 6 8 9 10 J12 INITn Chain Open: INITn Local Shunt: Local & Offboard HEADER 10 INITN GND DONE J9 TMS GND TCK DONE INITn_OB NC TDO_OB TDI_OB PROGRAMn_OB 2 3 PROGRAMN_CHN 4 TRSTn 5 TMS_BUF 6 TCK_BUF 8 DONE 9 INIT_CHN 10 Project 1 Multi-board JTAG header PWR J11 HEADER 2 DI HD2X1 J10 HEADER 2 DI HD2X1 EXBV8V472JV PROGRAMn Chain Open: PGM Local Shunt: Local & Offboard CABLE_TDO J8 3 4 ATDI XO TDI TDI FPGA_WRITEN CFG0 CFG1 CFG2 sysCONFIG Connector FPGA_D6 3_3V INITN PROGRAMN JTAG Daisy Chain HEADER 17X2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 TDO Chaining 1-2: TDO Local 1-3, 2-4: Offboard Chain TMS TCK FPGA_CCLK FPGA_SISPI FPGA_CSSPI0N_DI FPGA_CSSPI1N_DOUT DONE FPGA_D7 FPGA_D6 FPGA_D5 FPGA_D4 FPGA_D3 FPGA_D2 FPGA_D1 FPGA_D0 FPGA_CSN FPGA_CS1N 3_3V IN A1 3_3VIN TDI_ECP3 TDO_PAC TDI_XO NC7WZ16-MACO6A/Fairchild TinyLogic JTAG TMS_BUF TDI_BUF J41 HEADER 3X2 2 4 6 PLACE JUMPERS FOR LOCAL ECP3 JTAG CHAIN 6 FPGA_D[8..15] 3,6 6 INITN PROGRAMN FPGA_D[0..7] CFG[0..2] 3,6 6 DONE TDI_BUF CABLE_TDO TDO_ECP3 TEMP TEMP_GND 6 6 FPGA_WRITEN FPGA_CSN FPGA_CS1N 3,6 FPGA_D7 FPGA_D0 SW2 SW DIP-3 CTS 194-3MST E1 D1 D2 C1 K10 N25 P25 F33 F32 J34 H34 G32 G33 H33 G34 E32 F34 E31 E34 D34 F31 G30 D33 G31 C34 C33 B34 B33 F30 D32 C31 D31 C32 B32 D29 D30 A33 A32 W23 AN4 AP4 FPGA_CSN R58 10K-0603SMT CONFIG CFG Switches 0(ON) CFG2 3_3V U1G 1 2 3 HEADER 3 J6 PR16B/BUSY/SISPI/AVDN PR16A/D7/SPID0 PR14B/D6/SPID1 PR14A/D5 PR13B/D4/SO PR13A/D3/SI PR11B/D2 PR11A/D1 PR10B/D0/SPIFASTN PR8B/MCLK PR10A/WRITEN PR8A/DOUT/CSON/CSSPI1N PR5B/DI/CSSPI0N/CEN PR7B/CSN/SN/CONT1N/OEN PR7A/CS1N/HOLDN/CONT2N/RDY PR5A/HFP DONE CCLK INITN PROGRAMN CFG0 CFG1 CFG2 PT145B/XD15 PT145A/XD14 PT143B/XD13 PT143A/XD12 PT142B/XD11 PT142A/XD10 PT140B/XD9 PT140A/XD8 XRES TEMPSENSE TEMPVSS 13 10K-0603SMT R68 4_7K-0603SMT FPGA_CS1N R57 10K-0603SMT 12 9 10 SN74LVC125A/SO14 4A 4OE_N 3A 3OE_N U14B FPGA_XRES FPGA_CCLK R67 1 2 3 HEADER 3 J5 3_3V HEADER 2 6 5 4 1 2 3 3 R VM Cable 5 VCC GND 2 SPIFASTN R52 C108 Buffer C106 100NF-0603SMT 1 2 100NF-0603SMT 1 2 J3 RN1B 4 RN1C Daisy Chain Off-Board 5 RN1D 4_7K-0603SMT R69 GND 7 14 VCC 4LOCAL_TCK 5 5 VCC GND 2 1 RN1A 8 CABLE_TDO 2 7 LOCAL_TDI 3 6 LOCAL_TMS 1 2 30 C104 INITN 100NF-0603SMT DONE C107 PROGRAMN FPGA_D[8..15] 100NF-0603SMT A B C D Lattice Semiconductor LatticeECP3 Serial Protocol Board – Revision D User’s Guide Figure 24. Programming A B C 3_3V R80 0R-0603SMT R79 OPEN-0603SMT 5 SW4 CPLD RESET 3_3V 5 5 5 3,5 TCK_BUF 5 TDI_XO 3 TDI_PAC 3,5 TMS_BUF R84 1K-0603SMT GSRN DONE 3,5,14 3,5 LOADER_CK PROGRAMN INITN 5 5 CFG[0..2] 7,14 CLOCK_CTRL_SEL0 7,14 CLOCK_CTRL_SEL1 SPI_CLK FPGA_CCLK 4 A4 CFG0 CFG1 CFG2 FPGA_0 FPGA_1 FPGA_2 FPGA_3 FPGA_4 FPGA_5 FPGA_6 FPGA_7 FPGA_8 FPGA_9 FPGA_10 FPGA_11 FPGA_12 FPGA_13 FPGA_14 FPGA_15 TCK_BUF TDI_XO TDI_PAC TMS_BUF M7 M1 P13 P10 N7 N8 P11 N13 N1 N3 N4 P1 M12 M2 M3 M4 M6 H12 H13 M13 N6 M14 B1 L3 A3 A2 M9 P4 M5 N5 P3 N12 K12 N14 DONE GSRN A1 INITN J2 G1 A5 P8 M8 J3 K1 E3 B7 P5 H2 FPGA_D0 FPGA_D1 FPGA_D2 FPGA_D3 FPGA_D4 FPGA_D5 FPGA_D6 FPGA_D7 LOADER_CK PROGRAMN C6 C2 K14 P12 L14 M11 G2 E2 FPGA_D15 FPGA_D14 FPGA_D13 FPGA_D12 FPGA_D11 FPGA_D10 FPGA_D9 FPGA_D8 3,5 14 FPGA_[0..15] 3_3V R82 2_2K-0603SMT 5 FPGA_D[0..7] 5 FPGA_D[8..15] 4 NC GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 SPI_CLK FPGA_CLK CFG0 CFG1 CFG2 TCK TDI TDO TMS SLEEPN FUNC_RESET FPGA_RESETN FPGA_DONE FPGA_INITN TSALL FPGA_DATA_0 FPGA_DATA_1 FPGA_DATA_2 FPGA_DATA_3 FPGA_DATA_4 FPGA_DATA_5 FPGA_DATA_6 FPGA_DATA_7 FPGA_CCLK FPGA_PROGRAMN FPGA_D15 FPGA_D14 FPGA_D13 FPGA_D12 FPGA_D11 FPGA_D10 FPGA_D9 FPGA_D8 U17 C109 100NF-0603SMT C110 10NF-0603SMT C5 3_3V C111 100NF-0603SMT Lattice FPGA Loader LCMXO1200C-CSBGA132 N2 D 5 C117 100NF-0603SMT FPGA_D[8..15] FPGA_D[0..7] G12 VCC C7 VCC H3 VCC P6 VCC GND B4 GND A10 A7 VCCAUX P7 VCCAUX GND D13 GND E1 GND F1 GND J14 GND C9 VCCIO0 B11 VCCIO1 E12 VCCIO2 L12 VCCIO3 GND L2 C112 100NF-0603SMT C113 3 3 FLASH_DQ_15 FLASH_DQ_14 FLASH_DQ_13 FLASH_DQ_12 FLASH_DQ_11 FLASH_DQ_10 FLASH_DQ_9 FLASH_DQ_8 FLASH_DQ_7 FLASH_DQ_6 FLASH_DQ_5 FLASH_DQ_4 FLASH_DQ_3 FLASH_DQ_2 FLASH_DQ_1 FLASH_DQ_0 CLOCK FLASH_WE_N FLASH_WP_N_ACC FLASH_RESET_N FLASH_OE_N FLASH_CEm FLASH_RD/BY FLASH_BYTEn FLASH_CE1_N FLASH_CE0_N FLASH_ADDRESS_0 FLASH_ADDRESS_1 FLASH_ADDRESS_2 FLASH_ADDRESS_3 FLASH_ADDRESS_4 FLASH_ADDRESS_5 FLASH_ADDRESS_6 FLASH_ADDRESS_7 FLASH_ADDRESS_8 FLASH_ADDRESS_9 FLASH_ADDRESS_10 FLASH_ADDRESS_11 FLASH_ADDRESS_12 FLASH_ADDRESS_13 FLASH_ADDRESS_14 FLASH_ADDRESS_15 FLASH_ADDRESS_16 FLASH_ADDRESS_17 FLASH_ADDRESS_18 FLASH_ADDRESS_19 FLASH_ADDRESS_20 FLASH_ADDRESS_21 FPGA_CSN FPGA_CS1N FPGA_WRITEN 10NF-0603SMT K3 VCCIO6 D2 VCCIO7 GND M10 VCCIO4 GND L13 VCCIO5 GND N11 GND P2 31 P9 C114 E14 D12 J12 G14 J13 F14 F13 E13 D3 C4 J1 H1 N9 K13 G13 G3 A8 K2 L1 P14 C1 B2 D1 F2 F3 C3 B6 A6 B3 B5 A9 B9 C10 B10 C11 A11 D14 C8 A14 B8 C14 B12 C13 A13 B13 A12 C12 B14 F12 H14 N10 FLASH_D15 FLASH_D14 FLASH_D13 FLASH_D12 FLASH_D11 FLASH_D10 FLASH_D9 FLASH_D8 FLASH_D7 FLASH_D6 FLASH_D5 FLASH_D4 FLASH_D3 FLASH_D2 FLASH_D1 FLASH_D0 FLASH_CLK FLASH_WE_N FLASH_WP_N_ACC FLASH_RESET_N FLASH_OE_N FLASH_CEm FLASH_RD/BY FLASH_BYTEn FLASH_A0 FLASH_A1 FLASH_A2 FLASH_A3 FLASH_A4 FLASH_A5 FLASH_A6 FLASH_A7 FLASH_A8 FLASH_A9 FLASH_A10 FLASH_A11 FLASH_A12 FLASH_A13 FLASH_A14 FLASH_A15 FLASH_A16 FLASH_A17 FLASH_A18 FLASH_A19 FLASH_A20 FLASH_A21 FPGA_CSN FPGA_CS1N FPGA_WRITEN 10NF-0603SMT FLASH_CLK 15 FPGA_CSN 5 FPGA_CS1N 5 FPGA_WRITEN 5 FLASH_A[0..21] FLASH_A21 FLASH_A20 FLASH_A19 FLASH_A18 FLASH_A17 FLASH_A16 FLASH_A15 FLASH_A14 FLASH_A13 FLASH_A12 FLASH_A11 FLASH_A10 FLASH_A9 FLASH_A8 FLASH_A7 FLASH_A6 FLASH_A5 FLASH_A4 FLASH_A3 FLASH_A2 FLASH_A1 FLASH_A0 2 H6 H1 C4 D3 D4 C3 B2 E6 D6 C6 A6 B6 D5 C5 A5 B5 A2 C2 D2 B1 A1 C1 D1 E1 2 U16 VCC DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 CEn OEn WEn RD/BY BYTEn WPn RESETn FLASH_D[0..15] S29GL064A GND GND A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 G4 G6 F5 G5 F4 G3 F3 G2 F2 E5 H5 E4 H4 H3 E3 H2 E2 F1 G1 A4 A3 F6 B3 B4 3_3V C115 C116 1 Wednesday, August 26, 2009 Sheet ECP3 SPB Eval Board Project 6 of 15 Rev 3.0 1605 Valley Center Parkway Bethlehem, PA 18017 Parallel FPGA Loader R81 10K-0603SMT 3_3V FLASH_D[0..15] 10NF-0603SMT Date: Size C Title FLASH_D15 FLASH_D14 FLASH_D13 FLASH_D12 FLASH_D11 FLASH_D10 FLASH_D9 FLASH_D8 FLASH_D7 FLASH_D6 FLASH_D5 FLASH_D4 FLASH_D3 FLASH_D2 FLASH_D1 FLASH_D0 FLASH_CEm FLASH_OE_N FLASH_WE_N FLASH_RD/BY FLASH_BYTEn FLASH_WP_N_ACC FLASH_RESET_N 100NF-0603SMT 1 A B C D Lattice Semiconductor LatticeECP3 Serial Protocol Board – Revision D User’s Guide Figure 25. Parallel FPGA Loader R83 1K-0603SMT A B C R127 R126 R122 R116 OPEN-0603SMT OPEN-0603SMT OPEN-0603SMT 8 OPEN-0603SMT 8 PCSB_SMA_P PCSB_SMA_N PCSB_REFCLKN OPEN-0603SMT CDC_Y0B_OUT CDC_Y0_OUT PCSB_REFCLKN OPEN-0603SMT R125 R121 PCSB_REFCLKP OPEN-0603SMT R118 ETH_SIN ETH_SIN_n ETH_SOUT ETH_SOUT_n 2 3 4 5 2 3 4 5 PCSC_OSC_N R131 R128 OPEN-0603SMT PCSC_REFCLKN OPEN-0603SMT R132 R130 PCSC_REFCLKP R129 OPEN-0603SMT OPEN-0603SMT SMA 1 5 2 3 4 5 SMA 1 J34 1 J33 2 3 4 5 SMA PCSB_SMA_N PCSB_SMA_P J30 SMA 1 J29 PCSC_SMA_P PCSC_SMA_N PCSC_SMA_P PCSC_SMA_N PCSC_REFCLKN OPEN-0603SMT SMA REF CLKs PCSC_REFCLKP PCSC_OSC_P 1 2 3 4 5 2 3 4 5 PCSB_HDINP0 PCSB_HDINP2 J22 SMA J14 SMA 2 3 4 5 2 3 4 5 PCSB_HDINN0 PCSB_HDINN2 SMA-TH 1 SMA-TH 1 J23 SMA J15 SMA PCSB_HDINP1 PCSB_HDINP3 SMA-TH 1 SMA-TH 1 2 3 4 5 2 3 4 5 J24 SMA J16 SMA PCSB_HDINN1 PCSB_HDINN3 SMA-TH 1 SMA-TH 1 3 2 3 4 5 2 3 4 5 J25 SMA J17 SMA PCSB_HDOUTP0 PCSB_HDOUTP2 SMA-TH 1 SMA-TH 1 9 9 9 9 3_3V 1_6R-0603SMT C135 R113 1_6R-0603SMT C132 R100 + + C126 J32 C128 C125 C123 C121 NC DIS# Q_N Q 2 3 4 5 2 3 4 5 1 SMA 1 J35 SMA PCSC_HDOUTP3 PCSC_HDINP3 4 2 3 4 5 2 3 4 5 1 SMA 1 J36 SMA PCSB_OSC_N 5 2 1 NC DIS# Q_N Q PCSC_HDOUTN3 PCSC_HDINN3 PCSC_OSC_N NOTE: PLACE TERMINATIONS CLOSE TO U18 DEVICE. 3 1 2 3 4 5 6 7 J26 SMA J18 SMA PCSB_HDOUTN0 PCSB_HDOUTN2 SMA-TH 1 SMA-TH 1 2 3 4 5 2 3 4 5 J27 SMA J19 SMA PCSB_HDOUTP1 R86 R89 51R-0603SMT +12V +12V RSVD_B3 GND SMCLK SMDAT GND +3.3V JTAG1 3.3Vaux WAKE# RSVD_B12 GND PETp0 PETn0 GND PRSNT3# GND PETp1 PETn1 GND GND PETp2 PETn2 GND GND PETp3 PETn3 GND RSVD_B30 PRSNT4# GND PCI Express x4 Edge Finger Conn. PRSNT1# +12V +12V GND JTAG2 JTAG3 JTAG4 JTAG5 +3.3V +3.3V PERST# GND REFCLK+ REFCLKGND PERp0 PERn0 GND RSVD_A19 GND PERp1 PERn1 GND GND PERp2 PERn2 GND GND PERp3 PERn3 GND RSVD_A32 CN3 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 1 2 4 5 PCSB_SMA_N R90 51R-0603SMT PCSB_OSC_P PCSB_OSC_N R98 R104 3_3V R110 51R-0603SMT x4_PETp3 x4_PETn3 x4_PETp2 x4_PETn2 x4_PETp1 x4_PETn1 x4_PETp0 x4_PETn0 PCIE_3V3 1 TP26 TestPoint 2 PCSC_OSC_P PCSC_OSC_N MUX U18B MUX MC100LVEL56 SEL1 VBB1 D1B_N D1B D1A_N D1A 3_3V Q1 Q1_N 3_3V 13 12 3_3V 2_8K-0603SMT R120 1_62K-0603SMT R114 R111 82R-0603SMT Q PCSC_REFCLKP R258 0R-0603SMT Qn PCSC_REFCLKN R259 0R-0603SMT R109 130R-0603SMT PCSC 2_8K-0603SMT R99 1_62K-0603SMT R95 3_3V PCSB_REFCLKN R339 62R-0603SMT 1_Q 1_Qn 19 18 R338 62R-0603SMT PCSB_REFCLKP PCSB 1 C138 C140 C142 C144 R133 OPEN-0603SMT Place near U1 C145 C143 C141 C139 x4_PCIE_CLKN 100NFX5R-0402SMT 100NFX5R-0402SMT 100NFX5R-0402SMT 100NFX5R-0402SMT 100NFX5R-0402SMT 100NFX5R-0402SMT 100NFX5R-0402SMT 100NFX5R-0402SMT x4_PERn3 x4_PERp3 x4_PERn2 x4_PERp2 x4_PERn1 x4_PERp1 x4_PERn0 x4_PERp0 Date: Size C Title 1 Wednesday, August 26, 2009 Sheet ECP3 SPB Eval Board Project SERDES R105 3_3V R112 7 of 15 Rev 3.0 1605 Valley Center Parkway Bethlehem, PA 18017 All Nets are 100-ohm differential pairs. The P and N traces shall be <20mil matched in length x4_PCIE_CLKP PCSA_HDOUTN0 PCSA_HDOUTP0 PCSA_HDOUTN1 PCSA_HDOUTP1 PCSA_HDOUTN2 PCSA_HDOUTP2 PCSA_HDOUTN3 PCSA_HDOUTP3 PCIE TERMINATIONS 15 8 10 9 7 6 Q0 + C130 100NF-0603SMT MC100LVEL56 COM_SEL SEL0 VBB0 D0B_N D0B D0A_N PCSC_SMA_N 3_4K-0603SMT R117 R108 51R-0603SMT + U18A D0A Q0_N 3_3V + C119 100NF-0603SMT PCSC_SMA_P C129 100NF-0603SMT 3_4K-0603SMT 16 17 3 1 PCSB_SMA_P + PCSB_HDOUTN3 OPEN-0603SMT OPEN-0603SMT R103 3_3V 6,14 CLOCK_CTRL_SEL1 6,14 CLOCK_CTRL_SEL0 PCSB_HDOUTN1 SMA-TH B side = PRIMARY Component Side(TOP) A side = SECONDARY Component Side(BOTTOM) x4_PERp3 x4_PERn3 x4_PERp2 x4_PERn2 x4_PERp1 x4_PERn1 x4_PERp0 x4_PERn0 x4_PCIE_CLKP x4_PCIE_CLKN PCIE_PERSTN A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 1 SMA-TH C118 100NF-0603SMT J28 SMA J20 SMA NOTE: PLACE TERMINATIONS CLOSE TO DEVICE. 2 3 4 5 2 3 4 5 OPEN-0603SMT OPEN-0603SMT R85 3_3V 3_3V PCSB_HDOUTP3 SMA-TH 1 SMA-TH 1 REFCLK MUXES OUT_SATA_TGT+ OUT_SATA_TGT- IN_SATA_TGT+ IN_SATA_TGT- 2 3 4 5 2 3 4 5 2 X4 PCIe Board Fingers 12_0VIN PCIE_3V3 82R-0603SMT R124 NOTE: PLACE TERMINATIONS CLOSE TO U18 DEVICE. R115 130R-0603SMT 82R-0603SMT R107 SATA G A+ AG BB+ G CN2 Target OUT_SATA_HOST- R102 130R-0603SMT 150R-0603SMT R97 IN_SATA_HOST+ IN_SATA_HOST- OUT_SATA_HOST+ OUT_SATA_HOST- 14 PCIE_PERSTN R123 82R-0603SMT PCSC_OSC_P 5 R119 130R-0603SMT 4 Y2 CW-P423-125.00MHZ 3_3V 3_3V R106 82R-0603SMT PCSB_OSC_P 4 1 2 3 4 5 6 7 150R-0603SMT R96 Y1 R101 CW-P423-156.25MHZ 130R-0603SMT 125MHZ 2 1 SATA G A+ AG BB+ G CN1 Host OUT_SATA_HOST+ PCSC_HDOUTN1 PCSC_HDOUTP1 PCSC_HDOUTN0 PCSC_HDOUTP0 PCSC_HDINN1 PCSC_HDINP1 PCSC_HDINN0 PCSC_HDINP0 156.25MHZ OUT_SATA_TGT- 10NF-0402SMT 150R-0603SMT R92 10NF-0402SMT 10NF-0402SMT C124 10NF-0402SMT C122 10NF-0402SMT C120 SMA TEST POINTS PCSC J31 3_3V 150R-0603SMT OUT_SATA_TGT+ OUT_SATA_HOST+ OUT_SATA_HOST- 50 50 R91 OUT_SATA_TGT+ OUT_SATA_TGT- 50 50 10NF-0402SMT 10NF-0402SMT IN_SATA_HOST+ IN_SATA_HOST- 50 IN_SATA_TGT- 50 50 10NF-0402SMT IN_SATA_TGT+ 50 SATA CONNECTIONS & TERMINATIONS SMA-TH 1 SMA-TH REFCLK STUFFING OPTIONS PCSB_REFCLKN PCSB_REFCLKP PCSB_OSC_N PCSB_REFCLKP PCSB_OSC_P ECP3-90-1156BGA PCSC_VCCOB PCSC_VCCIB ETH_SIN ETH_SIN_n ETH_SOUT ETH_SOUT_n PCSB_VCCOB PCSB_VCCIB PCSA_VCCOB PCSA_VCCIB J21 SMA J13 SMA C133 C136 D 2 3 4 5 2 3 4 5 100NF-0603SMT 100NF-0603SMT C127 4 10UF-16V-TANTBSMT 10UF-16V-TANTBSMT 6 VCC 3 10NF-0603SMT 20 VCC SMA TEST POINTS- PCSB C134 R87 130R-0603SMT R93 82R-0603SMT 5 x4_PETp3 AL21 x4_PETn3 AK21 x4_PETp2 AL20 x4_PETn2 AK20 x4_PETp1 AL19 x4_PETn1 AK19 x4_PETp0 AL18 x4_PETn0 AK18 AP21 PCSA_HDOUTP0 AN21 PCSA_HDOUTN0 AP20 PCSA_HDOUTP1 AN20 PCSA_HDOUTN1 PCSA_HDOUTP2 AP19 AN19 PCSA_HDOUTN2 AP18 PCSA_HDOUTP3 AN18 PCSA_HDOUTN3 AH19 x4_PCIE_CLKP AH20 x4_PCIE_CLKN AF21 AF20 AF19 AF18 AG21 AG20 AG19 AG18 PCSB_HDINP0 AL17 AK17 PCSB_HDINN0 PCSB_HDINP1 AL16 AK16 PCSB_HDINN1 PCSB_HDINP2 AL15 AK15 PCSB_HDINN2 PCSB_HDINP3 AL14 AK14 PCSB_HDINN3 AP17 PCSB_HDOUTP0 AN17 PCSB_HDOUTN0 AP16 PCSB_HDOUTP1 AN16 PCSB_HDOUTN1 AP15 PCSB_HDOUTP2 AN15 PCSB_HDOUTN2 AP14 PCSB_HDOUTP3 AN14 PCSB_HDOUTN3 AH15 PCSB_REFCLKP AH16 PCSB_REFCLKN AF17 AF16 AF15 AF14 AG17 AG16 AG15 AG14 PCSC_HDINP0 AL25 AK25 PCSC_HDINN0 PCSC_HDINP1 AL24 AK24 PCSC_HDINN1 PCSC_HDINP2 AL23 PCSC_HDINN2 AK23 PCSC_HDINP3 AL22 AK22 PCSC_HDINN3 AP25 PCSC_HDOUTP0 AN25 PCSC_HDOUTN0 AP24 PCSC_HDOUTP1 AN24 PCSC_HDOUTN1 AP23 PCSC_HDOUTP2 AN23 PCSC_HDOUTN2 AP22 PCSC_HDOUTP3 AN22 PCSC_HDOUTN3 AH22 PCSC_REFCLKP AH23 PCSC_REFCLKN AF24 AF23 AF22 AE20 AG24 AG23 AG22 AE21 C131 C137 PCSA_HDINP0 PCSA_HDINN0 PCSA_HDINP1 PCSA_HDINN1 PCSA_HDINP2 PCSA_HDINN2 PCSA_HDINP3 PCSA_HDINN3 PCSA_HDOUTP0 PCSA_HDOUTN0 PCSA_HDOUTP1 PCSA_HDOUTN1 PCSA_HDOUTP2 PCSA_HDOUTN2 PCSA_HDOUTP3 PCSA_HDOUTN3 PCSA_REFCLKP PCSA_REFCLKN PCSA_VCCIB0 PCSA_VCCIB1 PCSA_VCCIB2 PCSA_VCCIB3 PCSA_VCCOB0 PCSA_VCCOB1 PCSA_VCCOB2 PCSA_VCCOB3 PCSB_HDINP0 PCSB_HDINN0 PCSB_HDINP1 PCSB_HDINN1 PCSB_HDINP2 PCSB_HDINN2 PCSB_HDINP3 PCSB_HDINN3 PCSB_HDOUTP0 PCSB_HDOUTN0 PCSB_HDOUTP1 PCSB_HDOUTN1 PCSB_HDOUTP2 PCSB_HDOUTN2 PCSB_HDOUTP3 PCSB_HDOUTN3 PCSB_REFCLKP PCSB_REFCLKN PCSB_VCCIB0 PCSB_VCCIB1 PCSB_VCCIB2 PCSB_VCCIB3 PCSB_VCCOB0 PCSB_VCCOB1 PCSB_VCCOB2 PCSB_VCCOB3 PCSC_HDINP0 PCSC_HDINN0 PCSC_HDINP1 PCSC_HDINN1 PCSC_HDINP2 PCSC_HDINN2 PCSC_HDINP3 PCSC_HDINN3 PCSC_HDOUTP0 PCSC_HDOUTN0 PCSC_HDOUTP1 PCSC_HDOUTN1 PCSC_HDOUTP2 PCSC_HDOUTN2 PCSC_HDOUTP3 PCSC_HDOUTN3 PCSC_REFCLKP PCSC_REFCLKN PCSC_VCCIB0 PCSC_VCCIB1 PCSC_VCCIB2 PCSC_VCCIB3 PCSC_VCCOB0 PCSC_VCCOB1 PCSC_VCCOB2 PCSC_VCCOB3 SERDES 10NF-0603SMT 14 VCC R88 130R-0603SMT R94 82R-0603SMT U1H 100NF-0603SMT 100NF-0603SMT VEE GND 6 VCC GND 3 32 11 130R-0603SMT 82R-0603SMT A B C D Lattice Semiconductor LatticeECP3 Serial Protocol Board – Revision D User’s Guide Figure 26. SERDES A B C 5 SW6 SW5 R147 10K-0402SMT 2 1 R140 10K-0402SMT 2 1 AMBER_LED 1 3_3V Y3 Y3B Y2 Y2B Y1 Y1B CDC_STATUS_VCXO Y4 Y4B C152 10NF-0402SMT CDC_RESET C150 10NF-0402SMT CDC_PWR_DWN C161 22UF-16V-TANTBSMT 1 2 75 OHM @ 100MHZ L2 C155 22UF-16V-TANTBSMT 1 2 75 OHM @ 100MHZ L1 CDC_Y2B_OUT CDC_Y2_OUT CDC_Y1B_OUT CDC_Y1_OUT + + 4 CDC_Y2B_OUT CDC_Y2_OUT CDC_Y1B_OUT CDC_Y1_OUT R151 2 CDC_STATUS_REF 1 750R-0402SMT D13 AMBER_LED R150 1 1 2 750R-0402SMT D14 1 R152 2 Y1 150R-0402SMT 1 R153 2 Y1B 150R-0402SMT 1 R156 2 Y2 150R-0402SMT 1 R157 2 Y2B 150R-0402SMT 1 R158 2 Y3 150R-0402SMT 1 R159 2 Y3B 150R-0402SMT 1 R160 2 Y4 150R-0402SMT 1 R161 2 Y4B 150R-0402SMT 2 2 CDC_RST CDC_PWRDWN 2 1 2 1 + + CDC7005 NPD VCC Y1 Y1B VCC VCC Y2 Y2B VCC VCC Y3 Y3B VCC NRESET VCC Y4 Y4B VCC VCC VCC VCC STATUS_VCXO STATUS_REF GND U19 C162 10UF-16V-TANTBSMT C156 10UF-16V-TANTBSMT 14 14 14 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 C157 100NF-0603SMT VCC Y0B Y0 VCC VCC VCXO_INB VCXO_IN VCC I_REF AVCC AVCC REF_IN CTRL_LE CTRL_CLK NC CTRL_DATA AVCC CP_OUT AVCC OPA_IN OPA_IP AVCC OPA_OUT STATUS_LOCK C163 100NF-0603SMT 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 C164 33NF-0402SMT C158 33NF-0402SMT CDC_STATUS_LOCK CDC_CP_OUT 1 2 R144 12K-0402SMT CDC_REFCLK CDC_3_3V C165 10NF-0402SMT 3 C159 10NF-0402SMT 14 C153 100NF-0603SMT C166 10NF-0402SMT CDC_3_3V 10NF-0402SMT C160 CDC_AVCC D15 AMBER_LED R154 750R-0402SMT CDC_CTRL_DATA CDC_REFCLK 14 CDC_CTRL_LE 14 CDC_CTRL_CLK 14 CDC_VCXO_INB CDC_VCXO_IN 3 CDC_Y0B CDC_Y0 R138 150R-0603SMT R139 150R-0603SMT 1 2 3 4 5 2 CDC_SPI_CLK CDC_SPI_LE C41710PF-0402SMT 1 2 C41610PF-0402SMT 1 2 C41510PF-0402SMT 1 2 J47 C149 1 100PF-0402SMT C151 2 1 6 5 4 CDC_3_3V VCXO1 TCO-2111 VCC V_CTRL OUTB EN OUT GND 10NF-0603SMT 100NF-0603SMT 2 1 R137 22R-0603SMT C147 22 1CDC_Y0B_OUT C146 22 1 R136 1 CDC_Y0_OUT 22R-0603SMT 10NF-0603SMT 2 U31 C419 10NF-0402SMT 14 VCC 13 2 4OE 12 4A 11 4Y 10 3OE 9 3A 8 3Y 1 SN74LV125 1OE 1A 1Y 2OE 2A 2Y GND CDC_SPI_DATA 1 2 3 4 5 6 7 CDC_3_3V C418 100NF-0603SMT 1 2 2 R345 1 100K-0402SMT 2 R344 1 100K-0402SMT 2 R343 1 100K-0402SMT Place VCXO as close as possible to CDC7005 device R145 82R-0402SMT HDR5 C154 22UF-16V-TANTBSMT R155 4_7K-0402SMT R149 82R-0402SMT 2 OPEN-0603SMT R134 R141 130R-0402SMT CDC_3_3V CDC_3_3V R148 130R-0402SMT CDC_3_3V + 1 2 1 2 1 2 1 2 R135 OPEN-0603SMT 2 21 1 CDC_AVCC 1 2 2 1 1 2 2 1 2 1 2 1 CDC_3_3V 1 2 1 2CDC_CTRL_LE R340 100R-0402SMT 4 1 2 1 2 1 2 CDC_CTRL_CLK 1 2 R341 100R-0402SMT 1 2 3 CDC_3_3V R146 OPEN-0402SMT R142 10K-0402SMT CDC_3_3V Date: Size C C148 100NF-0603SMT 1 Wednesday, August 26, 2009 Sheet 8 of 17 Rev 3.0 1605 Valley Center Parkway Bethlehem, PA 18017 R143 160R-0402SMT 1 ECP3 SPB Eval Board Project Clock Cleaner 1 2 R347 100K-0402SMT Title 7 R346 10K-0402SMT CDC_3_3V 1 7 V_CTRL CDC_Y0B_OUT CDC_Y0_OUT 2 1 2 1 2 1 1 2 D 5 1 2 1 2 1 2 1 33 2 CDC_CTRL_DATA 1 2 R342 100R-0402SMT A B C D Lattice Semiconductor LatticeECP3 Serial Protocol Board – Revision D User’s Guide Figure 27. Clock Cleaner A B C EN ADJ ETH_MD3_N ETH_MD3_P ETH_MD2_N ETH_MD2_P ETH_MD1_N ETH_MD1_P ETH_MD0_N 5 1 2 VCC OUT 25MHz DI OSC_SMT EN GND Y3 14 ETH_RX_ER 14 ETH_RX_DV 14 ETH_RX_CLK 14 ETH_RX_D[0..7] 14 ETH_TX_EN 14 ETH_TX_ER 14 ETH_TX_CLK 14 ETH_TX_D[0..7] 14 ETH_GTX_CLK ETH_MD0_P Place termination resistors RX_D0-7, RX_ER, RX_DV, RX_CLK, TX_CLK, CRS, COL as close to the G-PHY as possible using 50 ohm impedence traces. Place termination resistors TX_D0-7, TX_ER, TX_EN, GTX_CLK as close to FPGA as possible using 50 ohm impedence traces. 5 GND GND GND 3 6 7 D 4 3 2 1 SO-8 DI 33R-0402SMT 33R-0402SMT R175 R176 ETH_TX_D6 ETH_TX_D7 3_3V AVDD CLK25 R201 R202 TP31 PHY_CLK25 Place caps close to RJ45 jack L4 ETH_COMA U21 COMA XTAL1 XTAL2 125CLK CRS COL CONFIG0 CONFIG1 CONFIG2 CONFIG3 CONFIG4 CONFIG5 CONFIG6 SEL_FREQ RX_DV RX_ER RX_CLK RXD0 RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7 TX_EN TX_ER TX_CLK TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7 GTX_CLK ETH_1_2V C189 10NF-0402SMT C188 10NF-0402SMT C187 10NF-0402SMT C186 10NF-0402SMT 88e1111 117TFBGA DI H9 J9 K2 B5 B6 D8 E9 F8 G7 F9 G9 G8 H8 B1 D2 C1 B2 D3 C3 B3 C4 A1 A2 C5 E1 F2 D1 F1 G2 G3 H2 H1 H3 J1 J2 E2 ETH_125CLK PHY_CRS PHY_COL PHY_FREQ_SEL ETH_CFG0 ETH_CFG1 ETH_CFG2 ETH_CFG3 ETH_CFG4 ETH_CFG5 ETH_CFG6 33R-0402SMT 33R-0402SMT R204 4_7K-0402SMT 22R-0603SMT R203 ETH_CRS ETH_COL PHY_RX_D0 PHY_RX_D1 PHY_RX_D2 PHY_RX_D3 PHY_RX_D4 PHY_RX_D5 PHY_RX_D6 PHY_RX_D7 33R-0402SMT PHY_RX_DV 33R-0402SMT PHY_RX_ER 33R-0402SMT PHY_RX_CLK 33R-0402SMT 33R-0402SMT 33R-0402SMT 33R-0402SMT 33R-0402SMT 33R-0402SMT 33R-0402SMT 33R-0402SMT PHY_TX_EN PHY_TX_ER PHY_TX_CLK PHY_TX_D0 PHY_TX_D1 PHY_TX_D2 PHY_TX_D3 PHY_TX_D4 PHY_TX_D5 PHY_TX_D6 PHY_TX_D7 PHY_GTX_CLK 33R-0402SMT 33R-0402SMT 33R-0402SMT R189 R190 R191 R180 R181 R182 R183 R184 R185 R186 R188 10 ETH_CFG[0..6] ETH_RX_D0 ETH_RX_D1 ETH_RX_D2 ETH_RX_D3 ETH_RX_D4 ETH_RX_D5 ETH_RX_D6 ETH_RX_D7 R178 R172 R179 33R-0402SMT C171 100NF-0603SMT ETH_1_2V C170 10NF-0603SMT C169 100NF-0603SMT 4 8 7 9 3 1 2 4 6 5 11 12 10 RJ-45 MDID+ MDDCT MDID- MDIC+ MDCCT MDIC- MDIB+ MDBCT MDIB- MDIA+ MDACT MDIA- J37 LED2+ LED2LED1+ LED1- SHLD1 SHLD2 7 8 4 5 3 6 1 2 16 15 14 13 19 20 MH1 MH2 MHOLE_1 MHOLE_1 0.100_PTH 0.100_PTH MH1 and MH2 are 0.100" diameter plated through holes Ethernet RJ45 Connector 14 ETH_CRS 14 ETH_COL ETH_RX_DV ETH_RX_ER ETH_RX_CLK ETH_TX_EN ETH_TX_ER ETH_TX_CLK 33R-0402SMT 33R-0402SMT R174 R171 ETH_TX_D4 ETH_TX_D5 33R-0402SMT 33R-0402SMT R169 R170 ETH_TX_D2 ETH_TX_D3 33R-0402SMT 33R-0402SMT R165 C168 R167 R168 + ETH_TX_D0 ETH_TX_D1 ETH_GTX_CLK C167 47UF-10V-TANTBSMT ETH_TX_D[0..7] OUT C185 10NF-0402SMT 2 1 IN 1 2 ETH_RX_D[0..7] 1UF-16V-0805SMT RJ45 U20 LT1963-ADJ 2 8 1 2_5V 1 4 ETH_LED_TX_PU ETH_LED_TX ETH_LED_RX_PU ETH_LED_RX 22UF-16V-TANTBSMT 2_5V + C172 C6 C7 D7 E3 E7 F3 J3 J7 DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD C173 B9 F7 J8 VDDOH VDDOH VDDOH 1UF-16V-0805SMT B4 C2 K1 VDDO VDDO VDDO K9 L2 VDDOX VDDOX AVDD AVDD PHY_MDIO PHY_MDC PHY_RESET_N PHY_INT_N PHY_FREQ_SEL PHY_CLK25 PHY_NET0 PHY_NET1 PHY_NET2 PHY_NET3 PHY_NET4 PHY_NET5 3 B7 M3 M4 M7 M8 N5 PHY_NET[0..5] 3 MDIO_3 MDIO_3 MDIO_2 MDIO_2 MDIO_1 MDIO_1 MDIO_0 MDIO_0 MDIO MDC 14 TDI TDO TMS TCK TRST HSDAC HSDAC S_OUT S_OUT S_CLK S_CLK S_IN S_IN RSET RESET INT ETH_SOUT ETH_SOUT_n A7 A8 L7 K8 L8 L9 M9 R205 4_7K-0402SMT HSDAC_TP HSDAC_n_TP SCLK SCLKb ETH_RSET_N ETH_SIN ETH_SIN_n A5 A6 M2 A3 A4 PHY_RESET_N PHY_INT_N R187 TP29 TP30 ETH_SOUT ETH_SOUT_n TP27 TP28 ETH_SIN ETH_SIN_n R192 1_5K-0402SMT PHY_MDIO PHY_MDC K3 L1 M1 L3 ETH_MD3_P ETH_MD3_N ETH_MD2_P ETH_MD2_N ETH_MD1_P ETH_MD1_N ETH_MD0_P ETH_MD0_N ETH_LED_1000 ETH_LED_100 ETH_LED_10 ETH_LED_DUPLEX ETH_LED_RX ETH_LED_TX M5 M6 2_5V R163 220R-0402SMT A9 B8 C8 E8 C9 D9 N8 N9 N6 N7 N3 N4 N1 N2 FB14 BLM41PG600SN1 LINK1000 LINK100 LINK10 DUPLEX RX_LED TX_LED AVDD AVDD AVDD AVDD AVDD AVDD GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VSSC ETH_LED_TX_PU 5 1 34 D4 D5 D6 E4 E5 E6 F4 F5 F6 G4 G5 G6 H4 H5 H6 J4 J5 J6 K4 K5 K6 L5 L6 H7 ETH_LED_RX_PU 7 7 7 7 2_5V 5K-0402SMT ETH_LED5 ETH_LED4 ETH_LED3 ETH_LED2 ETH_LED1 ETH_LED0 R164 220R-0402SMT 10 2 D18 GREEN_LED D17 AMBER_LED D16 AMBER_LED R193 R194 ETH_MD1_P C182 10NF-0603SMT MD1_BIAS R198 C183 10NF-0603SMT MD2_BIAS Date: Size C Title C184 10NF-0603SMT MD3_BIAS Wednesday, August 26, 2009 1 Sheet ECP3-SPB Eval Board 9 of 17 Rev 3.0 1605 Valley Center Parkway Bethlehem, PA 18017 1000BASE-T PHY/RJ45 Project ETH_MD3_P ETH_MD3_N 49_9R-0402SMT 49_9R-0402SMT ETH_MD2_N R199 OSC bypass C180 100NF-0603SMT R200 C179 10NF-0603SMT ETH_MD2_P 49_9R-0402SMT 49_9R-0402SMT ETH_MD1_N R197 VDDO bypass C178 100NF-0603SMT 2_5V 2_5V 1 Place 49 ohm termination resistors as close as possible to G-PHY. The associated 0.01uF capacitor should be placed close to the 49 ohm resistors. C181 10NF-0603SMT MD0_BIAS R196 C176 100NF-0603SMT 49_9R-0402SMT 49_9R-0402SMT ETH_MD0_N R195 ETH_MD0_P DI led_0603 DI led_0603 DI led_0603 DI led_0603 C177 10NF-0603SMT ETH_1_2V DVDD bypass C174 220NF-0603SMT C175 100NF-0603SMT AVDD ETH_LED_DUPLEX R177 ETH_LED_DUPLEX_PU 220R-0603SMT D19 AMBER_LED ETH_LED_1000_PU R173 220R-0603SMT R166 220R-0603SMT ETH_LED_100 ETH_LED_1000 ETH_LED_10_PU R162 220R-0603SMT ETH_LED_10 49_9R-0402SMT 49_9R-0402SMT ETH_LED[0..5] 2 A B C D Lattice Semiconductor LatticeECP3 Serial Protocol Board – Revision D User’s Guide Figure 28. 1000BASE-T PHY/RJ45 35 A B C 5 9 ETH_CFG[0..6] 2_5V TDA DIP-8 SW7 TDA DIP-8 SW9 3 TDA DIP-8 SW10 ETH_LED_10 ETH_LED_100 ETH_LED_1000 ETH_LED_DUPLEX ETH_LED_RX ETH_LED_TX ETH_LED3 ETH_LED4 ETH_LED5 ETH_LED2 ETH_LED1 ETH_LED0 TDA DIP-8 SW11 ETH_LED[0..5] ETH_CFG4 ETH_CFG2 ETH_CFG1 9 2 4 3 2 ONLY ONE SWITCH PER DIP PACK CAN BE ACTIVE AT A TIME TDA DIP-8 SW8 4 ETH_CFG3 D 5 Title Date: Size B ETH_CFG5 Wednesday, August 26, 2009 1 Sheet ECP3 SPB Eval Board Project TDA DIP-8 SW13 ETH_CFG6 10 of 17 Rev 3.0 1605 Valley Center Parkway Bethlehem, PA 18017 PHY CONFIGURATION TDA DIP-8 SW12 1 A B C D Lattice Semiconductor LatticeECP3 Serial Protocol Board – Revision D User’s Guide Figure 29. PHY Configuration ETH_CFG0 36 A B C D 5 5 1_5V C223 C224 W11 W10 C225 VTT6 VTT6 AB12 V11 V12 AB11 U2 U1 V9 V8 V2 V1 V5 W5 V4 V3 V7 W7 W2 W1 W8 W9 W4 W3 W6 Y6 Y2 Y1 Y8 AA8 Y5 Y4 Y9 Y10 AA2 AA1 Y7 AA7 AA4 AA3 AA10 AB9 AB2 AB1 AA5 AB5 AD2 AD1 AC6 AC7 AD4 AD3 AE2 AE1 AE4 AE3 AM1 AM2 AL1 AL2 AN1 AN2 AD9 AD8 AP2 AP3 AJ2 AJ3 AL3 AK3 AJ4 AK4 AN3 AM3 AJ5 AJ6 AL5 AM5 AM6 AN6 AL4 AM4 AP5 AP6 AH7 AJ7 AE9 AD10 AK6 AL6 AF9 AG9 AK7 AL7 AN7 AP7 AN8 AP8 AK8 AL8 AM7 AM8 AH9 AJ8 C226 C227 1_5V 4 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT C222 Bank 6 ECP3-90-1156BGA VCCIO6 VCCIO6 VCCIO6 VCCIO6 PL44A/LDQ49 PL44B/LDQ49 PL46A/LDQ49/PCLKT6_0 PL46B/LDQ49/PCLKC6_0 PL47A/LDQ49 PL47B/LDQ49 PL49A/LDQS49 PL49B/LDQS49# PL50A/LDQ49 PL50B/LDQ49 PL52A/LDQ49/VREF1_6 PL52B/LDQ49/VREF2_6 PL53A/LDQ58 PL53B/LDQ58 PL55A/LDQ58 PL55B/LDQ58 PL56A/LDQ58 PL56B/LDQ58 PL58A/LDQS58 PL58B/LDQS58# PL59A/LDQ58 PL59B/LDQ58 PL61A/LDQ58 PL61B/LDQ58 PL61E_A/LDQ58/LLM1_GPLLT_FB_A PL61E_B/LDQ58/LLM1_GPLLT_FB_B PL61E_C/LDQ58/LLM1_GPLLT_IN_A PL61E_D/LDQ58/LLM1_GPLLT_IN_B PL62A/LDQ67 PL62B/LDQ67 PL64A/LDQ67 PL64B/LDQ67 PL65A/LDQ67 PL65B/LDQ67 PL67A/LDQS67 PL67B/LDQS67# PL68A/LDQ67 PL68B/LDQ67 PL70A/LDQ67 PL70B/LDQ67 PL70E_A/LDQ67/LLM2_GPLLT_FB_A PL70E_B/LDQ67/LLM2_GPLLT_FB_B PL70E_C/LDQ67/LLM2_GPLLT_IN_A PL70E_D/LDQ67/LLM2_GPLLT_IN_B PL71A PL71B PL74A PL74B PL77A PL77B PL79E_A/LLM3_GPLLT_FB_A PL79E_B/LLM3_GPLLT_FB_B PL79E_C/LLM3_GPLLT_IN_A PL79E_D/LLM3_GPLLT_IN_B PL80A/LDQ85 PL80B/LDQ85 PL82A/LDQ85 PL82B/LDQ85 PL83A/LDQ85 PL83B/LDQ85 PL85A/LDQS85 PL85B/LDQS85# PL86A/LDQ85 PL86B/LDQ85 PL88A/LDQ85 PL88B/LDQ85 PL89A/LDQ94 PL89B/LDQ94 PL91A/LDQ94 PL91B/LDQ94 PL92A/LDQ94 PL92B/LDQ94 PL94A/LDQS94 PL94B/LDQS94# PL95A/LDQ94 PL95B/LDQ94 PL97A/LDQ94 PL97B/LDQ94 PB2A PB2B PB4A PB4B PB5A PB5B PB7A PB7B PB8A PB8B PB14A PB14B PB16A PB16B PB10A PB10B PB11A PB11B PB13A PB13B U1E BANK6 4 3 3 1_8V C215 C216 C217 VTT7 VTT7 T11 T10 U12 U11 N12 N11 G4 G5 K9 K8 H5 H4 F2 F1 F3 E3 G2 G1 G3 H3 H1 J1 J3 H2 N4 N3 M5 N5 N2 N1 M10 N10 P5 P4 N8 P8 P2 P1 N7 N6 R7 R5 P9 P10 R2 R1 P7 P6 R4 R3 R9 R10 T6 T5 R8 T7 T4 T3 T9 T8 T2 T1 U9 U8 U5 U4 U6 U7 C218 C219 1_8V 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT C214 ECP3-90-1156BGA Bank 7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 PL2A PL2B PL4A PL4B PL5A PL5B PL8A/LDQ13 PL8B/LDQ13 PL10A/LDQ13 PL10B/LDQ13 PL11A/LDQ13 PL11B/LDQ13 PL13A/LDQS13 PL13B/LDQS13# PL14A/LDQ13 PL14B/LDQ13 PL16A/LDQ13 PL16B/LDQ13 PL17A/LDQ22 PL17B/LDQ22 PL19A/LDQ22 PL19B/LDQ22 PL20A/LDQ22 PL20B/LDQ22 PL22A/LDQS22 PL22B/LDQS22# PL23A/LDQ22 PL23B/LDQ22 PL25A/LDQ22 PL25B/LDQ22 PL25E_A/LDQ22/LUM2_GPLLT_FB_A PL25E_B//LDQ22/LUM2_GPLLT_FB_B PL25E_C/LDQ22/LUM2_GPLLT_IN_A PL25E_D//LDQ22/LUM2_GPLLT_IN_B PL26A/LDQ31 PL26B/LDQ31 PL28A/LDQ31 PL28B/LDQ31 PL29A/LDQ31 PL29B/LDQ31 PL31A/LDQS31 PL31B/LDQS31# PL32A/LDQ31 PL32B/LDQ31 PL34A/LDQ31/VREF1_7 PL34B/LDQ31/VREF2_7 PL35A/LDQ40 PL35B/LDQ40 PL37A/LUM0_GDLLT_IN_A/LDQ40 PL37B/LUM0_GDLLT_IN_B/LDQ40 PL38A/LUM0_GDLLT_FB_A/LDQ40 PL38B/LUM0_GDLLT_FB_B/LDQ40 PL40A/LDQS40 PL40B/LDQS40# PL41A/LDQ40 PL41B/LDQ40 PL43A/PCLKT7_0/LDQ40 PL43B/PCLKC7_0/LDQ40 PL43E_A/LUM0_GPLLT_FB_A PL43E_B/LUM0_GPLLT_FB_B PL43E_C/LUM0_GPLLT_IN_A PL43E_D/LUM0_GPLLT_IN_B U1F BANK7 2 2 Date: Size C Title 1 Wednesday, August 26, 2009 ECP3 SPB Card Project Bank 6 and Bank 7 Sheet 11 of 17 Rev 3.0 1605 Valley Center Parkway Bethlehem, PA 18017 1 A B C D Lattice Semiconductor LatticeECP3 Serial Protocol Board – Revision D User’s Guide Figure 30. Bank 6 and Bank 7 A B C D 6 5 FLASH_CLK 5 4 LA1 LA3 LA5 LA7 LA9 LA11 LA13 LA15 LA17 LA19 LA21 LA23 LA25 LA27 LA29 LA31 LA33 OSC_IN1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 1 2 3 4 3 4 5V GND CLK1 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 LA1 SCL SDA CLK 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 CY2304-1 8 7 6 5 2 1 LA2 LA4 LA6 LA8 LA10 LA12 LA14 LA16 LA18 LA20 LA22 LA24 LA26 LA28 LA30 LA32 LA34 OSC_IN2 OSC_IN3 2_767004 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 GND N/C REF FBK CLKA1 VDD CLKA2 CLKB2 GND CLKB1 U28 Y4 OUT Vcc 3_3V 1 3 5 7 9 11 13 15 17 HEADER 9X2 J40 GENERAL PURPOSE HEADER 2 4 6 8 10 12 14 16 18 TP_0 TP_1 TP_2 TP_3 TP_4 TP_5 TP_6 TP_7 TP_8 TP_9 TP_10 TP_11 TP_12 TP_13 TP_14 TP_15 LOGIC ANALYZER PROBE FLASH_CLK 100NF-0603SMT C343 CTS-CB3LV-3C-100.00MHZ-50ppm 4 TP_[0..15] 14 14 14 C345 10NF-0603SMT OSC_IN[1..3] LA[1..34] C344 100NF-0603SMT 100MHZ GENERAL PURPOSE CLOCKS 3_3V GND GND GND GND GND 39 40 41 42 43 14 SWITCH[1..8] 3 SW DIP-8/SM SWITCH1 SWITCH2 SWITCH3 SWITCH4 SWITCH5 SWITCH6 SWITCH7 SWITCH8 8 4_7K 9 RN4H EXB2HV472JV SWITCH8 SW14 7 4_7K 10 RN4G EXB2HV472JV SWITCH7 6 4_7K 11 RN4F EXB2HV472JV 5 4_7K 12 RN4E EXB2HV472JV SWITCH5 SWITCH6 14 RN4C 3 4_7K EXB2HV472JV 4 4_7K 13 RN4D EXB2HV472JV SWITCH4 2 4_7K 15 RN4B EXB2HV472JV SWITCH2 SWITCH3 1 4_7K 16 RN4A EXB2HV472JV SWITCH1 3_3V DIP SWITCH 3 14 LED[1..8] 3_3V LED1_PU 2 LED8 LED7 LED6 LED5 LED4 LED3 LED2 LED1 LED8_PU LED7_PU 7 470R 10 RN6G EXB2HV471JV 8 470R 9 RN6H EXB2HV471JV LED6_PU 6 470R 11 RN6F EXB2HV471JV LED5_PU LED4_PU 13 RN6D 4 470R EXB2HV471JV 5 470R 12 RN6E EXB2HV471JV LED3_PU LED2_PU 3 470R 14 RN6C EXB2HV471JV 2 470R 15 RN6B EXB2HV471JV 16 RN6A 1 470R EXB2HV471JV 2 LEDs Date: Size C Title 1 Wednesday, August 26, 2009 Sheet 13 of 15 Rev D 1605 Valley Center Parkway Bethlehem, PA 18017 LED-SMT1206_RED D22 LED-SMT1206_YELLOW D23 LED-SMT1206_GREEN D26 LED-SMT1206_BLUE D28 LED-SMT1206_BLUE D27 LED-SMT1206_GREEN D25 LED-SMT1206_YELLOW D24 ECP3 SPB Eval Board Project 1 LED-SMT1206_RED D21 FPGA TEST LED8 LED7 LED8_PU LED7_PU LED6 LED6_PU LED5 LED5_PU LED4 LED4_PU LED3 LED3_PU LED2 LED2_PU LED1 LED1_PU R Y G B B G Y 37 R A B C D Lattice Semiconductor LatticeECP3 Serial Protocol Board – Revision D User’s Guide Figure 31. FPGA Test A B C D U1K ECP3-90-1156BGA 5 C349 C350 C351 C359 C360 C361 C362 C363 C366 C367 C368 C369 C352 C353 C354 C364 C355 C356 C377 C378 C379 C371 C372 C373 C384 M HOLE2 MH3 1000PF-0402SMT C388 C380 M HOLE2 MH4 C386 C387 M HOLE2 MH5 C391 1000PF-0402SMT 1000PF-0402SMT C390 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C385 1000PF-0402SMT C389 1000PF-0402SMT 1000PF-0402SMT C383 C374 C381 C382 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C370 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C375 C376 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C365 VCCPLL 3_3V C348 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C358 1_2V_A 1_5V 2_5V C347 C357 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C346 VCC_CORE ALL CAPS PLACED UNDER BGA 4 3 M26 M27 M28 M29 M30 M31 M33 M34 N9 AA9 AB3 AB4 AB6 AB7 AB8 AB10 AB25 AB26 AB27 AB31 AB32 AC1 AC2 AC4 AC5 AC8 AC9 AC10 AC25 AC26 AC27 AC28 AD5 AD7 AD25 AD26 AD27 AD28 AD29 AD30 AD31 AD33 AD34 AE5 AE6 AE7 AE8 AE14 AE15 AE27 AE28 AE33 AE34 AF1 AF3 AF4 AF6 AF7 AF8 AF11 AF12 AF13 AF27 AF28 AF29 AF34 AG1 AG2 AG3 AG4 AG5 AG6 AG7 AG11 AG12 AG13 AG28 AG29 AG30 AG31 AG32 AG33 AG34 AH1 AH2 AH3 AH4 AH5 AH6 AH8 AH12 AH13 AH29 AH30 AH31 AH32 AH34 AJ1 AJ29 AJ30 AJ32 AK1 AK10 AK11 AK12 AK13 AL10 AL11 AL12 AL13 AN10 AN11 AN12 AN13 AP10 AP11 AP12 AP13 NC121 NC122 NC123 NC124 NC125 NC126 NC127 NC128 NC129 NC130 NC131 NC132 NC133 NC134 NC135 NC136 NC137 NC138 NC139 NC140 NC141 NC142 NC143 NC144 NC145 NC146 NC147 NC148 NC149 NC150 NC151 NC152 NC153 NC154 NC155 NC156 NC157 NC158 NC159 NC160 NC161 NC162 NC163 NC164 NC165 NC166 NC167 NC168 NC169 NC170 NC171 NC172 NC173 NC174 NC175 NC176 NC177 NC178 NC179 NC180 NC181 NC182 NC183 NC184 NC185 NC186 NC187 NC188 NC189 NC190 NC191 NC192 NC193 NC194 NC195 NC196 NC197 NC198 NC199 NC200 NC201 NC202 NC203 NC204 NC205 NC206 NC207 NC208 NC209 NC210 NC211 NC212 NC213 NC214 NC215 NC216 NC217 NC218 NC219 NC220 NC221 NC222 NC223 NC224 NC225 NC226 NC227 NC228 NC229 NC230 NC231 NC232 NC233 NC234 NC235 NC236 NC237 NC238 NC120 NC119 NC117 NC118 NC116 NC115 NC114 NC113 NC112 NC111 NC110 NC109 NC108 NC107 NC106 NC105 NC104 NC103 NC102 NC101 NC100 NC99 NC98 NC97 NC96 NC95 NC94 NC93 NC92 NC91 NC90 NC89 NC88 NC87 NC86 NC85 NC84 NC83 NC82 NC81 NC80 NC79 NC78 NC77 NC76 NC75 NC74 NC73 NC72 NC71 NC70 NC69 NC68 NC67 NC66 NC65 NC64 NC63 NC62 NC61 NC60 NC59 NC58 NC57 NC56 NC55 NC54 NC53 NC52 NC51 NC50 NC49 NC48 NC47 NC46 NC45 NC44 NC43 NC42 NC41 NC40 NC39 NC38 NC37 NC36 NC35 NC34 NC33 NC32 NC31 NC30 NC29 NC28 NC27 NC26 NC25 NC24 NC23 NC22 NC21 NC20 NC19 NC18 NC17 NC16 NC15 NC14 NC13 NC12 NC11 NC10 NC9 NC8 NC7 NC6 NC5 NC4 NC3 NC2 NC1 38 5 4 3 M25 M9 M7 M8 M4 M3 M2 M1 L34 L33 L32 L31 L30 L28 L27 L26 L25 L10 L9 L8 L7 L6 L5 L4 L2 L1 K34 K33 K32 K31 K30 K29 K28 K27 K26 K25 K11 K7 K6 K5 K4 K3 K2 K1 J32 J31 J29 J28 J27 J26 J25 J24 J11 J10 J9 J8 J7 J6 J4 H32 H31 H30 H29 H28 H24 H21 H12 H11 H10 H9 H7 H6 G29 G28 G27 G24 G22 G15 G14 G10 G9 G8 G7 G6 F29 F28 F27 F26 F25 F24 F16 F15 F9 F8 F7 F6 F5 F4 E29 E28 E27 E25 E16 E14 E8 E7 E6 D27 D26 D9 D8 D7 C27 C26 C9 C8 C7 B29 B27 B8 2 2 AD24 AH21 AM9 AJ9 AK26 M19 U17 C18 AF33 AM15 AG27 L11 Y11 E5 T14 B26 L3 F20 B9 AM24 E26 M16 AD23 AC3 M6 L15 U29 AL26 M24 AA15 AM11 AM10 U20 AE10 AJ21 AE24 AH10 E30 AA19 V21 T21 W12 P17 W14 C15 L21 R16 AN9 AD14 L23 U10 AD20 AM18 W21 Y21 AK9 Y24 H8 AE11 M32 V20 M12 E33 B30 AA16 J33 Y16 AG10 K18 AF2 AF25 AK5 AD6 W15 V15 W20 M11 Y3 AM25 R6 B5 AJ22 AG25 AE25 R19 AJ26 AC29 J5 AC11 AM22 AJ19 AM17 L24 W19 AN30 R21 AA24 U21 Y29 P16 AL9 R15 T20 AJ14 A1 T17 F17 AC24 P15 V19 C12 R11 V25 AA20 U25 AJ17 ECP3-90-1156BGA GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VSS U1L GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND AF10 Y15 P29 U3 J2 J30 AP9 K17 Y19 P21 P3 AJ13 AM13 V10 AH24 P11 U14 AA17 Y17 AM26 U16 AA6 AC12 Y20 AJ11 AJ25 T15 AH14 AD21 P18 AA11 R17 AE17 AP34 AH18 AJ10 W18 AK33 AA14 V17 AA32 AH11 AN5 R32 V6 AG8 L20 C24 H27 AK2 AD11 V16 AF30 AC19 AA21 F23 AJ16 P24 AM20 AJ24 AN26 AM12 AM19 C21 T12 M23 L29 E9 AE18 V14 T18 AJ18 AM23 W16 W17 AD32 E2 P14 V18 AM16 P20 AP1 R14 R24 AD15 AM14 U18 U19 P19 AA18 AP26 L12 Y18 U15 AD12 T16 T23 L14 AJ20 AH17 T19 A34 AJ12 R18 R20 AH25 AK30 Y14 AM21 AF5 V32 AJ23 AC23 AJ15 F14 AC16 F11 Date: Size C Title 1 Wednesday, August 26, 2009 Sheet ECP3 SPB Eval Board Project VSS/Decoupling 14 of 15 Rev 3.0 1605 Valley Center Parkway Bethlehem, PA 18017 1 A B C D Lattice Semiconductor LatticeECP3 Serial Protocol Board – Revision D User’s Guide Figure 32. VSS/Decoupling Bank 0 SEGMENT A B C D E F G H K M N P R S T U DP ECP3-90-1156BGA VCCIO0 VCCIO0 VCCIO0 VCCIO0 M17 L13 M13 L17 C3 C4 B1 B2 E4 D4 B3 A2 D5 C6 B4 A3 D6 C5 A4 A5 B7 A7 B6 A6 A8 A9 A10 B10 J12 K12 C11 D11 G11 G12 A11 B11 K13 J13 E11 F12 F10 E10 A12 B12 J14 H13 D12 E12 K14 K15 E13 F13 G13 H14 A13 B13 D10 C10 C13 D13 J15 H15 D3 C2 C14 D14 A14 B14 G16 G17 D15 E15 J16 H16 A15 B15 E17 F18 C16 D16 K16 L16 A16 B16 G18 F19 C17 D17 J17 H17 BGA C30 C29 B31 A31 H25 H26 A30 A29 A27 A26 A28 B28 G25 G26 D25 C25 D28 2_5V 5 USB_0 USB_1 USB_2 USB_3 USB_4 USB_5 USB_6 USB_7 RS232_0 RS232_1 ETH_TX_CLK OSC_IN1 LA1 LA2 LA3 LA4 LA5 LA6 LA7 LA8 LA9 LA10 LA11 LA12 LA13 LA14 LA15 LA16 LA17 LA18 LA19 LA20 LA21 LA22 LA23 LA24 LA25 LA26 LA27 LA28 LA29 LA30 LA31 LA32 LA33 LA34 RS232_RXD RS232_TXD USB_TXD USB_DTR# USB_RTS# USB_RXD USB_RI# USB_DSR# USB_DCD# USB_CTS# OSC_IN2 TP_0 TP_1 TP_2 TP_3 TP_4 TP_5 TP_6 TP_7 TP_8 TP_9 TP_10 TP_11 TP_12 TP_13 TP_14 TP_15 FPGA_0 FPGA_1 FPGA_2 FPGA_3 FPGA_4 FPGA_5 FPGA_6 FPGA_7 FPGA_8 FPGA_9 FPGA_10 FPGA_11 FPGA_12 FPGA_13 FPGA_14 FPGA_15 8 1 14 9 16 SEG_K 13 12 11 10 9 SEG_E SEG_C SEG_B SEG_A 2 1 A LTP-587HR/16-SEGMENT RN3H RN3G RN3F 16 B 8 C 7 D 6 9 RN3E 13 RN3D E 5 4 F SEG_D 5 8 6 G RN3C H RN3B RN3A K 2 15 150R EXB2HV151JV 14 3 M SEG_F 4 3 RN2H RN2C RN2G 17 RN2B 15 RN2F 12 N SEG_G 7 RN2A 11 RN2E D20 18 L22 L18 M22 M18 A17 B17 E19 E20 A18 B18 J18 H18 D18 E18 G19 H19 A19 B19 K20 L19 C19 D19 J19 K19 A20 B20 G20 G21 C20 D20 F21 F22 A21 B21 D21 E21 H20 J20 A22 B22 J22 J23 C22 D22 J21 H22 A23 B23 E22 E23 C23 D23 K22 K21 A24 B24 G23 H23 D24 E24 K23 K24 A25 B25 C28 D28 C25 D25 G26 G25 B28 A28 A26 A27 A29 A30 H26 H25 A31 B31 C29 C30 SEG_DP SEG_U SEG_T SEG_S SEG_R SEG_P SEG_N SEG_M SEG_K SEG_H SEG_G SEG_F SEG_E SEG_D SEG_C SEG_B SEG_A I2C_SDA I2C_SCL GSRN CDC_CTRL_LE CDC_CTRL_CLK CDC_CTRL_DATA PCIE_PERSTN 9 9 9 9 4 PHY_NET[0..5] ETH_RX_D[0..7] ETH_GTX_CLK ETH_TX_D[0..7] ETH_CRS ETH_COL ETH_RX_CLK 9 9 9 9 9 9 9 10NF-0603SMT C335 OSC_IN1 OSC_IN2 OSC_IN3 CLOCK_CTRL_SEL0 CLOCK_CTRL_SEL1 8 1_6R-0603SMT C395 R260 + 10NF-0603SMT C338 C340 NC PP10 Q Q_N 5 4 3 FPGA CLOCK 2 DIS# SP26 T25 T24 N24 U23 N23 U24 N30 N29 N26 P26 N32 N31 N27 N28 N34 N33 P28 P27 P32 P31 P30 R29 P34 P33 R28 R27 R31 R30 R26 R25 R34 R33 T29 T28 T32 T31 T26 T27 T34 T33 T30 U30 U32 U31 U26 U27 U34 U33 V34 V33 J44 HEADER 2 HD2x1 DI VTT2 VTT2 Y5 CW-P423-DNP 10NF-0603SMT 1 10NF-0603SMT C339 15 1_5V Bank 2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 PR17A/RDQ22 PR17B/RDQ22 PR19A/RDQ22/HS19 PR19B/RDQ22/HS19 PR20A/RDQ22 PR20B/RDQ22 PR22A/RDQS22 PR22B/RDQS22# PR23A/RDQ22 PR23B/RDQ22 PR25A/RDQ22/HS25 PR25B/RDQ22/HS25 PR25E_A/RUM2_GPLLT_FB_A/RDQ22 PR25E_B/RUM2_GPLLT_FB_B/RDQ22 PR25E_C/RUM2_GPLLT_IN_A/RDQ22 PR25E_D/RUM2_GPLLT_IN_B/RDQ22 PR26A/RDQ31 PR26B/RDQ31 PR28A/RDQ31/HS28 PR28B/RDQ31/HS28 PR29A/RDQ31 PR29B/RDQ31 PR31A/RDQS31 PR31B/RDQS31# PR32A/RDQ31 PR32B/RDQ31 PR34A/VREF1_2/RDQ31/HS34 PR34B/VREF2_2/RDQ31/HS34 PR35A/RDQ40 PR35B/RDQ40 PR37A/RUM0_GDLLT_IN_A/RDQ40/HS37 PR37B/RUM0_GDLLT_IN_B/RDQ40/HS37 PR38A/RUM0_GDLLT_FB_A/RDQ40 PR38B/RUM0_GDLLT_FB_B/RDQ40 PR40A/RDQS40 PR40B/RDQS40# PR41A/RDQ40 PR41B/RDQ40 PR43A/PCLKT2_0/RDQ40/HS43 PR43B/PCLKC2_0/RDQ40/HS43 PR43E_A/RUM0_GPLLT_FB_A/RDQ40 PR43E_B/RUM0_GPLLT_FB_B/RDQ40 PR43E_C/RUM0_GPLLT_IN_A/RDQ40 PR43E_D/RUM0_GPLLT_IN_B/RDQ40 ECP3-90-1156BGA U1C BANK2 OSC_IN[1..3] 2_5V 10NF-0603SMT C337 3_3V 10NF-0603SMT C336 6,7 6,7 I2C_SDA 3 I2C_SCL 3 GSRN 3,5,6 CDC_CTRL_LE 8 CDC_CTRL_CLK 8 CDC_CTRL_DATA 8 PCIE_PERSTN 7 1 R235 2 CDC_REFCLKCDC_REFCLK 22R-0603SMT PHY_NET0 PHY_NET1 PHY_NET2 PHY_NET3 PHY_NET4 PHY_NET5 CDC_REFCLK_i ETH_RX_D1 ETH_RX_D2 ETH_RX_D3 ETH_RX_D4 ETH_RX_D5 ETH_RX_D6 ETH_RX_D7 PHY_MDIO PHY_MDC PHY_RESET_N PHY_INT_N PHY_FREQ_SEL PHY_CLK25 ETH_GTX_CLK ETH_TX_D0 ETH_TX_D1 ETH_TX_D2 ETH_TX_D3 ETH_TX_D4 ETH_TX_D5 ETH_TX_D6 ETH_TX_D7 ETH_TX_EN ETH_TX_ER ETH_TX_EN ETH_RX_ER ETH_TX_ER ETH_RX_ER ETH_RX_DV ETH_RX_DV ETH_RX_D0 ETH_CRS ETH_COL ETH_RX_CLK 16-SEGMENT DISPLAY 3_3V ECP3-90-1156BGA Bank 1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 PT74A PT74B PT76A/PCLKT1_0 PT76B/PCLKC1_0 PT77A PT77B PT79A PT79B PT80A PT80B PT82A PT82B PT83A PT83B PT85A PT85B PT86A PT86B PT88A PT88B PT89A PT89B PT91A PT91B PT95A PT95B PT97A PT97B PT98A PT98B PT101A PT101B PT103A PT103B PT104A PT104B PT106A PT106B PT107A PT107B PT109A PT109B PT110A PT110B PT112A PT112B PT113A PT113B PT115A PT115B PT116A PT116B PT118A PT118B PT119A PT119B PT121A PT121B PT122A PT122B PT124A PT124B PT125A PT125B PT127A PT127B PT128A PT128B PT130A PT130B PT131A PT131B PT133A PT133B PT134A PT134B PT136A/VREF1_1 PT136B/VREF2_1 P SEG_H 7 10 SEG_N SEG_M 10 RN2D 14 15 6 R 3 2 15 6 11 SEG_P R232 150R-0603SMT 4 13 EXB2HV151JV 5 12 150R 1 16 9 15 17 17 SEG_R SEG_S SEG_T SEG_U SEG_DP ETH_TX_CLK LA[1..34] RS232_[0..1] USB_[0..7] TP_[0..15] FPGA_[0..15] S A B C D PT2A PT2B PT5A PT5B PT7A PT7B PT8A PT8B PT10A PT10B PT11A PT11B PT13A PT13B PT14A PT14B PT16A PT16B PT17A PT17B PT19A PT19B PT20A PT20B PT22A PT22B PT23A PT23B PT25A PT25B PT26A PT26B PT28A PT28B PT29A PT29B PT31A PT31B PT32A PT32B PT34A PT34B PT35A PT35B PT37A PT37B PT38A PT38B PT40A PT40B PT41A PT41B PT43A PT43B PT44A PT44B PT46A PT46B PT4A/VREF1_0 PT4B/VREF2_0 PT50A PT50B PT56A PT56B PT58A PT58B PT59A PT59B PT61A PT61B PT62A PT62B PT64A PT64B PT65A PT65B PT67A PT67B PT68A PT68B PT70A PT70B PT71A PT71B PT73A/PCLKT0_0 PT73B/PCLKC0_0 U1A C394 U1B 100NF-0603SMT BANK1 C396 R337 15 SMA 1 J45 1 C407 C408 C325 C326 + C327 GP_CLKP R263 82R-0603SMT GP_CLKN 3_3V 82R-0603SMT R264 NOTE: PLACE TERMINATIONS CLOSE TO U1 DEVICE. R262 130R-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT C324 DP3 DQS# C414 VCCIO2 2 3 4 5 10NF-0603SMT 100NF-0603SMT C413 3 TP39 TP40 C328 C323 100NF-0603SMT 10NF-0603SMT 10NF-0603SMT C321 C322 51R-0603SMT FPGA_IN SP25 OSC_IN3 DQS DQ_TEST 10NF-0603SMT 10NF-0603SMT 100NF-0603SMT C406 R261 130R-0603SMT 1 VTT2 DQ_TEST DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQS DQS# DQ6 DQ7 VREF1_2 OSC_IN3 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQS DQS# DQ6 DQ7 DQ_TEST 50-OHM TRACES 1 BANK0 100NF-0603SMT 2 2 2 1UF-16V-0805SMT 3 22UF-16V-TANTBSMT 4 10UF-16V-TANTBSMT 2 1 6 BANK3 ECP3-90-1156BGA Bank 3 VTT3 VTT3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 PR44A PR44B PR46A/PCLKT3_0 PR46B/PCLKC3_0 PR47A PR47B PR49A PR49B PR50A PR50B PR52A/VREF1_3 PR52B/VREF2_3 PR53A PR53B PR55A PR55B PR56A PR56B PR58A PR58B PR59A PR59B PR61A PR61B PR61E_A/RLM1_GPLLT_FB_A PR61E_B/RLM1_GPLLT_FB_B PR61E_C/RLM1_GPLLT_IN_A PR61E_D/RLM1_GPLLT_IN_B PR62A PR62B PR64A/HS64 PR64B/HS64 PR65A PR65B PR67A PR67B PR68A PR68B PR70A/HS70 PR70B/HS70 PR70E_A/RLM2_GPLLT_FB_A PR70E_B/RLM2_GPLLT_FB_B PR70E_C/RLM2_GPLLT_IN_A PR70E_D/RLM2_GPLLT_IN_B PR71A PR71B PR74A PR74B PR77A PR77B PR79E_A/RLM3_GPLLT_FB_A PR79E_B/RLM3_GPLLT_FB_B PR79E_C/RLM3_GPLLT_IN_A PR79E_D/RLM3_GPLLT_IN_B PR80A PR80B PR82A/HS82 PR82B/HS82 PR83A PR83B PR85A PR85B PR86A PR86B PR88A/HS88 PR88B/HS88 PR89A PR89B PR91A/HS91 PR91B/HS91 PR92A PR92B PR94A PR94B PR95A PR95B PR97A/HS97 PR97B/HS97 PB131A PB131B PB133A PB133B PB134A PB134B PB136A PB136B PB137A PB137B PB139A PB139B PB140A PB140B PB142A PB142B PB143A PB143B PB145A PB145B U1D Date: Size C Title W25 W24 AB23 AB24 V24 V23 R237 0R-0603SMT LVDS_OUTP_0 LVDS_OUTN_0 GP_CLKP GP_CLKN LVDS_OUTP_1 LVDS_OUTN_1 LED1 LED2 LED3 LED4 LED5 LED6 LED7 LED8 SWITCH1 SWITCH2 SWITCH3 SWITCH4 SWITCH5 SWITCH6 SWITCH7 SWITCH8 FPGA_SMA_P FPGA_SMA_N DP1 DP2 C330 1 3 SMA 1 LVDS_OUTN_0 10NF-0603SMT C333 C334 10NF-0603SMT Wednesday, August 26, 2009 1 Sheet 14 of 17 2 3 4 5 2 3 4 5 Rev 3.0 1605 Valley Center Parkway Bethlehem, PA 18017 10NF-0603SMT C332 J39 SMA LVDS_OUTN_1 2_5V C331 3 R234 100R-0603SMT 1 R233 100R-0603SMT J38 1 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT C329 LVDS_OUTP_0 LVDS_OUTP_1 CDC_Y2_OUT 8 CDC_Y2B_OUT 8 R230 51R-0603SMT 15 15 CDC_Y1_OUT 8 CDC_Y1B_OUT 8 SWITCH[1..8] LED[1..8] FPGA_SMA_N 51R-0603SMT R231 FPGA_SMA_P ECP3 SPB Eval Board Project FPGA Pins V31 V30 U28 V28 W34 W33 V27 V26 W32 W31 V29 W28 W30 W29 W27 W26 Y34 Y33 Y30 AA29 Y32 Y31 Y26 Y25 AA34 AA33 Y28 Y27 AB34 AB33 AA25 AA26 AA31 AA30 AB30 AC30 AC34 AC33 AA28 AA27 AC32 AC31 AB28 AB29 AE32 AE31 AE30 AE29 AF32 AF31 AM34 AM33 AJ34 AK34 AN34 AN33 AH33 AJ33 AP33 AP32 AL34 AL33 AL32 AK32 AJ31 AK31 AN32 AM32 AL30 AM30 AP31 AN31 AP29 AP30 AL31 AM31 AM29 AN29 AP28 AN28 AP27 AN27 AM27 AL27 AH26 AG26 AM28 AL28 AK27 AJ27 AK28 AJ28 AH27 AH28 AL29 AK29 AF26 AE26 1 2 5 T VCC U GND DP 3 1 2 39 2 A B C D Lattice Semiconductor LatticeECP3 Serial Protocol Board – Revision D User’s Guide Figure 33. FPGA Pins 40 5 USB_RI# USB_DSR# USB_DCD# USB_CTS# USB_3 USB_4 USB_5 USB_6 USB_7 4 C402 3_3V 10NF-0603SMT C403 3 11 USB_DCD# USB_CTS# 14 13 12 9 10 USB_DSR# 8 7 6 5 4 2 USB_DTR# USB_RTS# USB_RXD 100NF-0603SMT USB_RI# C404 1 USB_TXD FT232R GPIO3 GPIO2 SLEEP# CTS# DCD# DSR# NC_1 GND RI# RXD VCCIO RTS# DTR# TXD U30 3_3V C400 100NFX5R-0402SMT 0402 C401 100NF-0603SMT 3 USBDP USBDM 3V3OUT GND RESET# VCC GND GPIO0 GPIO1 NC_2 AGND TEST OSCI OSCO 16 12 9 USB_P CB1 CB0 R332 4_7K-0603SMT R331 10K-0603SMT RS232_RXD 15 15 14 7 100NF-0603SMT USB_N C405 3_3V CB1 CB0 GND T1OUT T2OUT R1OUT R2OUT 16 17 18 19 20 21 22 23 24 25 26 27 28 MAX3232 TSSOP16 VCC C1+ C1C2+ C2V+ V- T1IN T2IN R1IN R2IN U29 J43 1 2 3 4 5 INDUCTOR L3 1 2 3 4 5 2 1 1 330R-0402SMT GREEN_LED R330 GREEN_LED R329 1 2 1 330R-0402SMT D32 D31 HEADER 5X2 2 2 2 RS232 Title Misc. 1605 Valley Center Parkway Bethlehem, PA 18017 C D Date: Size C 1 Wednesday, August 26, 2009 Sheet ECP3 SPB Eval Board Project 17 of 17 Rev 3.0 A USB_RXD USB_2 C399 100NFX5R-0402SMT 0402 1 3 4 5 2 6 11 10 13 8 2 4 6 8 10 1 A USB_[0..7] USB_RTS# USB_1 RS232_TXD RS232_1 J42 1 3 5 7 9 2 B 14 USB_TXD USB_DTR# USB_0 RS232_RXD RS232_0 C397 100NFX5R-0402SMT C398 0402 100NFX5R-0402SMT 0402 14 RS232_[0..1] 1UF-16V-0805SMT 3 8 B C 4 USB_MINI_AB D 5 9 9 6 6 8 7 7 Lattice Semiconductor LatticeECP3 Serial Protocol Board – Revision D User’s Guide Figure 34. Miscellaneous LatticeECP3 Serial Protocol Board – Revision D User’s Guide Lattice Semiconductor Appendix B. Bill of Materials Table 27. Bill of Materials Item Quantity Reference Part Manufacturer Molex Part Number 67800-1005/ DK#WM19023-ND Description 1 2 CN1,CN2 SATA CONN HEADER 7POS VERT SMD 15GOLD 2 1 CN3 PCI Express x4 Edge Finger Conn. 3 1 C1 470UF-FKSMT Panasonic EEV-FK1V471Q CAP 470UF 35V ELECT FK SMD 4 5 C2,C199,C211,C233,C280 100UF-FKSMT Panasonic EEE-FK1V101XP CAP 100UF 35V ELECT FK SMD 5 6 C3,C6,C9,C12,C14,C15 330UF-FKSMT Panasonic EEE-FK1C331P CAP 330UF 16V ELECT FK SMD 6 16 C4,C5,C7,C8,C10,C11,C13,C132,C135,C1 56,C162,C201,C213,C234,C282,C395 10UF-16V-TANTBSMT AVX TAJB106K016R CAP TANTALUM 10UF 16V 10% SMD 7 121 C16,C19,C21,C31,C33,C35,C37,C39,C41, 100NF-0603SMT C49,C51,C53,C55,C57,C59,C63,C65,C67, C69,C70,C71,C72,C73,C74,C75,C76,C77, C78,C81,C82,C83,C84,C99,C102,C104,C1 05,C106,C107,C108,C109,C111,C113,C11 5,C117,C118,C119,C129,C130,C131,C133, C136,C137,C148,C149,C153,C157,C163,C 169,C171,C175,C176,C178,C180,C190,C1 92,C194,C196,C198,C202,C204,C206,C20 8,C210,C215,C217,C219,C223,C225,C227, C228,C230,C232,C239,C240,C242,C245,C 250,C253,C254,C257,C259,C261,C264,C2 66,C268,C270,C272,C274,C275,C277,C27 9,C286,C287,C290,C292,C294,C300,C302, C304,C305,C307,C310,C312,C314,C316,C 318,C320,C343,C344,C394,C396 Panasonic ECJ-1VF1C104Z CAP .1UF 16V CERAMIC Y5V 0603 8 21 C17,C25,C27,C29,C43,C45,C47,C61,C79, 22UF-16V-TANTBSMT C101,C154,C155,C161,C172,C237,C246,C 255,C283,C296,C327,C341 Kemet T491B226M016AT 9 27 C18,C26,C28,C30,C44,C46,C48,C62,C80, 1UF-16V-0805SMT C100,C168,C173,C191,C200,C203,C212,C 229,C235,C238,C247,C256,C276,C281,C2 84,C297,C328,C342 Panasonic ECJ-2FB1C105K CAP 1UF 16V CERAMIC 0805 X5R 10 113 C20,C22,C32,C34,C36,C38,C40,C42,C50, 10NF-0603SMT C52,C54,C56,C58,C60,C64,C66,C68,C85, C86,C87,C88,C89,C90,C91,C92,C93,C94, C95,C96,C97,C98,C103,C110,C112,C114, C116,C127,C134,C146,C147,C170,C177,C 179,C181,C182,C183,C184,C195,C197,C2 07,C209,C214,C216,C218,C222,C224,C22 6,C236,C241,C243,C244,C248,C249,C251, C252,C258,C260,C262,C263,C265,C267,C 269,C271,C273,C285,C288,C289,C291,C2 93,C295,C298,C299,C301,C303,C306,C30 8,C309,C311,C313,C315,C317,C319,C321, C322,C323,C324,C325,C326,C329,C330,C 331,C332,C333,C334,C335,C336,C337,C3 38,C339,C340,C345,C392,C393 Kemet C0603C103K5RACTU CAP .01UF 50V CERAMIC X7R 0603 11 1 C23 2200PF-0402SMT AVX 0402YC223KAT2A CAP CERM .022UF 10% 16V X7R 0402 12 1 C24 100NF-0402SMT Yageo 04022F104Z7B20D CAP .10UF 16V CERAMIC Y5V 0402 13 19 C120,C121,C122,C123,C124,C125,C126,C 10NF-0402SMT 128,C150,C152,C159,C160,C165,C166,C1 85,C186,C187,C188,C189 Panasonic ECJ0EB1E103K CAP .01UF 25V CERAMIC X7R 0402 14 8 C138,C139,C140,C141,C142,C143,C144,C 100NFX5R-0402SMT 145 Kemet C0402C104K8PACTU CAP .10UF 10V CERAMIC X5R 0402 15 1 C151 100PF-0402SMT AVX 04026C101KAT2A CAP CER 100PF 6.3V X7R 0402 16 2 C158,C164 33NF-0402SMT AVX 0402YD333KAT2A CAP CERM .033UF 10% 16V X5R 0402 17 5 C167,C193,C205,C231,C278 47UF-10V-TANTBSMT Kemet B45196H2476K209 CAP TANTALUM 47UF 10V 10% SMD 18 1 C174 220NF-0603SMT AVX 06036C224KAT2A CAP CER .22UF 6.3V X7R 0603 19 46 C346,C347,C348,C349,C350,C351,C352,C 1000PF-0402SMT 353,C354,C355,C356,C357,C358,C359,C3 60,C361,C362,C363,C364,C365,C366,C36 7,C368,C369,C370,C371,C372,C373,C374, C375,C376,C377,C378,C379,C380,C381,C 382,C383,C384,C385,C386,C387,C388,C3 89,C390,C391 Panasonic ECJ-0EB1E102K CAP 1000PF 25V CERAMIC X7R 0402 20 2 DP1,DP2 DIFFTESTPOINT 21 11 D1,D2,D3,D4,D5,D6,D7,D11,D12,D25,D26 LED-SMT1206_GREEN Panasonic LNJ316C83RA LED GREEN (UP) W/LENS 1206 PCB Edge finger Alt: CC0402ZRY5V7BB104 Alt: ECJ-0EB1E101K Alt: 0603ZC224KAT2A 41 LatticeECP3 Serial Protocol Board – Revision D User’s Guide Lattice Semiconductor Table 27. Bill of Materials (Continued) Item Quantity Reference Part Manufacturer Part Number Description 22 5 D8,D9,D10,D21,D22 LED-SMT1206_RED Panasonic LNJ211R82RA LED RED (UP) W/LENS 1206 23 6 D13,D14,D15,D16,D17,D19 AMBER_LED Lite-On LTST-C190AKT LED AMBER CLEAR 0603 SMD 24 1 D18 GREEN_LED Lite-On LTST-C190GKT LED GREEN CLEAR 0603 SMD 25 1 D20 LTP-587HR/16-SEGMENT Lite-On LTP-587HR 16-segment array 26 2 D23,D24 LED-SMT1206_YELLOW Panasonic LNJ411K84RA LED YELLOW (UP) W/LENS 1206 27 2 D27,D28 LED-SMT1206_BLUE Panasonic LNJ916C8BRA LED BLUE (UP) W/LENS 1206 28 6 FB1,FB2,FB3,FB7,FB8,FB9 BLM41PG600SN1(NOB) 29 13 FB4,FB5,FB6,FB10,FB11,FB12,FB13,FB14 BLM41PG600SN1 ,FB15,FB16,,FB18,FB19,FB20, Murata BLM41PG600SN1L FERRITE CHIP 60 OHM 6000MA 1806 30 2 F1, F3 F1251CT-ND Littlefuse þ FUSEBLOCK WITH 10A FUSE SMD 31 5 F2,F4,F5,F6,F7 F1228CT-ND Littlefuse 0154005.DR FUSEBLOCK WITH 5A FUSE SMD 32 1 J1 22HP037-2.1mm Condor 22HP037A power input 33 4 J2,J3,J10,J11 HEADER 2 Samtec TSW-102-07-T-S 2x1-0.25 Header 34 1 J4 ( SEE ECN FOR Placement ) HEADER 17X2 Samtec TSW-117-07-T-D 17x2-0.25 Header 35 2 J5,J6 HEADER 3 Samtec TSW-103-07-T-S 3x1-0.25 Header 36 2 J7,J8 HEADER 2X2 Samtec TSW-102-07-T-D 2x2-0.25 Header 37 2 J9,J12 HEADER 10 Samtec TSW-110-07-T-S 10x1-0.25 Header 38 16 J13,J14,J15,J16,J17,J18,J19,J20,J21,J22,J Rosenberger 32K153-400E3 Rosenberger 23,J24,J25,J26,J27,J28 32K153-400E3 TH- SMA connector Alt 32K153-400L5 39 10 J29,J30,J31,J32,J33,J34,J35,J36,J38,J39 SMA Molex 73391-0060 CONN JACK SMA STR 50 OHM PCB 40 1 J37 RJ-45 Bel Fuse L-829-1J1T-43 Integrated RJ45 Connector 41 1 J40 HEADER 9X2 Samtec TSW-109-07-T-D 9x2-0.25 Header 42 1 LA1 2_767004 Amp 2-767004-2 CONN RECEPT 38POS .025 VERT SMD 43 7 LP1,LP2,LP3,LP4,LP5,LP6,LP7 5016 Keystone Electronics 5016 TEST POINT PC COMPACT SMT 44 2 L1,L2 75 OHM @ 100MHZ Murata BLM18BA750SN1D 45 2 MH1,MH2 MHOLE_1 46 3 MH3,MH4,MH5 M HOLE2 47 10 PP1,PP2,PP3,PP4,PP5,PP7,PP8,PP9,PP1 0,PP11 PROBEPOINT 48 1 Q1 NTMS4503 ON Semiconductor NTMS4503NR2G MOSFET N-CH 28V 14A 8SOIC 49 6 Q2,Q3,Q4,Q5,Q6,Q7 2N2222/SOT23 Diodes Inc MMBT2222A-7 TRANS NPN 40V 350MW SMD SOT-23 50 1 RN1 EXBV8V472JV Panasonic EXBV8V472JV RES ARRAY 4.7K OHM 5% 4 RES SMD 51 2 RN2,RN3 EXB2HV151JV Panasonic EXB2HV151JV RES ARRAY 150 OHM 5% 8 RES SMD 52 1 RN4 EXB2HV472JV Panasonic EXB2HV472JV RES ARRAY 4.7K OHM 5% 8 RES SMD 54 1 RN6 EXB2HV471JV Panasonic EXB2HV471JV RES ARRAY 470 OHM 5% 8 RES SMD 55 4 RP1,RP2,RP3,RP4 CTS-RT1402B7 CTS Corporation Resistor/ Electrocomponents RT2402B7 RES NET DDR SDRAM 50 OHM 3X9 BGA 56 1 R1 470R-1206SMT Panasonic ERJ-8GEYJ471V RES 470 OHM 1/4W 5% 1206 SMD 57 4 R2,R12,R13,R14 100R-0805SMT Panasonic ERJ-6GEYJ101V RES 100 OHM 1/8W 5% 0805 SMD 58 20 R3,R4,R24,R25,R80,R207,R209,R211,R21 0R-0603SMT 5,R217,R222,R227,R236,R237,R249,R254, R258,R259,R265,R266 Panasonic ERJ-3GEY0R00V RES ZERO OHM 1/10W 5% 0603 SMD 59 1 R6 1_13K-0603SMT Panasonic ERJ-3EKF1131V RES 1.13K OHM 1/10W 1% 0603 SMD 60 0 50R-0603SMT Vishay FC0603E50R0BTBT1 RES 50 OHM 125MW .1% 0603 SMD 61 2 53 R7,R8 OPEN-0805SMT 42 LatticeECP3 Serial Protocol Board – Revision D User’s Guide Lattice Semiconductor Table 27. Bill of Materials (Continued) Item Quantity Reference Part Manufacturer Part Number Description 62 47 R70,R71,R79,R85,R86,R103,R104,R116,R OPEN-0603SMT 118,R121,R122,R125,R126,R127,R128,R1 29,R130,R131,R132,R133,R134,R135,R21 4,R220,R226,R250,R251,R267,R268,R270, R271,R272,R310.R311,R312,R315,R316,R 317,R318,R319,R320,R321,R322,R323,R3 24,R325,R326 63 1 R10 12_1K-0603SMT Susumu Co Ltd RG1608P-1212-B-T5 RES 12.1K OHM 1/10W .1% 0603 SMD 64 4 R11,R19,R37,R43 2K-0603SMT Panasonic ERJ-3EKF2001V RES 2.00K OHM 1/10W 1% 0603 SMD 65 1 R15 806R-0603SMT Panasonic ERJ-3EKF8060V RES 806 OHM 1/10W 1% 0603 SMD 66 0 R16 49_9R-0603SMT Yageo RC0603FR-0749R9L RES 49.9 OHM 1/10W 1% 0603 SMD 67 5 R34,R77,R78,R233,R234 100R-0603SMT Panasonic ERA-3YEB101V RES 100 OHM 1/16W .1% 0603 SMD 68 0 R18 66_5R-0603SMT Vishay CRCW060366R5FKEA RES 66.5 OHM 1/10W 1% 0603 SMD 69 21 R9,R21,R22,R23,R52,R57,R58,R59,R60,R 10K-0603SMT 61,R62,R63,R64,R65,R66,R68,R73,R75,R7 6,R81,R314 Panasonic ERJ-3GEYJ103V RES 10K OHM 1/10W 5% 0603 SMD 70 1 R26 200R-0402SMT Panasonic ERJ-2RKF2000X RES 200 OHM 1/16W 1% 0402 SMD 71 17 R27,R28,R29,R30,R31,R32,R33,R36,R39, R42,R44,R46,R49,R51,R140,R142,R147 10K-0402SMT Panasonic ERJ-2RKF1002X RES 10.0K OHM 1/16W 1% 0402 SMD 72 6 R35,R38,R41,R45,R48,R50 330R-0402SMT Panasonic ERJ-2GEJ331X RES 330 OHM 1/16W 5% 0402 SMD 73 19 R5,R18,R16,R17,R40,R47,R83,R84,R212, 1K-0603SMT R216,R219,R223,R224,R228,R229,R246,R 247,R252,R253 Panasonic ERJ-3EKF1001V RES 1.00K OHM 1/16W 1% 0603 SMD 74 3 R53,R54,R55 680R-0603SMT Panasonic ERJ-3GEYJ681V RES 680 OHM 1/10W 5% 0603 SMD 75 6 R56,R74,R162,R166,R173,R177 220R-0603SMT Panasonic ERJ-3GEYJ221V RES 220 OHM 1/10W 5% 0603 SMD 76 7 R67,R69,R72,R206,R208,R210,R218 4_7K-0603SMT Panasonic ERJ-3GEYJ472V RES 4.7K OHM 1/10W 5% 0603 SMD 77 1 R82 2_2K-0603SMT Panasonic ERJ-3GEYJ222V RES 2.2K OHM 1/10W 5% 0603 SMD 78 10 R87,R88,R101,R102,R105,R109,R115,R11 130R-0603SMT 9,R261,R262 Panasonic ERA-3YEB131V RES 130 OHM 1/16W .1% 0603 SMD 79 6 R89,R90,R108,R110,R230,R231 51R-0603SMT Panasonic ERJ-3GEYJ510V RES 51 OHM 1/10W 5% 0603 SMD 80 7 R91,R92,R96,R97,R138,R139,R232 150R-0603SMT Panasonic ERA-3YEB151V RES 150 OHM 1/16W .1% 0603 SMD 81 10 R93,R94,R106,R107,R111,R112,R123,R12 82R-0603SMT 4,R263,R264 Yageo RC0603FR-0782RL RES 82.0 OHM 1/10W 1% 0603 SMD 82 2 R95,R114 1_62K-0603SMT Panasonic ERJ-3EKF1621V RES 1.62K OHM 1/10W 1% 0603 SMD 83 2 R98,R117 3_4K-0603SMT Panasonic ERJ-3EKF3401V RES 3.4K OHM 1/10W 1% 0603 SMD 84 2 R99,R120 2_8K-0603SMT Panasonic ERJ-3EKF2801V RES 2.8K OHM 1/10W 1% 0603 SMD 85 3 R100,R113,R260 1_6R-0603SMT Panasonic ERJ-3GEYJ1R6V RESISTOR 1.6 OHM 1/10W 5% 0603 86 2 R141,R148 130R-0402SMT Panasonic ERJ-2RKF1300X RES 130 OHM 1/16W 1% 0402 SMD 87 1 R143 160R-0402SMT Panasonic ERJ-2RKF1600X RES 160 OHM 1/16W 1% 0402 SMD 88 1 R144 12K-0402SMT Rohm MCR01MZPF1202 RES 12.0K OHM 1/16W 1% 0402 SMD 89 2 R145,R149 82R-0402SMT Panasonic ERJ-2RKF82R0X RES 82 OHM 1/16W 1% 0402 SMD 90 1 R146 OPEN-0402SMT 91 3 R150,R151,R154 750R-0402SMT Panasonic ERJ-2RKF7500X RES 750 OHM 1/16W 1% 0402 SMD 92 8 R152,R153,R156,R157,R158,R159,R160,R 150R-0402SMT 161 Panasonic ERJ-2RKF1500X RES 150 OHM 1/16W 1% 0402 SMD 93 5 R155,R204,R205,R300,R301 Panasonic ERJ-2RKF4701X RES 4.70K OHM 1/16.0W 1% 0402 SM Alt: RC0603FR-0749R9L Alt: RC0603FR-0782RL Alt: CRCW040282R0FKED 4_7K-0402SMT 43 LatticeECP3 Serial Protocol Board – Revision D User’s Guide Lattice Semiconductor Table 27. Bill of Materials (Continued) Item Quantity Reference 94 2 R163,R164 95 25 96 Part 220R-0402SMT Manufacturer Part Number Description Panasonic ERJ-2RKF2200X RES 220 OHM 1/16W 1% 0402 SMD R165,R167,R168,R169,R170,R171,R172,R 33R-0402SMT 174,R175,R176,R178,R179,R180,R181,R1 82,R183,R184,R185,R186,R188,R189,R19 0,R191,R201,R202 Panasonic ERJ-2GEJ330X RES 33 OHM 1/16W 5% 0402 SMD 1 R187 1_5K-0402SMT Panasonic ERJ-2RKF1501X RES 1.50K OHM 1/16W 1% 0402 SMD 97 1 R192 5K-0402SMT Panasonic ERJ-2RKF5001X RES 5K OHM 1/16W 1% 0402 SMD 98 8 R193,R194,R195,R196,R197,R198,R199,R 49_9R-0402SMT 200 Panasonic ERJ-2RKF49R9X RES 49.9 OHM 1/16W 1% 0402 SMD 99 5 R136,R137,R203,R235 22R-0603SMT Yageo RC0603FR-0722RL RES 22.0 OHM 1/10W 1% 0603 SMD 100 5 R213,R221,R225,R248,R255 1K_ADJ/SMT3MM BC Components ST3A102CT POT 1K 3MM CERM SQ S/T SMD 102 2 R256,R257 100R-0402SMT Panasonic ERJ-2GEJ101X RES 100 OHM 1/16W 5% 0402 SMD 103 24 SP1,SP2,SP3,SP4,SP5,SP6,SP7,SP8,SP9, TEST POINT SP10,SP11,SP12,SP13,SP14,SP15,SP16, SP17,SP18,SP19,SP20,SP21,SP22,SP23, SP24 104 2 SW1,SW3 SW PUSHBUTTON-SPST C&K Components EP11FPD SPST- Momentary RA SMT 105 1 SW2 SW DIP-3 CTS 194-3MST CTS Corporation Resistor/ Electrocomponents 194-3MST SWITCH SIDE ACTUATED GOLD 3 SEC 106 3 SW4,SW5,SW6 EVQ-P2H02B Panasonic EVQ-P2H02B SWITCH LT 4.7MMX3.5MM 250GF SMD 107 7 SW7,SW8,SW9,SW10,SW11,SW12,SW13 TDA DIP-8 ITT TDA08H0SK1 SWITCH DIP 8POS HALF PITCH SMT 108 1 SW14 SW DIP-8/SM C&K Components BPA08SB 8-POSITION DIP PACK 109 1 TB1 Terminal Block/ED1202DS On-Shore Tech. ED120/2DS TERMINAL BLOCK 5.08MM VERT 2POS 110 38 TP1,TP2,TP3,TP4,TP5,TP6,TP7,TP8,TP9,T TestPoint P10,TP11,TP12,TP13,TP14,TP15,TP16,TP 17,TP18,TP19,TP20,TP21,TP22,TP23,TP2 4,TP25,TP26,TP27,TP28,TP29,TP30,TP31, TP32,TP33,TP34,TP35,TP36,TP37,TP38 111 1 U1 LFE3-95E-#FN1156CES LATTICE SUPPLIED 112 1 U4 PTH12060W Texas Instruments PTH12060WAH TH MODULE PIP 12VIN 10A ADJ 10-TH 113 4 U3,U5,U6,U7 SC1592 Semtech SC1592IMTRT IC LDO ADJ REG 3A TO-2637 114 1 U8 24AA1025-ISM Microchip Technology 24AA1025-I/SM IC SRL EEPROM 1024K 1.8V 8SOIC 115 1 U9 MAX6692 Maxim MAX6692MSA IC TEMP SENSING I2C 116 1 U10 POWR1220AT8 LATTICE SUPPLIED 117 1 U11 M25P64-FLASH Macronix MX25L6405MC20G IC SRL FLASH 64MBIT 3V 16-SOP Wide(300MIL) 118 1 U12 MAX6817 Maxim MAX6817-EUT+T ±15kV ESD-Protected, Dual, CMOS Switch Debouncers 119 2 U13,U15 NC7WZ16-MACO6A/ Fairchild TinyLogic Fairchild NC7WZ16P6X IC BUFFER UHS DUAL SC70-6 120 1 U14 SN74LVC125A/SO14 Texas Instruments SN74LVC125AD IC QUAD BUS BUFFER GATE 14-SOIC 121 1 U16 S29GL064A Spansion S29GL064N90BFI040 48fBGA FLASH-VBN048 122 1 U17 LCMXO1200C-CSBGA132 LATTICE SUPPLIED 123 1 U18 MC100LVEL56 ON Semiconductor MC100LVEL56DW 3.3V ECL Dual Differential 2:1 Multiplexer 124 1 U19 CDC7005 Texas Instruments CDC7005-QFN Clock cleaner QFN package 125 1 U20 LT1963-ADJ Linear Tech LT1963ES8 IC REG LDO ADJ 1.5A LN 8SOIC 126 1 U21 88e1111 Marvell 88e1111-Bx-BAB-C000( Bx indicates any revision code) single-port Gigabit Ethernet(117TFBGA) 127 4 U22,U23,U24,U26 LP2996-SO8 National Semi LP2996M IC DDR TERMINATION REG 8SOIC 130 1 U28 CY2304-1 Cypress Semiconductor CY2304SC-1 zero delay buffer 131 1 VCXO1 TCO-2111 Epson-Toyocom TCO2111-245.76MHZ VCXO 13.9x9.8mm SMT Alt: ERJ-2RKF4991X 101 Alt: TCO-2111T 245.7600MHZ:RO 44 LatticeECP3 Serial Protocol Board – Revision D User’s Guide Lattice Semiconductor Table 27. Bill of Materials (Continued) Item Quantity Reference Part Manufacturer Part Number Description 132 1 Y1 CW-P423-156.25MHZ Connor-Winfield CW-P423F-156.25MHZ 5x7.5mm SMT Oscillator 156.25MHz 133 1 Y2 CW-P423-125.00MHZ Connor-Winfield CW-P423F-125.0MHZ 5x7.5mm SMT Oscillator 1525.0MHz 134 1 Y3 25MHz Epson Toyocom Corporation SG-636PCE 25.0000MC0:ROHS OSCILLATOR 25.0000MHZ SMD 10.5mm x 5.8mm 135 1 Y4 CTS-CB3LV-3C -100.00MHZ-50ppm CTS-Frequency Controls CB3LV-3C-100M0000-T 136 DNP Y5 137 1 U2 PTH12060L Texas Instruments PTH12060LAH TH MODULE PIP 12VIN 10A ADJ 10-TH(0.8v-1.8v) 138 2 D29,D30 MMBZ5221BLT1 On-Semi MMBZ5221BLT1 Zener Voltage Regulators 225 mW SOT?23 Surface Mount 139 0 Q20 MMBT3906 Diodes Inc MMBT3906-7-F TRANS PNP 40V 300MW SMD SOT23 140 1 R20 464R-0603SMT Panasonic ERJ-3EKF4640V RES 464 OHM 1/10W 1% 0603 SMD 141 A/R Socket ISI HLS-341156-B-10 142 1 R269 ERJ-3EKF4531V Panasonic ERJ-3EKF4531V 143 0 FB17 , FB21 CRCW12100000ZSTA Vishay 144 2 R327,R328 0R-2010SMT Vishay/Dale CRCW20100000Z0EF RES 0.0 OHM1/2W 5% 2010 SMD 145 1 J42 HEADER2X5 Samtec TSW-105-07-T-D 5x2-0.25 Header 146 1 U29 MAX3232 Texas Instruments MAX3232IPWR IC DRVR/RCVR MLTCH RS232 16TSSOP 147 4 C397, C398, C399, C400 100NFX5R-0402SMT Kemet C0402C104K8PACTU CAP .10UF 10V CERAMIC X5R 0402 148 1 U30 FT232 Future Technology Devices International Ltd FTDI_FT232RL USB Serial Converter SSOP28 149 1 C402 1UF-16V-0805SMT Panasonic ECJ-2FB1C105K CAP 1UF 16V CERAMIC 0805 X5R 150 2 C403,C407 10NF-0603SMT Kemet C0603C103K5RACTU CAP .01UF 50V CERAMIC X7R 0603 151 2 C404, C405 100NF-0603SMT Panasonic ECJ-1VF1C104Z CAP .1UF 16V CERAMIC Y5V 0603 152 1 R331 10K-0603SMT Panasonic ERJ-3GEYJ103V RES 10K OHM 1/10W 5% 0603 SMD 153 1 J43 USB MINI AB MOLEX MOLEX_56579-0576 154 1 L3 INDUCTOR Panasonic Inductor 1uH 10% 230mA 1210 (Digikey PCD1008CT-ND) ELJ-FA1R0KF2 155 2 TP39, TP40 TestPoint 156 1 J45 SMA Molex 73391-0060 CONN JACK SMA STR 50 OHM PCB 157 1 R337 50R-0603SMT Vishay FC0603E50R0BTBT1 RES 50 OHM 125MW .1% 0603 SMD 158 2 C406, C408 1K-0603 Kemet C0603C103K5RACTU CAP .01UF 50V CERAMIC X7R 0603 159 1 C401 100NF-0603SMT Panasonic ECJ-1VF1C104Z CAP .1UF 16V CERAMIC Y5V 0603 160 2 SP25, SP26 TestPoint 161 1 DP3 DIFFTESTPOINT 162 2 D31, D32 GREEN_LED Lite-On LTST-C190GKT 163 2 R329, R330 330R-0402SMT Panasonic ERJ-2GEJ331X RES 330 OHM 1/16W 5% 0402 SMD 164 1 J41 HEADER3X2 Samtec TSW-103-07-T-D 3x2-0.25 Header 165 1 J44 HEADER 2 Samtec TSW-102-07-T-S 2x1-0.25 Header 166 4 R353,R354,R355,R356 1K-0603SMT Panasonic ERJ-3EKF1001V RES 1.00K OHM 1/16W 1% 0603 SMD 167 2 R338, R339 62R-0603SMT Panasonic ERJ-3GEYJ620V RES 62 OHM 1/10W 5% 0603 SMD 168 3 R340,R341,R342 100R-0402SMT Panasonic ERJ-2GEJ101X RES 100 OHM 1/10W 5% 0402 SMD 169 4 R343,R344,R345,R347 100K-0402SMT Panasonic ERJ-2GEJ104X RES 100K OHM 1/10W 5% 0402 SMD 179 1 R346 10K-0603SMT Panasonic ERJ-2RKF1002X RES 10.0K OHM 1/16W 1% 0402 SMD OSC CLOCK 100.000 MHZ 3.3V SMD 5x7.5mm SMT Oscillator 45 LatticeECP3 Serial Protocol Board – Revision D User’s Guide Lattice Semiconductor Table 27. Bill of Materials (Continued) Item Quantity Reference Part Manufacturer Part Number Description 180 4 C418,C409,C411,C413 100NF-0603SMT Panasonic ECJ-1VF1C104Z CAP .1UF 16V CERAMIC Y5V 0603 181 5 C419,C427,C431,C220,C221 10NF-0402SMT Panasonic ECJ0EB1E103K CAP .01UF 25V CERAMIC X7R 0402 182 1 U31 SN74LV125 Texas Instruments SN74LVC125AD IC QUAD BUS BUFFER GATE 14-SOIC 183 3 C415,C416,C417 10PF-0402SMT Panasonic ECJ-0EC1H100D CAP 10PF 50V CERAMIC 0402 SMD 184 2 R350,R351 0R-0603SMT Panasonic ERJ-3GEY0R00V RES ZERO OHM 1/10W 5% 0603 SMD 185 1 J48 SMA Molex 73391-0060 CONN JACK SMA STR 50 OHM PCB 186 1 J47 HDR5 Samtec TSW-105-07-T-S 5x1-0.25 Header 187 3 D33,D34,D35 SCHOTTKY/VISHAYV12P10 Vishay V12P10-E3/87A TO277 SCHOTTKY DIODE 188 6 C420,C421,C422,C423,C425,C429 10UF-16V-TANTBSMT AVX TAJB106K016R CAP TANTALUM 10UF 16V 10% SMD 189 4 R357,R358,R359,R360 OPEN-0603SMT 190 3 R348,R349,R352,R373 50R-0603SMT Vishay FC0603E50R0BTBT1 RES 50 OHM 125MW .1% 0603 SMD 191 8 C424,C426,C428,C430,C438,C410,C412,C 100NF-0603SMT 414 Panasonic ECJ-1VF1C104Z CAP .1UF 16V CERAMIC Y5V 0603 192 6 R361,R362,R364,R365,R367,R368 50R-0402SMT Vishay FC0402E50R0BTBST1 RES 50 OHM 50MW .1% 0402 SMD 193 2 R363,R366 1_6R-0603SMT Panasonic ERJ-3GEYJ1R6V RESISTOR 1.6 OHM 1/10W 5% 0603 194 2 Y6,Y7 CRYSTEK_133MHZ Crystek CCLD-033-50-133.000 OSC LVDS 133.0 MHZ 3.3V 7mmx5mm SMD 195 2 R256,R257 50R-0402SMT Vishay FC0402E50R0BTBST1 RES 50 OHM 50MW .1% 0402 SMD 196 1 R269 Do Not Populate 197 2 R300, R301 10K-0402SMT Panasonic ERJ-2RKF1002X RES 10.0K OHM 1/16W 1% 0402 SMD 198 1 R228 240R-0603SMT Panasonic ERA-3YEB241V RES 240 OHM 1/16W .1% 0603 SMD 46