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SLAS393 − OCTOBER 2003
FEATURES
D Eight Voltage Output DACs in One Package
− TLV5610IYE . . . 12-Bit
− TLV5608IYE . . . 10-Bit
D Programmable Settling Time vs Power
Consumption
− 1 µs in Fast Mode
− 3 µs in Slow Mode
D Compatible With TMS320 DSP Family and
APPLICATIONS
D Digital Servo Control Loops
D Digital Offset and Gain Adjustment
D Industrial Process Control
D Machine and Motion Control Devices
D Mass Storage Devices
WCS PACKAGE
(BOTTOM VIEW)
LDAC
MODE
OUTD
REF
OUTB
OUTC
SPI Serial Ports
D Monotonic Over Temperature
D Low Power Consumption:
− 18 mW in Slow Mode at 3 V
− 48 mW in Fast Mode at 3 V
D Power Down Mode
D Buffered, High Impedance Reference Inputs
D Data Output for Daisy Chainin
DOUT
DVDD
18 17 16
19
15
14
13
20
12
11
DGND
1
10
DIN
2
9
3 4
5
FS
SCLK
6
7
OUTE
PRE
OUTA
AVDD
AGND
OUTH
8
OUTG
OUTF
DESCRIPTION
The TLV5610IYE and TLV5608IYE are pin compatible eight channel 12-/10-bit voltage output DACs each with a flexible
serial interface. The serial interface allows glueless interface to TMS320 and SPI, QSPI, and Microwire serial ports. It is
programmed with a 16-bit serial string containing 4 control and 12 data bits.
Additional features are a power-down mode, an LDAC input for simultaneous update of all eight DAC outputs, and a data
output which can be used to cascade multiple devices.
The resistor string output voltage is buffered by a rail-to-rail output amplifier with a programmable settling time to allow the
designer to optimize speed vs power dissipation. The buffered, high-impedance reference input can be connected to the
supply voltage.
The TLV5610IYE and TLV5608IYE implemented with a CMOS process and are available in a 20-terminal WCS package.
The TLV5610IYE and TLV5608IYE are characterized for operation from −40°C to 85°C in a wire-bonded small outline
(SOIC) package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
TMS320 DSP is a trademark of Texas Instruments.
!"#$%&'(!$" !) *+%%,"( ') $# -+./!*'(!$" 0'(, %$0+*()
*$"#$%& ($ )-,*!#!*'(!$") -,% (1, (,%&) $# ,2') ")(%+&,"() )('"0'%0 3'%%'"(4
%$0+*(!$" -%$*,))!"5 0$,) "$( ",*,))'%!/4 !"*/+0, (,)(!"5 $# '// -'%'&,(,%)
Copyright 2003, Texas Instruments Incorporated
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SLAS393 − OCTOBER 2003
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS
PACKAGE
TA
WCS(1)
(YE)
TLV5610IYE
−40°C to 85°C
TLV5608IYE
(1) Wafer chip scale package. See Figure 13.
FUNCTIONAL BLOCK DIAGRAM
REF
12/10
12/10
12/10
X2
DAC A
Holding
Latch
OUTA
DAC A
Latch
SCLK
DIN
DOUT
Serial
Interface
FS
12
8
DAC B, C, D, E, F, G and H
Same as DAC A
MODE
PRE
LDAC
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
AGND
10
P
Analog ground
AVDD
DGND
11
P
Analog power supply
1
P
Digital ground
DIN
2
I
Digital serial data input
DOUT
19
O
Digital serial data output
DVDD
FS
20
P
Digital power supply
4
I
Frame sync input
LDAC
18
I
Load DAC. The DAC outputs are only updated, if this signal is low. It is an asynchronous input.
MODE
17
I
DSP/µC mode pin. High = µC mode, NC = DSP mode.
PRE
5
I
Preset input
REF
16
I
Voltage reference input
SCLK
3
I
Serial clock input
12−15,
6−9
O
DAC outputs A, B, C, D, E, F, G and H
OUTA−OUTH
2
OUT
B, C, D,
E, F, G
and H
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SLAS393 − OCTOBER 2003
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNIT
Supply voltage, (AVDD, DVDD to GND)
7V
Reference input voltage range
− 0.3 V to AVDD + 0.3
− 0.3 V to DVDD + 0.3
Digital input voltage rang
Operating free-air temperature range, TA
−40°C to 85°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Supply voltage, AVDD, AVDD
High level digital input, VIH
Low level digital input, VIL
Reference voltage, Vref
MIN
TYP
MAX
5-V operation
4.5
5
5.5
V
3-V operation
2.7
3
3.3
V
DVDD = 2.7 V to 5.5 V
DVDD = 2.7 V to 5.5 V
2
AVDD = 5 V
AVDD = 3 V
GND
GND
Load resistance, RL
UNIT
V
0.8
V
4.096 AVDD
2.048 AVDD
V
2
kΩ
Load capacitance, CL
100
pF
Clock frequency, fCLK
30
MHz
85
°C
Operating free-air temperature, TA
−40
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted(1)
POWER-SUPPLY
PARAMETER
IDD
Power supply current
TEST CONDITIONS
No load,
All inputs = DVDD or GND
MIN
Vref = 4.096 V,
TYP
MAX
Fast
16
21
Slow
6
8
Power-down supply current
POR
Power on threshold
PSRR
Power supply rejection ratio
mA
µA
0.1
Full scale, See Note 1
UNIT
2
V
−60
dB
STATIC DAC SPECIFICATIONS
Resolution
TLV5610IYE
12
TLV5608IYE
10
TLV5610IYE
INL
Integral nonlinearity
DNL
Differential nonlinearity
EZS
EZS TC
Zero scale error (offset error at zero scale)
EG
Gain error
TLV5608IYE
Vref = 2 V, 4 V
TLV5610IYE
TLV5608IYE
Vref = 2 V, 4 V
Bits
Code 40 to 4095
±2
±6
Code 20 to 1023
±0.5
±2
Code 40 to 4095
±0.5
±1
Code 20 to 1023
±0.1
±1
LSB
±30
mV
Zero scale error temperature coefficient
EGTC
Gain error temperature coefficient
(1) Power supply rejection ratio at full scale is measured by varying AVDD and is given by:
PSRR = 20 log [(EG(AVDDmax) – EG(AVDDmin))/VDDmax]
30
LSB
µV/°C
%Full
±0.6 Scale V
10
ppm/°C
3
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SLAS393 − OCTOBER 2003
ELECTRICAL CHARACTERISTICS (CONTINUED)
over operating free-air temperature range unless otherwise noted(1)
OUTPUT SPECIFICATIONS
PARAMETER
VO
TEST CONDITIONS
Voltage output range
RL = 10 kΩ
Output load regulation accuracy
MIN
TYP
0
MAX
AVDD−0.4
RL = 2 kΩ vs 10 kΩ
UNIT
V
±0.3
%Full
Scale V
MAX
UNIT
AVDD
V
REFERENCE INPUT
PARAMETER
VI
RI
Input voltage range
Ci
Input capacitance
TEST CONDITIONS
MIN
TYP
0
Input resistance
Reference input bandwidth
Vref = 0.4 Vpp + 2.048 Vdc, Input code = 0x800
100
kΩ
5
pF
Fast
2.2
MHz
Slow
1.9
MHz
−84
dB
Reference feedthrough
Vref = 2 Vpp at 1 kHz + 2.048 Vdc (see Note 1)
(1) Reference feedthrough is measured at the DAC output with an input code = 0x000.
DIGITAL INPUTS
PARAMETER
IIH
IIL
High-level digital input current
Ci
Input capacitance
TEST CONDITIONS
VI = DVDD
VI = 0 V
Low-level digital input current
MIN
TYP
MAX
1
UNIT
µA
µA
−1
8
pF
DIGITAL OUTPUTS
PARAMETER
VOH
VOL
High-level digital output voltage
TEST CONDITIONS
Low-level digital output voltage
RL = 10 kΩ
RL = 10 kΩ
Output voltage rise time
RL = 10 kΩ, CL = 20 pF, Includes propogation delay
MIN
TYP
MAX
2.6
UNIT
V
0.4
V
7
20
ns
ANALOG OUTPUT DYNAMIC PERFORMANCE
PARAMETER
TEST CONDITIONS
ts(FS)
Output settling time, full scale
RL = 10 kΩ,
CL = 100 pF, See Note 1
ts(CC)
Output settling time, code to code
RL = 10 kΩ,
CL = 100 pF, See Note 2
SR
Slew rate
RL = 10 kΩ,
CL = 100 pF, See Note 3
Glitch energy
See Note 4
TYP
MAX
Fast
MIN
1
3
Slow
3
7
Fast
0.5
1
Slow
1
2
Fast
4
10
Slow
1
3
4
UNIT
µss
µss
V/ s
V/µs
nV−s
Channel crosstalk
10 kHz sine, 4 VPP
−90
dB
(1)Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of 0x80 to 0xFFF
and 0xFFF to 0x080 respectively. Assured by design; not tested.
(2)Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of one count. The
max time applies to code changes near zero scale or full scale. Assured by design; not tested.
(3)Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full scale voltage.
(4)Code transition: TLV5610IYE − 0x7FF to 0x800, TLV5608IYE − 0x7FC to 0x800.
4
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SLAS393 − OCTOBER 2003
DIGITAL INPUT TIMING REQUIREMENTS
PARAMETER
tsu(FS-CK)
tsu(C16-FS)
Setup time, FS low before first negative SCLK edge
Setup time, 16th negative edge after FS low on which bit D0 is sampled before rising
edge of FS. µC mode only
MIN
TYP
MAX
UNIT
8
ns
10
ns
twL(LDAC)
twH
LDAC duration low
10
ns
SCLK pulse duration high
16
ns
twL
tsu(D)
SCLK pulse duration low
16
th(D)
twH(FS)
Hold time, data held valid after SCLK falling edge
FS duration high
twL(FS)
FS duration low
10
ns
ts
Settling time
Setup time, data ready before SCLK falling edge
8
ns
5
ns
10
ns
See AC
specs
5
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SLAS393 − OCTOBER 2003
TYPICAL CHARACTERISTICS
OUTPUT LOAD REGULATION
OUTPUT LOAD REGULATION
1
1
VDD = 3 V,
Vref = 2 V,
Zero Scale
0.9
0.8
0.8
Fast
0.7
VO − Output Voltage − V
VO − Output Voltage − V
VDD = 5 V,
Vref = 4 V,
Zero Scale
0.9
0.6
0.5
0.4
0.3
0.2
Fast
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.1
Slow
0
0
0.5
1.5
1
Sinking Current − mA
Slow
0
2
0.5
0
Figure 1
OUTPUT LOAD REGULATION
OUTPUT LOAD REGULATION
4.12
VDD = 3 V,
Vref = 2 V,
Full Scale
4.11
Slow
VO − Output Voltage − V
VO − Output Voltage − V
2.055
2
Figure 2
2.06
2.05
1.5
1
Sinking Current − mA
Fast
2.045
2.04
2.035
Fast
VDD = 5 V,
Vref = 4 V,
Full Scale
4.1
Slow
4.09
4.08
4.07
4.06
2.03
2.025
−0.05 −0.5
4.05
4.04
−1
−1.5 −2
−2.5 −3
Sourcing Current − mA
Figure 3
6
−3.5
−4
0
−0.5
−1
−1.5 −2
−2.5 −3
Sourcing Current − mA
Figure 4
−3.5
−4
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SLAS393 − OCTOBER 2003
INL − Integral Nonlinearity − LSB
TLV5610IYE
INTEGRAL NONLINEARITY
vs
CODE
4
3
2
1
0
−1
−2
−3
−4
0
1024
2048
3072
4096
3072
4096
Code
Figure 5
DNL − Differential Nonlinearity − LSB
TLV5610IYE
DIFFERENTIAL NONLINEARITY
vs
CODE
1.0
0.8
0.6
0.4
0.2
−0.0
−0.2
−0.4
−0.6
−0.8
−1.0
0
1024
2048
Code
Figure 6
7
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SLAS393 − OCTOBER 2003
INL − Integral Nonlinearity − LSB
TLV5608IYE
INTEGRAL NONLINEARITY
vs
CODE
2.0
1.5
1.0
0.5
0.0
−0.5
−1.0
−1.5
−2.0
0
256
512
768
1024
768
1024
Code
Figure 7
DNL − Differential Nonlinearity − LSB
TLV5608IYE
DIFFERENTIAL NONLINEARITY
vs
CODE
1.0
0.8
0.6
0.4
0.2
−0.0
−0.2
−0.4
−0.6
−0.8
−1.0
0
256
512
Code
Figure 8
8
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SLAS393 − OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
twH
twL
SCLK
X
1
2
3
4
16
X
th(D)
tsu(D)
DIN
X
DOUT
X
D15
D14
(1)
D15
D13
(1)
D14
D12
(1)
D1
(1)
D13
D12
D0
(1)
X
(1)
D0
D1
X
tsu(FS-CK)
twH(FS)
tsu(C16-FS)
FS
(µC mode)
twL(FS)
FS
(DSP Mode)
X
(1) Previous input data
Figure 9. Serial Interface Timing
twL(LDAC)
LDAC
ts
±0.5 LSB
OUTx
Figure 10. Output Timing
9
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SLAS393 − OCTOBER 2003
APPLICATION INFORMATION
GENERAL FUNCTION
The TLV5610IYE and TLV5608IYE are 8-channel, 12-bit, single supply DACs, based on a resistor string
architecture. They consist of a serial interface, a speed and power-down control logic, a reference input buffer,
a resistor string, and a rail-to-rail output buffer.
The output voltage (full scale determined by external reference) for each channel is given by:
REF CODE [V]
0x1000
where REF is the reference voltage and CODE is the digital input value. The input range is 0x000 to 0xFFF
for the TLV5610IYE and, 0x000 to 0xFFC for the TLV5608IYE. A power on reset initially puts the internal latches
to a defined state (all bits zero).
SERIAL INTERFACE
A falling edge of FS starts shifting the data on DIN starting with the MSB to the internal register on the falling
edges of SCLK. After 16 bits have been transferred, the content of the shift register is moved to one of the DAC
holding registers depending on the address bits within the data word. A logic 0 on the LDAC pin is required to
transfer the content of the DAC holding register to the DAC latch and to update the DAC outputs. LDAC is an
asynchronous input. It can be held low if a simultaneous update of all eight channels is not needed.
For daisy-chaining, DOUT provides the data sampled on DIN with a delay of 16 clock cycles.
DSP Mode:
SCLK
FS
DIN
X
D15
D14
D1
D0
E15
E14
X
D15
D14
D1
D0
X
E15
E1
E0
X
E1
E0
X
X
F15
F15
X
F15
F15
µC Mode:
SCLK
FS
DIN
E14
X
Difference between DSP mode (MODE = N.C. or 0) and µC (MODE = 1) mode:
D In µC mode FS needs to be held low until all 16 data bits have been transferred. If FS is driven high before
the 16th falling clock edge the data transfer is cancelled. The DAC is updated after a rising edge on FS.
D In DSP mode FS only needs to stay low for 20 ns and can go high before the 16th falling clock edge.
10
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SLAS393 − OCTOBER 2003
SERIAL CLOCK FREQUENCY AND UPDATE RATE
The maximum serial clock frequency is given by:
f
sclkmax
+
t
whmin
1
)t
+ 30 MHz
wlmin
The maximum update rate is:
f
+
updatemax
1
Ǔ
)t
16 ǒt
whmin
wlmin
+ 1.95 MHz
Note, that the maximum update rate is just a theoretical value for the serial interface, as the settling time of the
DAC has to be considered also.
DATA FORMAT
The 16 bit data word consists of two parts:
D Address bits
D Data bits
(D15…D12)
(D11…D0)
D15
D14
D13
D12
A3
A2
A1
A0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Data
Ax: Address bits. See table.
REGISTER MAP
A3
A2
A1
A0
FUNCTION
0
0
0
0
DAC A
0
0
0
1
DAC B
0
0
1
0
DAC C
0
0
1
1
DAC D
0
1
0
0
DAC E
0
1
0
1
DAC F
0
1
1
0
DAC G
0
1
1
1
DAC H
1
0
0
0
CTRL0
1
0
0
1
CTRL1
1
0
1
0
Preset
1
0
1
1
Reserved
1
1
0
0
DAC A and B
1
1
0
1
DAC C and D
1
1
1
0
DAC E and F
1
1
1
1
DAC G and H
11
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SLAS393 − OCTOBER 2003
DAC A−H AND TWO-CHANNEL REGISTERS
Writing to DAC A−H sets the output voltage of channel A−H. It is possible to automatically generate the
complement of one channel by writing to one of the four two-channel registers (DAC A and B etc.).
The TLV5610IYE decodes all 12 data bits. The TLV5608IYE decodes D11 to D2 (D1 and D0 are ignored).
PRESET
The outputs of all DAC channels can be driven to a predefined value stored in the preset register by driving the
PRE input low. The PRE input is asynchronous to the clock.
CTRL0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
PD
DO
X
X
IM
PD
DO
IM
X
: Full device power down
: Digital output enable
: Input mode
: Reserved
0 = normal
0 = disable
0 = straight binary
1 = power down
1 = enable
1 = twos complement
If DOUT is enabled, the data input on DIN is output on DOUT with a 16 cycle delay. That makes it possible to
daisy-chain multiple DACs on one serial bus.
CTRL1
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
PGH
PEF
PCD
PAB
SGH
SEF
SCD
SAB
PXY
SXY
XY
: Power Down DACXY
: Speed DACXY
: DAC pair AB, CD, EF or GH
0 = normal
0 = slow
1 = power down
1 = fast
In power-down mode, the amplifiers of the selected DAC pair within the device are disabled and the total power
consumption of the device is significantly reduced. Power-down mode of a specific DAC pair can be selected
by setting the PXY bit within the data word to 1.
There are two settling time modes: fast and slow. Fast mode of a DAC pair is selected by setting SXY to 1 and
slow mode is selected by setting SXY to 0.
12
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SLAS393 − OCTOBER 2003
USING TLV5610IYE AND TLV5608IYE, WAFER CHIP SCALE PACKAGE (WCS)
D TLV5610 and TLV5608 qualifications were done using a wire-bonded small outline (SOIC) package and
includes: steady state life, thermal shock, ESD, latch-up, biased HAST, autoclave, and characterization.
These qualified devices are orderable as TLV5610IDW and TLV5608IDW.
D The wafer chip-scale package (WCS), TLV5610IYE and TLV5608IYE, uses the same DIE as
TLV5610IDW and TLV5608IDW respectively, but are not qualified. WCS qualification, including board
level reliability (BLR), is the responsibility of the customer.
D It is recommended that underfill be used for increased reliability. BLR is application dependent, but may
include test such as: temperature cycling, drop test, key push, bend, vibration, and package shear.
The following WCSP information provides the user of the TLV5610IYE and TLV5608IYE with some general
guidelines for board assembly.
D Melting point of eutectic solder is 183°C.
D Recommended peak reflow temperatures are in the 220°C to 230°C range.
D The use of underfill is required. The use of underfill greatly reduces the risk of thermal mismatch fails.
Underfill is an epoxy/adhesive that may be added during the board assembly process to improve board
level/system level reliability. The process is to dispense the epoxy under the dice after die attach reflow. The
epoxy adheres to the body of the device and to the printed-circuit board. It reduces stress placed upon the solder
joints due to the thermal coefficient of expansion (TCE) mismatch between the board and the component.
Underfill material is highly filled with silica or other fillers to increase an epoxy’s modulus, reduce creep
sensitivity, and decrease the material’s TCE.
The recommendation for peak flow temperatures of 220°C to 230°C is based on general empirical results that
indicate that this temperature range is needed to facilitate good wetting of the solder bump to the substrate or
circuit board pad. Lower peak temperatures may cause nonwets (cold solder joints).
Bottom View
Top View
NOTES:A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
Figure 11. TLV5610IYE and TLV5608IYE Wafer Chip Scale Package
13
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