ICs for Consumer Electronics DDC-PLUS-Deflection Controller SDA 9362 Data Sheet 1998-02-01 Edition 1998-02-01 This edition was realized using the software system FrameMaker Published by Siemens AG, Bereich Halbleiter, Marketing-Kommunikation, Balanstraße 73, 81541 München © Siemens AG 1998. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. 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Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered. SDA 9362 Revision History: Current Version: 1998-02-01 Previous Version: 1997-04-01 Page Page (in previous (in current Version) Version) Subjects (major changes since last revision) 30 32 Nom./max. average current and max. standby current specified 30 32 Specification of charge current pump of PLL pin LF is unnecessary Data Classification Maximum Ratings Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Recommended Operating Conditions Under this conditions the functions given in the circuit description are fulfilled. Nominal conditions specify mean values expected over the production spread and are the proposed values for interface and application. If not stated otherwise, nominal values will apply at TA=25°C and the nominal supply voltage. Characteristics The listed characteristics are ensured over the operating range of the integrated circuit. Edition 1998-02-01 Published by Siemens AG, Semiconductor Group Copyright Siemens AG 1998. All rights reserved. Terms of delivery and right to change design reserved. SDA 9362 Table of Contents Page 1 1.1 1.2 1.3 1.4 1.5 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 6 6 7 9 2 2.1 2.2 2.3 2.4 2.5 2.5.1 2.5.2 2.5.3 2.5.4 2.5.5 System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frequency Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I²C-Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I²C-Bus Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I²C-Bus Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I²C-Bus Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Explanation of Some Control Items . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 10 12 13 13 14 14 14 15 16 20 3 3.1 3.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Characteristics (Assuming Recommended Operating Conditions) . . . . . . . 32 4 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5 5.1 5.2 5.3 5.4 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VD- Output Voltage, 4/3-CRT and 16/9-Source . . . . . . . . . . . . . . . . . . . . . . Function of H,V Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power On/Off Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standby Mode, RESN Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Semiconductor Group 4 35 35 36 37 38 1998-02-01 DDC-PLUS-Deflection Controller SDA 9362 MOS 1 Overview 1.1 Features • • • • • Deflection - Protection - 16:9 / 4:3 Ι2C Bus alignment of all deflection parameters All EW-, V- and H-functions (incl. Φ2) PW EHT compensation PH EHT compensation P-MQFP-44-2 • Compensation of H-phase deviation (e.g. caused by white bar) • Upper/lower EW-corner correction separately adjustable • V-angle correction: Vertical frequent linear modulation of H-phase • V-bow correction: Vertical frequent parabolic modulation of H-phase • Three reduced V-scan modes (75 %, 66 %, 50 % V-size) selectable • H- and V-blanking time adjustable • Partial overscan adjustable to hide the cut off control measuring lines in the reduced scan modes • Stop/start of vertical deflection adjustable to fill out the 16/9 screen with different letterbox formats without annoying overscan • Dynamic PH EHT-compensation (white bar) • Self adaptation of V-frequency/number of lines per field between 192 and 680 for each possible line frequency • Protection against EHT run away (X-rays protection) • Protection against missing V-deflection (CRT-protection) • Two digital outputs for general purpose, controlled by Ι2C Bus • Selectable softstart of the H-output stage • P-MQFP-44-2 package • 5 V supply voltage Type Ordering Code Package SDA 9362 Q67101-H5173-A701 P-MQFP-44-2 Semiconductor Group 5 1998-02-01 SDA 9362 1.2 General Description The SDA 9362 is a highly integrated deflection controller for CTV receivers with doubled line and standard or doubled field frequencies. It controls among others an horizontal driver circuit for a flyback line output stage, a DC coupled vertical sawtooth output stage and an East-West raster correction circuit. All adjustable output parameters are Ι2C Bus controlled. Inputs are HSYNC, VSYNC and the line locked clock CLL. Pin Configuration HDEDEF TST1 TST0 TEST HD VSYNC SW1 φ2 VREFH VREFL VSS(A) 1.3 34 35 36 37 38 39 40 41 42 43 44 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1 2 3 4 5 6 7 8 9 10 11 CLL X1 X2 SDA SCL HSYNC VBLE SCP VDD(D) VSS(D) VPROT SSD TST4 TST5 TST6 VDD(D) VSS(D) TST7 VSS(D) LF VDD(D) RESN VDVD+ E/W VDD(A) VREFP VREFN VSS(A) IBEAM SW2 VDD(A) HPROT UEP10259 Figure 1 Semiconductor Group 6 1998-02-01 SDA 9362 1.4 Pin Description Pin No. Symbol Type Description 1 CLL I/TTL Clock input 2 X1 I Reference oscillator input, crystal 3 X2 Q Reference oscillator output, crystal 4 SDA IQ 5 SCL I Ι2C-Bus data Ι2C-Bus clock 6 HSYNC I/TTL H-sync input 7 VBLE Q/TTL Vertical blanking output 8 SCP Q Blanking signal with H- and color burst component (V-component selectable by Ι2C Bus) 9 S Digital supply 10 VDD(D) VSS(D) S Digital ground 11 VPROT I Watching external V-output stage (input is the V-sawtooth from feedback resistor) 12 HPROT I Watching EHT (input is e.g. H-flyback) 13 VDD(A) S Analog supply 14 SW2 Q/TTL Output of an Ι2C Bus controlled switch (Register 00H, Bit D5) 15 IBEAM I Input for a beam current dependent signal for stabilization of width, height and H-phase 16 S Analog ground IQ Ground for VREFP, VREFH, VREFL 18 VSS(A) VREFN VREFP IQ Reference voltage for IBEAM ADC, HPROT / VPROT thresholds 19 VDD(A) S Analog supply 20 E/W Q Control signal output for East-West raster correction 21 VD+ Q Control signal output for DC coupled V-output stage 22 VD- Q Like VD+ 23 VSS(A) VREFL VREFH S Analog ground IQ Reference voltages for E/W-DAC, V-DAC IQ Like VREFL I Line flyback for H-delay compensation 17 24 25 26 Φ2 Semiconductor Group 7 1998-02-01 SDA 9362 1.4 Pin Description (cont’d) Pin No. Symbol Type Description 27 SW1 Q/TTL Output of an Ι2C Bus controlled switch (Register 00H, Bit D3) 28 VSYNC I/TTL V-sync input 29 HD Q Control signal output for H driver stage 30 TEST I/TTL Switching normal operation (TEST = L) and test mode (TEST = H: pin 34 is an additional test pin) 31 TST0 I Test pin, to be grounded 32 TST1 I Test pin, to be grounded 33 HDEDEF I/TTL Defines the default value of HDE 34 SSD I/TTL Disables soft start (H) 35 TST4 I Test pin, to be grounded 36 TST5 O Test pin, don’t connect 37 TST6 O Test pin, don’t connect 38 S Digital supply 39 VDD(D) VSS(D) S Digital ground 40 TST7 O Test pin, don’t connect 41 VSS(D) S Digital ground 42 LF IQ PLL loop filter 43 VDD(D) S Digital supply 44 RESN I/TTL Reset input, active low Semiconductor Group 8 1998-02-01 SDA 9362 1.5 Block Diagram φ2 SCP SCAN HPROT SSD VPROT SCL SDA RESN HDEDEF TST0 TEST TST1 VSYNC HSYNC Protection Start Up Ι2C H-Out V-Out HD VD+ VD- Control CLL EW-Corr E/W PWM PWM D/A D/A CLKI PLL LF PW/PH Corr X1 X2 VREFC VREFL VREFH VREFP VREFN ABL UEB10258 Figure 2 Semiconductor Group 9 1998-02-01 SDA 9362 2 System Description 2.1 Functional Description The main input signals are HSYNC with doubled horizontal frequency, VSYNC with vertical frequencies of 50/100 Hz or 60/120 Hz and the line locked clock CLL. The output signals control the horizontal as well as the vertical deflection stages and the East-West raster correction circuit. The H-output signal HD compensates the delays of the line output stage and its phase can be modulated vertical frequent to remove horizontal distortions of vertical raster lines (V-Bow, V-Angle). Time reference is the middle of the front and back edge of the line flyback pulse. A positive HD pulse switches off the line output transistor. Maximal H-shift is 2.25 µs. Picture tubes with 4:3 or 16:9 aspect ratio can be used by adapting the raster to the aspect ratio of the source signal. The V-output sawtooth signals VD- and VD+ controls a DC coupled output stage and can be disabled. Suitable blanking signals are delivered by the IC. The East-West output signal E/W is a vertical frequent parabola of 4th order, enabling an additional corner correction, separately for the upper and lower part. Two Ι2C Bus controlled digital outputs are available for general purpose. The picture width and picture height compensation (PW/PH Comp) processes the beam current dependent input signal IBEAM with effect to the outputs E/W and VD to keep width and height constant and independent of brightness. The alignment parameter Horizontal Shift Compensation enables to adjust the influence of the input signal IBEAM on the horizontal phase. The selectable start up circuit controls the energy supply of the H-output stage during the receiver's run up time by smooth decreasing the line output transistors switching frequency down to the normal operating value (softstart). HD starts with about 55 kHz and converges within 85 ms to its final value. The high time is kept constant. The normal operating pulse ratio H/L is 45/55. A watch dog function limits the period of the HD output signal independent of the clock CLL to max 35.2 µs. The protection circuit watches an EHT reference and the sawtooth of the vertical output stage. H-output stage is switched off if the EHT succeeds a defined threshold or if the V-deflection fails (refer to page 36). The function of this circuit is based on the internal quartz oscillator and therefore independent of the input clock CLL. HPROT: Input Semiconductor Group Vi < V2 Vi > V1 V2 ≤ Vi < V1 Continues blanking HD disabled Operating range 10 1998-02-01 SDA 9362 VPROT: Vertical sawtooth voltage Vi < V1 in first half of V-period or Vi > V2 in second half: HD disabled The pin SCP delivers the composite blanking signal SCP. It contains burst (Vb), Hblanking HBL (VHBL) and selectable V-blanking (control bit SSC). The phase of the Hblanking period can be varied by Ι2C Bus. For the timing following settings are possible: BD = 1 BD = 0, BSE = 0 (default value) BD = 0, BSE = 1(alignment range) : tBL = 0 : tHBL = tf (H-flyback time) : tHBL = (4 * H-blanking-time + 1) / CLL : tDBL = (H-shift + 4 * H-blanking-phase -2 * H-blanking-time + 43) / CLL : tBL = tVBL during V-blanking period : tBL is always tHBL SSC = 0 SSC = 1 Input Signal HSYNC t DB tB t DBL VOH VOHBL VOL t BL UED10260 Figure 3 BG-pulse width tB Delay to HSYNC tDB Semiconductor Group 54 / CLL 36 / CLL 11 1998-02-01 SDA 9362 2.2 Circuit Description The system clock for the SDA 9362 has to be generated externally (e.g. in the SDA 9206) and applied to pin CLL. Its frequency must be always the line frequency (defined by the horizontal time reference HSYNC) multiplied by 864. If no HSYNC signal is available an internal horizontal synchronisation signal is derived from CLL (CLL divided by 879). The input signal at VSYNC is the vertical time reference. It has to pass a window avoiding too short or long V-periods in the case of distorted or missing VSYNC pulses. The window allows a VSYNC pulse only after a minimum number of lines from its predecessor and sets an artificial one after a maximum number of lines. The window size is programmable by Ι2C Bus. The beam current dependent input signal IBEAM is A/D converted and then digitally processed. The A/D Converter requires a clock frequency twice the frequency of CLL which is generated by an internal analog PLL with an external loop filter at pin LF. Values which influence shape and amplitude of the output signals are transmitted as reduced binary values to the SDA 9362 via Ι2C Bus. A CPU which is designed for speed reasons in a pipe line structure calculates in consideration of feedback signals (e.g. IBEAM) values which exactly represent the output signals. These values control after D/A conversion the external deflection and raster correction circuits. The CPU firmware is stored in an internal ROM. Semiconductor Group 12 1998-02-01 SDA 9362 2.3 Reset Modes The circuit is only completely reset at power-on/off (timing diagram refer 5.3). If the pin RESN has L-level or during standby operation some parts of the circuit are not affected (timing diagram refer 5.4): Power-On-Reset External Reset (pin RESN=0) Standby Mode (I2C-Bit STDBY=1) HD output High Active Active H-protection Inactive Active Active V-protection Inactive Active1) Active1) Ι2C Interface (SDA, SCL) Tristate Ready Ready Ι2C Register 01H..1BH Set to default values Set to default values Set to default values Ι2C Register 00H, 48H Set to default values Not affected Not affected Status bit PONRES Set to 12) Set to 1 Not affected VREFP Not affected Not affected Not affected VREFH, VREFL Not affected Not affected Inactive CPU Inactive Inactive Inactive 1) Inactive if HPROT < V2 (typ. 2.4 V) 2) Can only be read after Power-On-Reset is finished Note: Power-On-Reset state is deactivated after ca. 32 cycles of the X1/X2 oscillator clock. RESN = Low and standby state are deactivated after ca. 42 cycles of the CLL clock. 2.4 Frequency Ranges H V nL 31.25 kHz 50 Hz 100 Hz 625 NI / 1250I 625 I 31.5 kHz 60 Hz 120 Hz 525 NI / 1050 I 525 I The allowed deviation of all input line frequencies is max. ± 4.5 %. nL: Number of lines per frame I: Interlaced NI: Non interlaced Semiconductor Group 13 1998-02-01 SDA 9362 If NSA = 0 (subaddress 01H/D5H) number of lines per field is selfadaptable between 192 and 680 for each specified H-frequency. 2.5 I2C-Bus Control 2.5.1 I2C-Bus Address 1 0 0 0 1 1 0 2.5.2 I2C-Bus Format write: S 1 0 0 0 1 1 0 0 A Subaddress A Data Byte A ***** Status byte A Data Byte n A ***** A P read: S 1 0 0 0 1 1 0 1 A NA P Reading starts at the last write address n. Specification of a subaddress in reading mode is not possible. S: A: P: NA: Start condition Acknowledge Stop condition Not acknowledge An automatical address increment function is implemented. After switching on the IC, all bits are set to defined states (00H) (exception: HDE depends on pin 33; see page 17) Semiconductor Group 14 1998-02-01 SDA 9362 2.5.3 I2C-Bus Commands Unit Subaddr. D7 D6 D5 D4 D3 D2 D1 D0 Allowed Effective Can be Default Range Range Disabled Value if by Bit Disabled Control Item Deflection control 0 00H see below – – – – – Deflection control 1 01H see below – – – – – Vertical shift 02H B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -128..127 – – – Vertical size 03H B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -128..127 – – – Vertical linearity 04H B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -128..127 – – – Vertical S-correction 05H B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -128..127 – – – Vertical EHT compensation 1) 06H B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -128..127 – – – Horizontal size 07H B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -128..127 – – – Pin phase 08H B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -128..127 – – – Pin amp 09H B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -128..127 – – – Upper corner pin correction 0AH B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -128..127 – – – Lower corner pin correction 0BH B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -128..127 – – – Horizontal EHT compensation 1) 0CH B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -128..127 – – – Horizontal shift 0DH B6 B5 B4 B3 B2 B1 B0 X – – 1/CLL Vertical angle 0EH B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -128..127 – – – Vertical bow 0FH B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -128..127 – – – Vertical blanking time 1) 10H X BSE = 0 b) lines Horizontal blanking time 11H X Horizontal blanking phase Vertical scan width 0 1) Vertical scan width 1 1) Guard band 1) Start reduced scan 1) Vertical sync control Min..No. of lines / 0..127 a) X 0..63 0..63 -32..31 -32..31 – – 4/CLL c) SSE = 0 9 line B5 B4 B3 B2 B1 B0 field 1) X 13H B7 B6 B5 B4 B3 B2 B1 B0 -128..127 14H X -64..63 B6 B5 B4 B3 B2 B1 B0 12H B5 B4 B3 B2 B1 B0 X Start vertical scan 1) -64..63 X X X X B9 B8 4/CLL 0..3 d) STE = 0 e) 256 lines 15H B7 B6 B5 B4 B3 B2 B1 B0 0..255 d) STE = 0 e) lines 16H X X B5 B4 B3 B2 B1 B0 0..63 0..63 GBE = 0 3 half lines 17H X X B5 B4 B3 B2 B1 B0 0..63 0, 2..63 SRSE = 0 2 line – – – – – 18H X BSE = 0 H-flyback see below 19H B7 B6 B5 B4 B3 B2 B1 B0 0..255 0..255 – – 2 lines Max. No. of lines / field 1) 1AH B7 B6 B5 B4 B3 B2 B1 B0 0..255 0..255 – – 2 lines AFC EHT compensation 1) 1BH B5 B4 B3 B2 B1 B0 X -32..31 -32..31 – – – Internal voltage Ref control 48H – – – – – 1) see below X see 2.5.5: Explanation of some control items Semiconductor Group 15 1998-02-01 SDA 9362 a) The effective range for Vertical Blanking Time: 16 ... 127 (absolute value) if STE = 0 0 ... 127 (offset value) if STE = 1. b) The "default value if disabled" for Vertical Blanking Time: 21 (absolute value) if STE = 0 8 (offset value) if STE = 1. c) The effective range for Start Vertical Scan: 2 ... 127 (absolute value) if STE = 0 if STE = 1 and NSA = 1 if STE = 1 and NSA = 0. -128 ... 127 (offset value) d) The effective range for Vertical Scan (total width: 10 Bit): 160 ... 684 lines. e) The "default value if disabled" for Vertical Scan equals the number of lines of the source signal reduced by the control value for Start Vertical Scan. (E.g.: input signal: 262 lines per field; Start vertical scan = 8 lines; then (if SSE = 1, STE = 0) vertical scan = 262 - 8 = 254 lines. At power on the RAM containing the control items is cleared. Therefore all data are zero by default before transferring individual values via Ι2C Bus. Allowed values out of the effective range are limited, e. g. Vertical blanking time = 3 is limited to 16 if STE = 0 (that means a minimum of 16 lines is blanked). There are five bits (SRSE, BSE, SSE, STE, GBE) in the deflection control byte 1 for disabling some control items. If one of these bits is "0", the value of the corresponding control item will be ignored and replaced by the value "default value if disabled" in the table above. 2.5.4 Detailed Description The Deflection Control Byte 0 includes the following bits: VOFF STDBY SW2 BD SW1 VR1 VOFF: Vertical off 0: normal vertical output due to control items 1: vertical saw-tooth is switched off, vertical protection is disabled STDBY: Stand-by mode 0: normal operation 1: stand-by mode (all internal clocks are disabled) Semiconductor Group 16 VR0 HDE 1998-02-01 SDA 9362 SW2: Setting of output SW2 0: output SW2 has L-level 1: output SW2 has H-level BD: Blanking disable 0: horizontal and vertical blanking enabled 1: horizontal and vertical blanking disabled SW1: Setting of output SW1 0: output SW1 has L-level 1: output SW1 has H-level VR1 ... VR0: Reduction of vertical size 00: 100 % V-size (16:9 source on 16:9 display) 01: 75 % V-size (16:9 source on 4:3 display) 10: 66 % V-size (two 4:3 sources on 16:9 display) 11: 50 % V-size (two 16:9 sources on 16:9 display) HDE: HD enable 0: line is switched off (HD disabled, that is H-level) 1: line is switched on (HD enabled) Default value depends on pin 33 (HDEDEF): HDEDEF = Low: 0 HDEDEF = High: 1 The Deflection Control Byte 1 includes the following bits: X VDC: VDC NSA STE GBE SRSE SSE BSE Vertical dynamic compensation 0: influence of the beam current input IBEAM on the vertical sawtooth is static (´zooming´ correction) 1: influence of the beam current input IBEAM on the vertical sawtooth is dynamic (´ripple´ correction) Semiconductor Group 17 1998-02-01 SDA 9362 NSA: No self adaptation 0: self adaptation on 1: self adaptation off STE: Scan time enable 0: control items for vertical scan width 0 and width 1 are disabled 1: control items for vertical scan width 0 and width 1 are enabled GBE: Guard band enable 0: control item for guard band is disabled 1: control item for guard band is enabled SRSE: Start reduced scan enable 0: control item for start reduced scan is disabled 1: control item for start reduced scan is enabled SSE: Start scan enable 0: control item for start vertical scan is disabled 1: control item for start vertical scan is enabled BSE: Blanking select enable 0: control items for blanking times are disabled 1: control items for blanking times are enabled The Vertical Sync Control Byte includes the following bits: X VBLE SSC X NI X X X VBLE: Vertical blanking extension (this bit does not change the VBL component at output SCP, only the trailing edge of VBLE is affected) 0: output VBLE has the same timing as VBL component at SCP 1: output VBLE is 6 lines longer than VBL component at SCP SSC: Sandcastle without VBL 0: output SCP with VBL component 1: output SCP without VBL component Semiconductor Group 18 1998-02-01 SDA 9362 NI: Non interlace 0: interlace depends on source 1: no interlace The Internal Voltage Ref Control Byte includes the following bits: BANDG5 BANDG4 BANDG3 BANDG2 BANDG1 BANDG0 BANDG BANDG4 OFF OFF BANDG5 ... Adjustment of internal bandgap reference BANDG0:100000: Reference Output voltage min : 011111: Reference Output voltage max Typical adjustment range is 1 V. BANDGOFF: Bandgap off 0: VREFH, VREFL derived internally from VREFP 1: external references on VREFP, VREFH, VREFL have to be applied (in this case BANDG4OFF must be = 1) BANDG4OFF: Bandgap 4 V off 0: internal bandgap reference is used for VREFP 1: external reference on VREFP (4 V) has to be applied The Status Byte includes the following bits HPON VPON – – – – – HPON: H-protection on 0: normal operation of the line output stage 1: high level on input HPROT has switched off the line VPON: V-protection on 0: normal operation of the vertical output stage 1: incorrect signal on input VPROT has switched off the line Semiconductor Group 19 PONRES 1998-02-01 SDA 9362 PONRES: Power On Reset 0: after bus master has read the status byte 1: after each detected reset Note: PONRES is reset after this byte has been read. 2.5.5 Explanation of Some Control Items Start Vertical Scan If enabled (SSE = 1) this control item defines the start of calculation of the vertical sawtooth, the east/west parabola and the vertical function required for the vertical modulated output HD. Vertical Scan (width0 and width1) The total width of this control item is 10 Bit. Therefore two (width0 and width1) registers are necessary. If enabled (STE = 1) it defines the duration of the vertical scan. When the vertical period has more lines than the sum of Start Vertical Scan and Vertical Scan, the calculation of the vertical sawtooth, the east/west parabola and the vertical parabola required for HD stops so that the corresponding output signals remain unchanged till the next vertical synchron pulse. Guard Band This control item is useful for optimizing self adaptation. Video signals with different number of lines in consecutive fields (e. g. VCR search mode) must not start the procedure of self adaptation. But switching between different TV standards has to change the slope of the vertical sawtooth getting always the same amplitude (self adaptation). To avoid problems with flicker free TV systems which have alternating number of lines per field an average value of four consecutive fields is calculated. If the deviation of these average values (e.g. PAL: 312.5 lines or 625 half lines) is less or equals Guard Band, no adaptation takes place. When it exceeds Guard Band, the vertical slope will be changed. Start Reduced Scan If enabled (SRSE = 1) this item defines the start of the D/A-conversion of the calculated vertical sawtooth. From begin of the vertical flyback to the line defined by Start Reduced Scan the output signals VD+, VD- remain unchanged (flyback level). Other outputs are not affected. a) control bits VR1, VR0 # 00 (reduction of vertical size) In this case the byte is useful for e.g. displaying 16/9 source format on 4/3 picture tubes without visible RGB lines generated of the automatic cut-off control (partial Semiconductor Group 20 1998-02-01 SDA 9362 overscan). It defines the start of the reduced amplitude (factors 0.5, 0.66, 0.75) of the vertical sawtooth (refer page 35). When Start Reduced Scan = 0 the reduction takes place over all lines including vertical flyback. b) control bits VR1, VR0 = 00 (no reduction of vertical size) If Start Reduced Scan > Start Vertical Scan the D/A conversion of the sawtooth starts (Start Reduced Scan - Start Vertical Scan) lines after begin of the calculation. This causes a jump of the output voltage VD+, VD- from flyback to scan level. It may be useful to hide the automatic cut-off control lines if no overscan is desired (e.g. for VGA display). If Start Reduced Scan <= Start Vertical Scan this byte has no effect. Vertical EHT Compensation This item controls the influence of the beam current dependent input signal IBEAM on the outputs VD+ and VD- according to the following equation Vertical EHT compensation + 128 1) ∆V VDPP = ∆V IBEAM * ----------------------------------------------------------------------------------------- * 0,57 512 ∆VVDPP: ∆VIBEAM: variation of VD+ and VD- peak-to-peak voltage variation of IBEAM input voltage 1) the factor 0.57 depends on VREFP, VREFH, VREFL If Vertical EHT Compensation = -128 the outputs VD+ and VD- are independent of the input signal IBEAM. Horizontal EHT Compensation This item controls the influence of the input signal IBEAM on the output E/W according to the following equation: Horizontal EHT compensation + 128 1) ∆V EW = ∆V IBEAM * --------------------------------------------------------------------------------------------------- * 2,12 128 ∆VEW: ∆VIBEAM: variation of E/W output voltage variation of IBEAM input voltage 1) the factor 2.12 depends on VREFP, VREFH, VREFL If Horizontal EHT Compensation = -128 the output E/W is independent of the input signal IBEAM. AFC EHT Compensation Deviation of the horizontal phase caused by high beam current (e.g. white bar) can be eliminated by this control item. The beam current dependent input signal IBEAM is multiplied by AFC EHT Compensation. Semiconductor Group 21 1998-02-01 SDA 9362 Additional to the control items Vertical angle, Vertical bow and Horizontal shift, this product influences the horizontal phase at the output HD according to the following equation: ∆φ = ∆V IBEAM ∆φ: ∆VIBEAM: CLL: 1) AFC EHT compensation 52 * ---------------------------------------------------------------- * ---------CLL 64 variation of horizontal phase at the output HD (positive values: shift left, negatives values: shift right) variation of IBEAM input voltage (units: Volt) 864 * fH 1) the factor 52 depends on VREFP Vertical Blanking Time (VBT) VBT defines the vertical blanking pulse VBL which is part of the output signal SCP. VBL is synchronized with the leading edge of HSYNC. It always starts and stops at the beginning of line and never in the center. a) Case of STE = 0 In this case the control item Vertical blanking time defines the duration of the V-blanking pulse (VBL) exactly in number of lines. Because of IC internal limitations 16 through 127 lines can be blanked. If BSE = 0 the control item Vertical blanking time is disabled and always 21 lines (default value if disabled) are blank. After power on the control bit BSE is 0. Therefore 21 lines will be blanked before any programming of the IC. If Vertical Blanking Time is less or equals 21 lines, VBL starts (point A in fig. above) always 0 ... 0.5 line (new odd field) or 0.5 ... 1 line (new even field) prior to the vertical flyback. Otherwise VBL is concentric to a fictitious vertical flyback period of 21 lines, that means VBL starts (VBT - 21) / 2 lines at the end of an odd field or (VBT - 20) / 2 at the end of an even field prior to point A. Possible start points are only the beginning of line. Semiconductor Group 22 1998-02-01 SDA 9362 1 2 1 Line 14 15 16 17 18 19 20 21 22 23 24 25 ~ ~ VSYNC ~ ~ HSYNC Start of even Field Start of odd Field ~ ~ VD- ~ ~ VBL (BSE = 0) 21 Lines ~ ~ VBL (BSE = 1, VBT = 16) 2 Lines 16 Lines 2 Lines ~ ~ VBL (BSE = 1, VBT = 25) 25 Lines 3 Lines ~ ~ VBL (BSE = 1, VBT = 26) 26 Lines UED10261 A Figure 4 Vertical Blanking Pulse VBL when STE = 0 and Number of Lines per Field = Constant Semiconductor Group 23 1998-02-01 SDA 9362 b) Case of STE = 1 In this case the control item Vertical blanking time is an extension for the V-blanking pulse. - If BSE = 1 and VBT = 0 the V-blanking pulse has its minimum: it starts always at end of scan (line B in Fig. below) and ends at start of scan (line C) defined by the control items Start Vertical Scan (if SSE = 1) and Vertical Scan. - BSE = 1 and (128 > VBT > 0) extend the V-blanking pulse according to the following relationship (If VBT > 127 this value is ignored and replaced by VBT - 128): VBL starts VBT / 2 lines (even field) respectively (VBT + 1) / 2 lines (odd field) prior to line B. VBL ends (VBT + 1) / 2 lines (even field) respectively VBT / 2 lines (odd field) after end of line C. Possible start points are only the beginning of line. - If BSE = 0 (after power on) the control item Vertical Blanking Time is disabled and VBL starts 4 lines prior to end of scan (line B) and ends 4 lines after start of scan (line C). Semiconductor Group 24 1998-02-01 SDA 9362 2 1 Line Start of odd Field C Start of even Field ~ ~ VD- 3 ~ ~ ~ ~ VSYNC 1 ~ ~ B ~ ~ HSYNC Even 4 Lines 4 Lines ~ ~ ~ ~ ~ ~ VBL (BSE = 1, VBT = 0) ~ ~ VBL (BSE = 0) 3 Lines 3 Lines ~ ~ ~ ~ VBL (BSE = 1, VBT = 7) B C UED10262 Figure 5 Vertical blanking pulse VBL when STE = 1 Semiconductor Group 25 1998-02-01 SDA 9362 Minimum Number of Lines per Field It defines the minimum number of lines per field for the vertical synchronisation. If the TV standard at the inputs VSYNC and HSYNC has less lines per field than defined by Minimum Number of Lines per Field no synchronisation is possible. The relationship between Minimum Number of Lines per Field and the minimum number of lines is given in the following table: Minimum Number of Lines per Field Minimum Number of Lines per Field 0 192 1 194 ... ... 127 446 128 448 ... ... 254 700 255 702 Maximum Number of Lines per Field It defines the maximum number of lines per field for the vertical synchronisation. If the TV standard at the inputs VSYNC and HSYNC has more lines per field than defined by Maximum Number of Lines per Field no synchronisation is possible. The relationship between Maximum Number of Lines per Field and the maximum number of lines is given in the following table: Maximum Number of Lines per Field Maximum Number of Lines per Field 0 702 1 192 2 194 ... ... 127 444 128 446 ... ... 255 700 Semiconductor Group 26 1998-02-01 SDA 9362 Mode Most Important V-Deflection Modes for 4:3 CRT Description Characteristics Notes VR1 NSA SRSE GBE STE SSE VR0 N0 Normal mode (for 4:3 source, Letterbox) with default settings Self adaptation scan start = line 9 start of V-ramp = line 9 scan time: depends on source signal guard band = 1.5 lines Mode after power on 00 0 0 0 0 0 N1 Normal mode (for 4:3 source, Letterbox) with user defined values Self adaptation scan start = Start Vertical Scan if (Start Reduced Scan>Start Vertical Scan) start of V-ramp = Start Reduced Scan else start of V-ramp = Start Vertical Scan scan time: depends on source signal guard band = Guard Band/2 [lines] Start of scan 00 adjustable start of V-ramp adjustable guard band adjustable 0 1 1 0 1 S0 Shrink mode 75% (for 16:9 source) with default settings Self adaptation scan start = line 9 start of reduced V-ramp = line 9 scan time: depends on source signal guard band = 1.5 lines 01 0 0 0 0 0 Start of scan 01 adjustable start of reduced V-ramp adjustable guard band adjustable 0 1 1 0 1 Self adaptation S1 Shrink mode scan start = Start Vertical Scan 75% (for 16:9 if (Start Reduced Scan>Start Vertical Scan) source) start of reduced V-ramp = with user Start Reduced Scan defined values else start of reduced V-ramp = Start Vertical Scan scan time: depends on source signal guard band = Guard Band/2 [lines] Semiconductor Group 27 1998-02-01 SDA 9362 Mode Most Important V-Deflection Modes for 16:9 CRT Description Characteristics Notes VR1 NSA SRSE GBE STE SSE VR0 N0 Normal mode (for 16:9 or 4:3 source) with default settings Self adaptation scan start = line 9 start of V-ramp = line 9 scan time: depends on source signal guard band = 1.5 lines Mode after power on 00 0 0 0 0 0 N1 Normal mode (for 16:9 or 4:3 source) with user defined values Self adaptation scan start = Start Vertical Scan if (Start reduced scan > Start vertical scan) start of V-ramp = Start reduced scan else start of V-ramp = Start vertical scan scan time: depends on source signal guard band = Guard Band/2 [lines] Start of scan 00 adjustable start of V-ramp adjustable guard band adjustable 0 1 1 0 1 Scan start = Z Zoom mode (number_of_lines - Vertical Scan)/2 +8 (for 4:3 source, scan time = Vertical Scan Letterbox) 00 Vertical scan controls zoom factor 0 X X 1 0 Scan start = SC Scroll mode (number_of_lines - Vertical Scan)/2 +8 + (for 4:3 source, Letterbox) Start vertical scan scan time = Vertical Scan Like above; 00 start vertical scan can be additionally used for adjustment of picture phase 0 X X 1 1 M Manual mode Scan start = Start Vertical Scan (for 4:3 source, scan time = Vertical Scan Letterbox) Scan start and scan time are separately adjustable 00 1 X X 1 X S2 Shrink mode 66% (for two 4:3 sources) with default settings Self adaptation scan start = line 9 start of reduced V-ramp = line 9 scan time: depends on source signal guard band =1.5 lines 10 0 0 0 0 0 S3 Shrink mode 50% (for two 16:9 sources) with default settings Self adaptation scan start = line 9 start of reduced V-ramp = line 9 scan time: depends on source signal guard band = 1.5 lines 11 0 0 0 0 0 Semiconductor Group 28 1998-02-01 SDA 9362 3 Absolute Maximum Ratings Parameter Operating temperature Storage temperature Junction temperature Soldering temperature Input voltage Output voltage Supply voltages Symbol TA Tstg Tj TS VI VQ VDD Supply total voltage differentials Total power dissipation Latch-up protection 1) Limit Values Unit min. max. -20 70 °C -40 125 °C 125 °C 260 °C Remark VSS - 0.3 V VDD + 0.3 V VSS - 0.3 V VDD + 0.3 V -0.3 6 V -0.25 0.25 V 0.85 W 100 mA Ptot -100 1) All inputs/outputs Between any internally non-connected supply pin of the same kind. All VDD(D) - and VDD(A) - Pins are connected internally by about 3 Ω The VSS(D) - Pins are connected internally by about 3 Ω Note: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions or at any other condition beyond those indicated in the operational sections of this specification is not implied. Semiconductor Group 29 1998-02-01 SDA 9362 3.1 Recommended Operating Conditions Parameter Symbol Supply voltages VDD Ambient temperature TA Limit Values Unit min. nom. max. 4.5 5 5.5 V -20 25 70 °C Remark For analog parameters 0°C TTL Inputs: CLL, HSYNC, VSYNC, TEST, SSD, HDEDEF, RESN H-input voltage L-input voltage VIH VIL 2.0 VDD V 0 0.8 V Input VPROT Threshold V1 1.4 1.5 1.6 V Threshold V2 0.9 1.0 1.1 V Threshold V1 3.9 4 4.1 V Threshold V2 2.1 2.4 2.7 V VREFP = 4 V VREFP = 4 V Input HPROT VREFP = 4 V VREFP = 4 V Input IBEAM L-input voltage VIL Full range input voltage 2 V 3 V VREFP = 4 V VREFP = 4 V Reference Voltage Input Pins (Internal Voltage Ref Control Byte Reg 48H = 00000011) VREFP input voltage VREFH input voltage VREFL input voltage VREFN input voltage Input Φ2 VVREFP VVREFH VVREFL VVREFN L-input voltage VIL VIH H-input voltage 4 V 2.5 V 1.2 V 0 V 0 0.7 V 2.0 VDD V 100 20000 ns VREFP = 4 V VREFP = 4 V Input HSYNC Pulse width high Setup time Hold time Input capacitance Semiconductor Group tSU tH CI 7 ns 6 ns 10 30 pF 1998-02-01 SDA 9362 3.1 Recommended Operating Conditions (cont’d) Parameter Symbol Limit Values min. nom. Unit Remark max. Input VSYNC Pulse width high 100 100/fH ns NI = 0 Pulse width high 1.5/fH 100/fH NI = 1 Input capacitance CI 10 pF 30 MHz 10 pF Input CLL Input frequency Input capacitance fI CI 25 27 Quartz Oscillator Input / Output X1, X2 Crystal frequency 12 Crystal resonant impedance MHz 25 External capacitance 27 Fundamental crystal type Ω pF See application information I2C Bus (All Values are Referred to min.(VIH) and max.(VIL)) H-input voltage L-input voltage SCL clock frequency Rise times of SCL, SDA VIH VIL 3 VDD V 0 1.5 V fSCL tR 0 400 kHz 0.3 µs 0.3 µs Fall times of SCL, SDA tF Set-up time DATA tSU;DA tHD;DA CL Hold time DATA Load capacitance Semiconductor Group 100 ns 0 ns 400 31 fSCL = 400 kHz pF 1998-02-01 SDA 9362 3.2 Characteristics (Assuming Recommended Operating Conditions) Parameter Symbol Limit Values min. Average supply current ICC Unit nom. max. 50 100 mA 25 mA 0.4 V Standby supply current Remark Output Pins: VBLE, SW1, SW2 Output low level Output high level VOL VOH V IO = 1 mA IO = -1 mA 0.6 V IO = 6 mA 1 V IO = 1 mA | IO | = 100 µA V IO = -1 mA 2.8 Input / Output SDA Output low level VOL Output SCP Output low level Output HBL level Output high level VOL VOHBL VOH 0 VDD / 2 VDD / 2 VDD / 2 -0.4 V +0.4 V 4.0 VDD DAC Output E/W DAC resolution 10 Bit Linear range: 100 ... 900 DAC output low 1.45 V Input data = 1001) DAC output high 3.48 V Input data = 9001) Load capacitance 30 CL pF kΩ Output load 20 Zero error -2 % 2% DAC output voltage = 2.5 V2) Gain error -5 % 5% 2) INL -0.2 % 0.2 % 2) DNL -0.1 % 0.1 % 2) 1) VREFH = 2.5 V, VREFL = 1.2 V 2) VREFH = 2.5 V, VREFL = 1.2 V, Input range = 100 ... 900 Semiconductor Group 32 1998-02-01 SDA 9362 3.2 Characteristics (Assuming Recommended Operating Conditions) (cont’d) Parameter Symbol Limit Values min. nom. Unit Remark max. DAC Output VD+, VDDAC resolution 14 Bit Linear range: 1500 ... 15000 DAC output low (VD-) 1.44 V Input data = 15001) DAC output high (VD-) 3.58 V Input data = 150001) DAC output low (VD-) - (VD+) -2.12 V Input data = 15001) DAC output high (VD-) - (VD+) 2.16 V Input data = 150001) Load capacitance 30 CL pF kΩ Output load 20 Zero error -1 % 1% (VD-) - (VD+) = 0 V2) Gain error -5 % 5% 2) INL -0.5 % 0.5 % 2) DNL Monotonous 1) VREFH = 2.5 V, VREFL = 1.2 V 2) VREFH = 2.5 V, VREFL = 1.2 V, Input range = 1500 ... 15000 Guar. by design Reference Output VREFP (Adjust. by Reg 48H, Bit D7 ... D2) (Reg 48H, Bit D1 = 0, Bit D0 = 0) Output voltage min 4.0 Output voltage max Output current 4.0 IQ -50 V Bit D7 ... D2 = 100000 V Bit D7 ... D2 = 011111 0 µA 2.6 V VREFP = 4 V 1.3 V VREFP = 4 V V IO = 8 mA IO = -8 mA Reference Output VREFH (Reg 48H, Bit D1 = 0) Output voltage VQ 2.4 2.5 Reference Output VREFL (Reg 48H, Bit D1 = 0) Output voltage VQ 1.1 1.2 VOL VOH 0 1 VDD VDD Output HD Output low level Output high level -1 V Semiconductor Group 33 1998-02-01 SDA 9362 4 Application Information VB SCP SCAN VPROT HPROT φ2 EHT ABL TV Contr. Ι2C + NVM H-Coil HD 27 pF X1 24.576 MHz SDA 9362 X2 E/W 27 pF + VSYNC VD- HSYNC VD+ + Source Sel Synch Sep _ LF V-Coil ABL D/A PWM RESN VPROT UES10263 Figure 6 Semiconductor Group 34 1998-02-01 SDA 9362 5 Waveforms 5.1 VD- Output Voltage, 4/3-CRT and 16/9-Source VVDV0(max) 1 V 16/9 2 V V0(min) 2 1 V 4/3 = 1 VV 16/9 2 0.75 2 V 63 SRS 0 SRSE = 1 n z (Line No.) Start Reduced Scan (SRS) selectable (line 0, 2...63) UED10264 Figure 7 Semiconductor Group 35 1998-02-01 SDA 9362 5.2 Function of H,V Protection HPON2) I2C Bus VPON2) I2C Bus Continuous blanking 0 0 H, V operation 1) 0 0 3 EHT overvoltage Continuous blanking after t2 1 after t2 0 4 Continuous H operation blanking V short after t0 if failure SSC = 0 0 0 V longer failure H off after t1 Continuous blanking after t0 if SSC = 0 0 1 after t1 EHT short overvoltage Continuous blanking after t2 1 after t2 1 after t1 HPROT 1 2 VPROT V1 V2 Start up or V1 V2 or or t 0 < t <_ t 1 5 Mode or or t <t1 or 6 SCP t <t1 t0 = 2 / fv ... 3 / fv t1 = 64 / fv ... 128 / fv t2 = 1 / fv ... 2 / fv 1) Depends on 2C-control items Ι 2) HPON or VPON = 1:HD = 0(OFF) Semiconductor Group 36 1998-02-01 SDA 9362 5.3 Power On/Off Diagram Supply Voltage PowerOnReset 32 Cycles 32 Cycles X1, X2 SSD = 0: ~ 250 µs1) SSD = 1: ~ 380 µs1) SSD = 0: ~ 250 µ s1) SSD = 1: ~ 380 µ s1) HD Ι 2 C Registers 01 H ...1C H , 1F H Programmable Ι 2 C Bus Tristate Ι 2 C Registers 01 H ...1C H , 1F H Programmable Ready Tristate Programmable Default Ready Tristate VREFP , VREFH, VREFL Protection Ι 2 C Reg. 00 H, 1D H, 1E H, 44 H ... 48 H Active Inactive Default Ι 2 C Reg. 01H ...1C H , 1F H Default Programmable Default Programmable Programmable Default Default CLL ~ 42 Cycles CPU Active Inactive Power On 1) ~ 42 Cycles Glitch For low FH-range this time has to be multiplied by 2 Power Off UET10275 Figure 8 Semiconductor Group 37 1998-02-01 SDA 9362 5.4 Standby Mode, RESN Diagram Standby RESN HD φ2-Loop 32 x 1 Cycles φ2-Loop Free Run SSD = 0: ~ 250 µ s1) SSD = 1: ~ 380 µ s1) ~ 42 CLL Cycles Free Run ~ 42 CLL Cycles Active CPU VREFP , VREFH, VREFL Protection Inactive Active Inactive Active Inactive Ι 2 C Bus Ready Ι 2 C Reg. Programmable 01H ...1C H , 1F H Default Values Ι 2 C Reg. 00 H, 1D H, 1E H 44 H ... 48 H Programmable Tristate Programmable Default Values Standby Mode 1) Default Values Ready Programmable Programmable External Reset For low FH-range this time has to be multiplied by 2 UET10276 Figure 9 Semiconductor Group 38 1998-02-01 SDA 9362 6 Package Outlines H 0.8 7˚ max. 0.15 +0.08 -0.02 2.45 max. 2 +0.1 -0.05 0.25 min. P-MQFP-44-2 (Plastic Metric Quad Flat Package) 0.88 ±0.15 0.3 +0.15 C 8 13.2 10 0.1 0.2 M A-B D C 44x 0.2 A-B D 44x 1) 0.2 A-B D H 4x D A 44 1 Index Marking 1) 13.2 10 1) B 0.6 x 45˚ Does not include plastic or metal protrusions of 0.25 max per side GPM05622 Figure 10 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group Dimensions in mm 39 1998-02-01