CXA1386P/K
8-bit 75MSPS Flash A/D Converter
Description
The CXA1386P/K are 8-bit high-speed flash A/D
converter ICs capable of digitizing analog signals at
the maximum rate of 75MSPS. The digital I/O levels
of these A/D converters are compatible with the
ECL 100K/10KH/10K.
The CXA1386P/K is pin-compatible with the
earlier
models
CXA1056P/K,
CXA1016P/K,
respectively. They can be replaced by the
CXA1386P/K without any design changes, in most
cases. Compared with the earlier models, these
new models have been greatly improved in
performance, by incorporating advanced process,
new circuit design and carefully considered layout.
Features
• Differential linearity error: ±1/2LSB or less
• Integral linearity error: ±1/2LSB or less
• High-speed operation with maximum conversion
rate of 75MSPS (Min.)
• Wide analog input bandwidth: 150MHz (Min. for
full-scale input)
• Low Power consumption: 580mW (Typ.)
• Single power supply: –5.2V
• Low input capacitance: 17pF (Typ.)
• Built-in integral linearity conpensation circuit
• Low error rate
• Operable at 50% clock duty cycle
• Good temperature characteristics
• Capable of driving 50Ω loads
CXA1386P
28 pin DIP (Plastic)
CXA1386K
44 pin LCC (Ceramic)
Structure
Bipolar silicon monolithic IC
Applications
• Digital oscilloscopes
• HDTV (high-definition TVs)
• Other apparatus requiring high-speed A/D
conversion
1
28 AVEE
2
27 VRT
DGND
3
26 AVEE
(LSB) D0
4
25 AGND
D1
5
24 VIN
D2
6
23 AGND
D3
7
D4
8
D5
9
D6 10
(MSB) D7 11
CXA1386P
22 VRM
21 AGND
20 VIN
19 AGND
18 AVEE
DGND 12
17 VRB
DVEE 13
16 CLK
MINV 14
15 CLK
39
AVEE 40
AVEE 41
VRT 42
43
44
AVEE
1
2
3
LINV
4
DVEE
5
DGND1
6
DGND2
7
38 37 36 35 34 33 32 31 30 29
CXA1386K
28
27
26
25
24
23
22
21
20
19
18
AVEE
AVEE
VRB
CLK
CLK
MINV
DVEE
DGND1
8 9 10 11 12 13 14 15 16 17
(LSB) D0
D1
D2
D3
D4
D5
D6
(MSB) D7
DGND2
LINV
DVEE
AGND
VIN
AGND
VRM
AGND
VIN
AGND
Pin Configuration
Pins with name are NC pins (not connected).
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E90114C54-ST
CXA1386P/K
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
AVEE, DVEE
• Analog input voltage
VIN
• Reference input voltage VRT, VRB, VRM
I VRT – VRB I
• Digital input voltage
CLK, CLK, MINV, LINV
I CLK – CLK I
• VRM pin input current
IVRM
• Digital output current
ID0 to ID7
• Storage temperature
Tstg
Recommended Operating Conditions
• Supply voltage
AVEE, DVEE
AVEE – DVEE
AGND – DGND
• Reference input voltage VRT
VRB
• Analog input voltage
VIN
• Pulse width of clock
TPW1
TPW0
• Operating temperature
Tc (CXA1386K)
Ta (CXA1386P)
Min.
–5.5
–0.05
–0.05
–0.1
–2.2
VRB
6.6
6.6
–20
–20
–7 to +0.5
–2.7 to +0.5
–2.7 to +0.5
2.5
–4 to +0.5
2.7
–3 to +3
–30 to 0
–65 to +150
V
V
V
V
V
V
mA
mA
°C
Typ. Max.
–5.2 –4.95
0
+0.05
0
+0.05
0
+0.1
–2.0 –1.8
VRT
Unit
V
V
V
V
V
–2–
+100
+75
ns
ns
°C
°C
CXA1386P/K
Block Diagram
MINV
r1
VRT
Comparator
r/2
r
r
r
r
1
2
•
•
•
63
D7 (MSB)
D6
64
VIN
r
r2
r
VRM
r
r
r
127
128
OUTPUT
r
ENCODE LOGIC
r
D5
65
•
•
•
126
129
•
•
•
191
D1
D0 (LSB)
r
r
r
r3
r/2
193
•
•
•
254
255
VRB
CLK
CLK
D3
D2
192
VIN
D4
CLOCK
DRIVER
LINV
–3–
CXA1386P/K
Pin Description and I/O pin Equivalent circuit
Pin No
LCC
31, 33,
35, 37
27, 28,
40, 41,
44
DIP
Symbol
19, 21,
AGND
23, 25
18, 26,
28
AVEE
I/O
—
—
Standard
voltage
level
Equivalent circuit
Description
0V
Anlog GND.
Used as GND for input
buffers and latches of
comparators.
Isolated from DGND or
DGND 1/2.
–5.2V
Analog VEE
–5.2V (Typ.).
Internally connected
with DVEE
(resistance: 4 to 6Ω).
Ceramic chip
capacitors of at least
0.1µF should be used
to connect to AGND
and be placed near
the pins.
DGND (DGND1)
23
16
CLK
CLK input
r
r
r
CLK
I
22
15
ECL
r
CLK
CLK
r
DVEE
r
Input complementary
to CLK.
With open connection,
kept at threshold
voltage (–1.3V).
Device is operable
without CLK input, but
use of complementary
inputs of CLK and CLK
is recommended to
obtain the stable highspeed operation.
—
3, 12
DGND
—
0V
Digital GND (Used for
internal circuits and
output transistors)
5, 19
—
DGND1
—
0V
Digital GND (Used for
internal circuits)
6, 16
—
DGND2
—
0V
Digital GND (Used for
output buffers)
–4–
CXA1386P/K
Pin No
LCC
DIP
Symbol
4, 20
2, 13
DVEE
8
4
D0
9
5
D1
10
6
D2
11
7
D3
12
8
D4
13
9
D5
14
10
D6
15
11
D7
I/O
—
Standard
voltage
level
Equivalent circuit
Description
Digital VEE
Internally connected
with AVEE
(resistance: 4 to 6Ω)
Ceramic chip
capacitors of at least
0.1µF should be used
to connect to DGND
and be placed near the
pins.
–5.2V
DGND (DGND2)
Di
O
Data outputs.
External pull-down
resistors are required.
ECL
MSB of data outputs.
External pull-down
resistor is required.
DVEE
Input pin for D0 (LSB)
to D6 output polarity
inversion (see output
code table).
With open connection,
kept at "L" level.
DGND (DGND1)
3
1
LINV
I
ECL
r
LINV
or
MINV
21
14
MINV
LSB of data outputs.
External pull-down
resistor is required.
I
ECL
DVEE
–5–
r
r
r
–1.3V
Input pin for D7 (MSB)
output polarity
inversion (see output
code table).
With open connection,
kept at "L" level.
CXA1386P/K
Pin No.
LCC
DIP
Symbol
I/O
Standard
voltage
level
Equivalent circuit
Description
AGND
Analog input pins.
These two pins must
be connected
externally, since they
are not internally
connected.
See Application Note
for precautions.
VIN
32, 36
20, 24
VIN
I
VRT
to
VRB
VIN
AVEE
VRT
26
17
VRB
I
r1
–2V
r/2
r
Comparator
1
Comparator
Comparator
2
•
•
•
127
Comparator
128
Comparator
129
Comparator
130
•
•
•
•
•
•
•
255
r
r
34
22
VRM
I
VRB/2
VRM
r2
r
Reference voltage
(bottom)
Typically –2V
A ceramic capacitor of
at least 0.1µF and a
tantalus capacitor of at
least 10µF should be
used to connect to
AGND and be placed
near the pins.
Reference voltage mid
point be used as a pin
for integral linearity
compensation
r
r
42
27
VRT
I
r
0V
Comparator
VRB
1, 2,
7, 17,
18, 24,
25, 29,
30, 38
39, 43
NC
—
r3
r/2
Reference voltage
(top) Typically 0V
When a voltage
different from AGND is
applied to this pin, a
ceramic capacitor of at
least 0.1µF and a
tantalus capacitor of at
least 10µF should be
used to connect to
AGND and be placed
near the pins.
Unused pins
No internal connections
have been made to
these pins.
Connecting them to
AGND or DGND on PC
board is recommended.
—
–6–
CXA1386P/K
Electrical Characteristics
Item
(Ta = 25°C, AVEE = DVEE = –5.2V, VRT = 0V, VRB = –2V)
Symbol
Resolution
n
DC characteristics
Integral linearity error
Differential linearity error
EIL
EDL
Analg input
Analog input capacitance CIN
Analog input resistance
RIN
Input bias current
IIN
Reference inputs
Reference resistance
Offset voltage
VRT
VRB
Digital inputs
Logic H level
Logic L level
Logic H current
Logic L current
Input capacitance
Condition
Fc = 75MSPS
Fc = 75MSPS
±0.3
±0.3
VIN = –1V + 0.07Vrms
17
390
VIN = –1V
75
8
0
Input connected to –0.8V
Input connected to –1.6V
110
18
10
0
–50
Digital outputs
Logic H level
Logic L level
Output rising time
Output falling time
VOH
VOL
Tr
Tf
RL = 620Ω to DVEE
RL = 620Ω to DVEE
RL = 620Ω to DVEE, 20% to 80%
RL = 620Ω to DVEE, 80% to 20%
DG
DP
VIN = 2Vp-p
Input frequency at –3dB
Input = 1MHz, FS
Clock = 75MHz
Input = 18.75MHz, FS
Clock = 75MHz
Input = 18.749MHz, FS
Error > 16LSB
Clock = 75MHz
NTSC 40IRE mod. ramp,
Fc = 75MSPS
Dynamic characteristics
Input bandwidth
S/N ratio
Error rate 10–9 TPS∗1
±0.5
±0.5
LSB
LSB
200
pF
kΩ
µA
155
32
24
Ω
mV
mV
–1.50
50
50
V
V
µA
µA
pF
75
4.0
6.6
6.6
–1.62
0.9
2.1
150
–150
∗1 TPS: Times Per Sample
2
∗2 Pd = IEE · VEE + (VRT – VRB)
RREF
–7–
V
V
ns
ns
46
dB
40
dB
10–9
}
MSPS
ps
ns
ns
ns
ns
MHz
{
IEE
Pd
9.0
–1.03
{
{
Error rate
10
3.0
6.5
Unit
bits
7
Fc
Taj
Tds
Tdo
TPW1
TPW0
Power supply
Supply current
Power consumption∗2
Max.
–1.13
Switching characteristics
Maximum conversion rate
Aperture jitter
Sampling delay
Output delay
H pulse width of clock
L pulse width of clock
Differential gain error
Differential phase error
Typ.
8
RREF
EOT
EOB
VIH
VIL
IIH
IIL
Min.
TPS∗1
1.0
0.5
%
deg
–104
580
mA
mW
CXA1386P/K
Output Code Table
VIN∗
MINV 1
LINV 1
Step
D7
0V
0
1
–1V
127
128
254
255
–2V
0
1
D0
D7
1
0
D0
0
0
D7
D0
D7
D0
0 0 0 ······ 0 0
1 0 0 ······ 0 0
0 1 1 ······ 1 1
1 1 1 ······ 1 1
0 0 0 ······ 0 0
0 0 0 ······ 0 1
:
:
0 1 1 ······ 1 1
1 0 0 ······ 0 0
:
:
1 1 1 ······ 1 0
1 1 1 ······ 1 1
1 0 0 ······ 0 0
1 0 0 ······ 0 1
:
:
1 1 1 ······ 1 1
0 0 0 ······ 0 0
:
:
0 1 1 ······ 1 0
0 1 1 ······ 1 1
0 1 1 ······ 1 1
0 1 1 ······ 1 0
:
:
0 0 0 ······ 0 0
1 1 1 ······ 1 1
:
:
1 0 0 ······ 0 1
1 0 0 ······ 0 0
1 1 1 ······ 1 1
1 1 1 ······ 1 0
:
:
1 0 0 ······ 0 0
0 1 1 ······ 1 1
:
:
0 0 0 ······ 0 1
0 0 0 ······ 0 0
1 1 1 ······ 1 1
0 1 1 ······ 1 1
1 0 0 ······ 0 0
0 0 0 ······ 0 0
∗ VRT = 0V, VRB = –2V
Timing diagram
Tds
N
N+1
Analog input
Tpw1
N+2
Tpw0
CLK
CLK
80%
N –1
Digital output
20%
Tdo
Tr
–8–
N
80%
N+1
20%
Tf
CXA1386P/K
Electrical Characteristics Test Circuit
Maximum conversion rate test circuit
Signal
Source
Vin
fCLK
– 1kHz
4
2Vp-p Sin Wave
8
CXA1386
P/K
CLK
A
ECL
Latch
B
CLK
Comparator
A> B
Pulse
Counter
ECL
Latch
+
DATA 16
Signal
Source
1/4
fCLK
Differential gain error test circuit
Differential phase error test circuit
(CX20202A-1)
VIN
DUT
CXA1386
P/K
Amp
10Ω
CLK
8
ECL
Latch
8
10bit
D/A
CLK
NTSC
Signal
Source
Delay
VBB
Vector
Scope
SG (CW)
50
DG.DP
Integral linearity error test circuit
Differential linearity error test circuit
+V
S2
S1: ON when A < B
S2: ON when A > B
S1
–V
VIN
DUT
CXA1386
P/K
A< BA> B
Comparator
8
A8
to
A1
A0
B8
to
B1
B0
"0"
8
Buffer
"1"
DVM
8
CLK (75MHz)
Controller
–9–
00000000
to
11111110
CXA1386P/K
Power Supply Current Test Circuit
Analog input bias current test circuit
–1V
A
IIN
IIN
–1V
1
2
27
3
26
4
25
5
24
6
23
7
A
28
CXA1386P
39
40
41
42
43
44
1
2
3
4
5
6
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
–2V
38 37 36 35 34 33 32 31 30 29
CXA1386K
28
27
26
25
24
23
22
21
20
19
18
–2V
8 9 10 11 12 13 14 15 16 17
7
A IEE
A IEE
–5.2V
–5.2V
Sampling delay test circuit
Aperture jitter test circuit
Aperture jitter test method
0V
–1V
VIN
37.5MHz
–2V
Amp
OSC1
φ: Variable
CLK
VIN
fr
CLK
CXA1386
P/K
8
VIN
129
128
127
126
125
CLK
Aperture jitter
∆v
∆t
Logic
Analizer
t
1024
samples
OSC2
ECL
Buffer
37.5MHz
σ (LSB)
Aperture jitter is defined as follows:
Taj = σ/
∆υ
256
= σ/(
∆t
2
× 2πf ),
Where σ (unit: LSB) is the deviation of the output codes when the input
frequency is exactly the same as the clock and is sampled at the
largest slew rate point.
– 10 –
CXA1386P/K
8bit 75MSPS ADC and DAC Evaluation Board
It is necessary to equip "the CXA1396D/P EVALUATION BOARD WITH DAC" with "A1396D – A1386P
ADAPTER" in order to evaluate CXA1386P.
In addition to indispensable features such as the reference voltage generator, this tool equips two sets of
analog inputs (the direct input and the buffer amplifier input), the input voltage offset generator, the clock
decimator, the output data latches, the 10-bit high-speed DAC, and the 20-pin cable connector for digital
outputs. This evaluation board provides full performance of the CXA1386P and it is designed to facilitate
evaluation.
Features
Resolution: 8bits
Maximum conversion rate: 75MSPS
Supply voltage: +5.0V, –5.2V, –2.0V
Two analog inputs (Direct input, buffer amplifier input)
Clock level converter: Sine wave to ECL level signal
Reference voltage adjustment circuit for the A/D converter
Built-in clock frequency decimation circuit: (1/1 to 1/16)
Fig. 1. Block Diagram
–5.2V (A)
H
L
VRB
–2V
VR2
(2k)
–5.2V (A)
SW1
VR3
(1k)
DIGITAL OUT
(CONNECTOR)
LINV MINV
Vin
OFFSET
VR1
(2k)
SW2
VRB
J1
A
1k
8
VRM
DATA
LATCH
8
BUFFER
(D7 to D0)
8
CXA1386P
B
CLK
C
AMP.IN
240
CLK
X (–2)
51
Vin
(D7 to D0)
D
8
2 (CLK.CLK)
51
DIR.IN
0.1µ
D/A
CONVERTER
DECIMATOR
CLK
CLK
SW3
1/1 to 1/16
+5V
–5.2V (A)
AGND
–5.2V (D)
– 11 –
DGND
–2V (D)
D/A OUT
CXA1386P/K
Supply Current
Item
Min.
–5.2V
+5.0V
–2.0V
Typ.
Max.
Unit
0.85
15
0.45
1.0
30
0.6
A
mA
A
(Note: Supply current –2.0V is the value when Rn10, Rn11 and Rn12 are not mounted.)
Analog Input (DIR. IN, AMP. IN)
Item
Min.
Input voltage (DIR. IN)
(AMP. IN)∗1
Input impedance
Typ.
–2.0
–0.5
Max.
Unit
0
+0.5
V
V
Ω
Max.
Unit
50
(∗1: Adjustable by VR1)
Clock Input (CLK)
Item
Min.
Input voltage
(Peak to Peak)
Input impedance
Typ.
2.0
Vp-p
50
Ω
Digital Output (D0 to D7)
ECL 10KH level
Clock Output
ECL 10KH level, complementary output
Output Code Table
VIN
MINV
LINV
0
0
0
1
1
0
1
1
0V
:
:
:
:
:
:
:
:
–2V
1 1 1 ······ 1 1
1 1 1 ······ 1 0
:
:
1 0 0 ······ 0 0
0 1 1 ······ 1 1
:
:
0 0 0 ······ 0 1
0 0 0 ······ 0 0
1 0 0 ······ 0 0
1 0 0 ······ 0 1
:
:
1 1 1 ······ 1 1
0 0 0 ······ 0 0
:
:
0 1 1 ······ 1 0
0 1 1 ······ 1 1
0 1 1 ······ 1 1
0 1 1 ······ 1 0
:
:
0 0 0 ······ 0 0
1 1 1 ······ 1 1
:
:
1 0 0 ······ 0 1
1 0 0 ······ 0 0
0 0 0 ······ 0 0
0 0 0 ······ 0 1
:
:
0 1 1 ······ 1 1
1 0 0 ······ 0 0
:
:
1 1 1 ······ 1 0
1 1 1 ······ 1 1
– 12 –
CXA1386P/K
Fig. 2. Timing Chart
N
A/D input pin
Vin
(DIR. IN, AMP. IN)
N+1
PCB input pin
CLK
CLK
A/D clock
CLK
A/D output
D7 to D0
N –1
N
D7 to D0
PCB output pin
(For 1/1 frequency division)
N –2
N –1
N
Tdh
1.8ns
(Typ)
CLKN
PCB output pin
CLK
(For 1/1 frequency division)
PCB output pin DATA OUT
(For 1/2 frequency division)
N –4
N –2
N
Tdh
1.8ns
(Typ)
CLKN
PCB output pin
CLK
(For 1/2 frequency division)
Adjustment Methods and Notes on Operation
1) Vin Offset (VR1)
The volume to adjust the signal range (0V center assumed) with the A/D converter input range when a
waveform is input through AMP. IN.
2) A/D Full Scale (VR2)
The volume to adjust A/D converter VRB voltage.
3) Linearity (VR3)
The volume to adjust VRM (linearity) voltage.
– 13 –
CXA1386P/K
4) D/A Full Scale (VR4)
The volume to adjust D/A output full scale (–1V)
5) J1 (input selection)
A: Shorts to adjust VRM voltage.
B: Shorts to supply DC voltage to Vin.
C: Shorts to select AMP.IN input.
D: Shorts to select DIR. IN input.
[Jumper Poisition at shipment]
J1
A
B
C
D
6) SW1
The switch for LINV High/Low
7) SW2
The switch for MINV High/Low
8) SW3 (Decimation)
The switch to select clock frequency decimation.
Switch position: decimation ratio
0: 1/1
1: 1/2
2: 1/4
3: 1/8
4: 1/16
9) SW4 (D/A INV)
The switch for D/A converter output inversion.
10) Rn10, Rn11 and Rn12 are not mounted at shipment. They are not required during evaluation.
11) Waveform probe pins P5 and P8 through P28 are devised to facilitate GND connection in order to reduce
the distortion. As shown in the diagram below, the distance between the probe point and the GND is 300
mils, and there is φ1.2mm throughhole at each. The signal and GND locations are suit for a Tektronix GND
tip (part number 013-1185-00).
φ1.2mm
GND
Probe point
300mil
Fig. 3.
12) D/A converter (IC13) input data (waveform probe pins P21 through P28) are the complementary signals of
the decimated A/D converter outputs. Those are inverted again in the D/A converter so that the direction of
reproduced waveform can agree with the A/D input signal converter.
13) The part number of the digital output connector is KEL 8830E-020-170S. A corresponding connector and
cable assembly is JUNKOSHA KB0020MCG50BI.
– 14 –
R1
51
CLK
DIR.IN
DGND
AGND
C1
0.1µ
R2
240
AGND AGND
C4
3.3µ
4
C3
IC1-1
TL4558 0.1µ
AGND
R7
1k
Q1
2SA970
AGND
2
3
DGND
C2
0.1µ
R3
51
R10 R11
510 43
Aout
Cout 15
Bin 10
Bin_ 9
8 VEE
VBB 11
Cin_ 12
Cin 13
Cout_ 14
7 Bout
Bout_
5 Ain
4 Ain_
6
R13
1k
VCC2 16
AGND AGND
2 Aout_
3
–5.2V
(D)
DGND
6
AGND AGND
C12
0.1µ
P1
AGND
VR3
1k
AGND
AGND
C20
10
C16
0.1µ
Rn1
Rn1
51
Rn1
51
Rn1
51
Rn1
51
DGND
C10
0.1µ
AGND
C15
1µ
41 VRT
C14
0.1µ
Q3
Q2
D2
D3
8 VEE
7 S2
6
5
4 Cout_
3
2
–5.2V (D)
DGND
1 VCC1
S1 9
Cin_ 10
D1 11
D0 12
CLK 13
Q0 14
Q1 15
VCC2 16
FERRITE BEAD
AVEE 1
NC 2
40 NC
42 NC
LINV 3
DVEE 4
DGND1 5
39 AVEE
38 AVEE
D0 7
D1 8
D2 9
D3 10
D4 11
D5 12
D6 13
D7 14
DGND2 15
DGND1 16
DVEE 17
MINV 18
NC 19
CLKN 20
CLK 21
DGND2 6
CXA1396D – CXA1386P ADAPTER
37 NC
36 NC
35 AGND
34 VIN
33 AGND
32 VRM
31 AGND
30 VIN
29 AGND
28 NC
27 NC
26 AVEE
25 AVEE
24 NC
23 VRB
22 NC
DGND DGND
C13
0.1µ
AGND
AGND
–5.2V (A)
AVEE P3
AGND P4
VIN P5
C17
0.1µ
AGND
–5.2V (A)
C18
0.1µ
C19
0.1µ
C5
0.1µ –2V
(D)
DGND
DGND
J1
D
C
B
A
Linearity
VRB P2
4
IC4
CLC404AJP
R12
C6
51
1µ
AGND
C11
0.1µ
7
C7
1µ
1 VCC1
–5.2V (A)
AGND
AGND
+5V (A)
–5.2V (A)
VRM
C8
0.1µ
6 8
7
5
4 IC1-2
IC3
TL4558
TL431CP
AGND
R8
510
VR1
2K
R4
6 122k
2
3
AGND AGND
AMP.IN
R6
240
Vin Offset
–5.2V (A)
R5/11k
R9
1.3k
AGND
A/D Full Scale VR2
2k
C9
0.1µ
IC2 : 10H116
FERRITE
BEAD
IC5 : 10H136
P17
P6
DGND
C37
0.1µ
–2V (D)
R14
51
DGND
H
D1
SW1
LINV
C24
0.1µ
DGND
–5.2V (A)
1
DGND DGND
C22
C21 0.1µ
0.1µ
Rn2
51
Rn2
51
Rn2
51
Rn2
51
VEE
A
X0
X1
X2
X3
Enable_
–5.2V (D)
8
7
6
5
4
3
VCC
–5.2V (D)
R15
330
DGND 2
DGND Rn2
C23
0.1µ
L
D3
–2V (D)
D2
C26
1µ
SW2
MINV
–5.2V (D)
DGND
DVEE
–5.2V (D)
DGND
C25
0.1µ
DGND
C27
0.1µ
C25
0.1µ
P9
P8
CLK
CLKN
D7
D1
D0
DGND
C30
0.1µ
Rn4
Rn3
DGND
D1
D0
8 VEE
7 D2
6
5
Q1
D1
D0
8
VEE
7 D2
6
5
4 Q2
3
Q0
1 VCC1
2
Aout
Bout_
DGND –5.2V (D)
8 VEE
7 Bout
6
5 Ain
4 Ain_
3
2 Aout_
1 VCC1
–5.2V (D)
DGND
DGND
C24
0.1µ
C34
0.1µ
SW3
Decimation
DGND
C35
0.1µ
Rn3
75
Rn3
75
Rn3
75
DGND
DGND
Q1
Q0
4 Q2
3
2
1 VCC1
–5.2V (D)
DGND
C36 C26
0.1µ 0.1µ
Rn4
75
Rn4
75
Rn4
75
Rn4
75
Rn3
75
DGND
C31
0.1µ
–2V (D)
R18
51
–2V (D)
P11
P13
D3
–2V (D)
D5
P15
P17
DGND
P10
P12
D2
D4
P14
P16
DGND
C29
0.1µ
DGND
B 9
C 10
X4 11
X5 12
X6 13
X7 14
Z 15
VCC1 16
D6
C22
R16
0.1µ
51
–2V (D)
R17
51
–2V (D)
C37
0.1µ
C38
0.1µ
5
4
3
2
1
Bin_ 9
Bin 10
VBB 11
Cin_ 12
Cin 13
Cout_ 14
Cout 15
VCC2 16
CLK 9
DGND
–2V
(D)
R20
51
DGND
DGND
VEE
Bin
Bout
VCC2 16
VEE
Bin
Bout
Aout
Ain
–2V (D)
C52
0.1µ
–2V (D)
51
Rn7
51
Rn7
51
Rn7
DGND
14 CLK
DGND
C51
0.1µ
NC 19
OUT 20
NC 21
NC 22
NC 23
NC 24
C46
0.1µ
DGND
AGND
C57
33µ
AGND
AGND
DGND
–5.2V (D)
R23
3.2k
D6
H
D5
AGND
AGND
DGND
D/A OUT
–2V (D)
DGND
–5.2V (D)
–5.2V (A)
AGND
+5V (A)
DGND
–5.2V (A)
C50
33µ
DGND
C54
33µ
P29 –2V (D)
P30 DGND
C55
33µ
20
DGND
16
DGND
18
DGND
14
DGND
DIGITAL OUT
P31 –5.2V (D)
SW4
D4
D/A INV L
C47
0.1µ
15
D7
P32 –5.2V (A)
C56
33µ
6
DGND
4
DGND
2
DGND
8
DGND
10
DGND
12
11
D5
DGND
7
D3
3
D1
19
CLKN
17
CLK
13
D6
9
D4
5
D2
1
D0
P33 AGND
R22 C49
240 0.1µ
–5.2V (D) DGND
DGND
DVEE 15
INV 16
DGND 17
CONNECTOR
KEL: 8830E-020-170S
(TOP VIEW)
P34 +5V (A)
DGND
75
Rn10
75
Rn10
75
Rn10
75
Rn10
Rn10
51
Rn11
51
Rn11
D/A Full Scale
IC14
NC 25
TL431CP
AVEE 26
VREF
51
Rn11
51
Rn11
R21
C48
0.1µ VR4 1k
27
2k
AGND1 18
13 CLKN
11 NC
12 NC
10 LSB
9 D9
8 D8
7 D7
6 D6
5 D5
4 D4
3 D3
2 D2
51
Rn11
AGND
–2V (D)
–2V (D)
DGND
1 MSB AGND2 28
51
Rn7
75
Rn8
75
Rn8
75
Rn8
75
Rn8
Rn8
75
75
Rn9
75
Rn9
75
Rn9
Rn9
Rn9
DGND –2V (D)
Rn7
DGND
C43
0.1µ
CLK P19
CLKN P20
DGND
C44
0.1µ
D0 P21
D1 P22
D2 P23
D3 P24
D4 P25
D5 P26
D6 P27
D7 P28
C45
0.1µ
Dout 9
Cin 10
Cout 11
COM
IN 12
Din 13
Bout_ Cout_ 14
Aout_ Dout_ 15 DGND
VCC1
Dout 9
Cin 10
Cout 11
COM
IN 12
Din 13
Aout
Ain
51
Rn12
51
Rn12
51
Rn12
DGND
Rn12
Rn12
–2V (D)
DGND
C53
0.1µ
Bout_ Cout_ 14
–5.2V (D)
8
6
C39
0.1µ
DGND
7
DGND
C40
0.1µ
VCC2 16
Aout_ Dout_ 15
VCC1
–5.2V (D)
D3 10
DGND
–2V (D)
Rn5
75
Rn5
75
Rn5
75
Rn5
75
DGND
8
7
D4 11
D5 12
Q3 13
Q4 14
Q5 15 DGND
VCC2 16
CLK 9
P18
6
D4 11
D3 10
5
2
4
C41
0.1µ
DGND
1
D5 12
Rn5
C42
0.1µ
DGND
Q3 13
CLK
Rn6
75
3
–2V (D)
Rn6
75
Rn6
75
Q4 14
R19
51
Q5 15 DGND
VCC2 16
Rn6
Rn6
75
IC12 : 10H101
IC11 : 10H101
+5V (A)
IC7 : 10H164
IC10 : 10H176
IC9 : 10H176
IC8 : 10H116
– 15 –
IC13 : CX20202A-1
Fig. 4. PCB Circuit Schematic
CXA1386P/K
CXA1386P/K
Characteristics Graphs
Fig 5. CXA1386P SNR vs. Input Frequency
50
CLK = 75MHz,
VEE = –5.2V
SNR [dB]
45
40
35
30
25
1
10
100
Input Frequency [MHz]
Fig. 6. CXA1386P Effective Bits vs. Input Frequency
8.0
CLK = 75MHz,
VEE = –5.2V
Effective Bits [bit]
7.0
6.0
5.0
4.0
1
10
100
Input Frequency [MHz]
Fig. 7. CXA1386P 2nd, 3rd Harmonic Distortion vs. Input Frequency
–20
2nd, 3rd Harmonic Distortion [dB]
CLK = 75MHz,
VEE = –5.2V
–30
–40
–50
2nd Hmnc
–60
3rd Hmnc
–70
1
10
Input Frequency [MHz]
– 16 –
100
CXA1386P/K
CXA1396D – CXA1386P ADAPTER (SCALE = 2/1)
55mm
CXA1386P ADAPTER
28
15
35mm
1
14
TOP VIEW
– 17 –
CXA1386P/K
Parts Layout
– 18 –
CXA1386P/K
Printed Pattern
1st layer Component plane (Top View)
4th layer Solder plane (Top view)
– 19 –
CXA1386P/K
2nd layer GND plane (Top View)
3rd layer Power supply plane (Top View)
– 20 –
CXA1386P/K
Package Outline
Unit: mm
CXA1386P
+ 0.1
0.05
0.25 –
28PIN DIP (PLASTIC) 600mil
+ 0.4
37.8 – 0.1
15.24
15
1
+ 0.3
13.0 – 0.1
28
0° to 15°
14
+ 0.4
4.6 – 0.1
3.0 MIN
0.5 MIN
2.54
0.5 ± 0.1
1.2 ± 0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
DIP-28P-03
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
∗DIP028-P-0600-C
LEAD MATERIAL
COPPER
PACKAGE WEIGHT
4.2g
JEDEC CODE
CXA1386K
44PIN LCC (CERAMIC) 1.8g
0.635 ± 0.07
1.27
+ 0.35
16.51 – 0.25
1.951 ± 0.25
1.651 ± 0.18
0.3
1.905 ± 0.25
1.27 ± 0.1
8
50
0.
C
12.5 ± 0.2
12.7 ± 0.1
6
01
1.
C
R0.2
PIN NO.1
INDEX
2.159 ± 0.5
PACKAGE STRUCTURE
SONY CODE
EIAJ CODE
LCC-44C-01
∗QFN044-C-S650-A
PACKAGE MATERIAL
CERAMIC
LEAD TREATMENT
GOLD PLATING
LEAD MATERIAL
JEDEC CODE
PACKAGE WEIGHT
– 21 –
1.8g