INFINEON ICB2FL01G

Datasheet V1.2 May 2010
ICB2FL01G
Smart Ballast Control IC for
Fluorescent Lamp Ballasts
Published by Infineon Technologies AG
http://www.infineon.com
IFAG IMM API SPI AC TM
N e v e r
s t o p
t h i n k i n g
2nd Generation FL-Controller for FL-Ballasts
ICB2FL01G
Revision History
Datasheet ICB2FL01G
Actual Release: V1.2 Date: 05.05.2010
Previous Release: 18.02.2009
Page of
Page of
Subjects changed since last release
actual Rel. prev. Rel.
3
3
Figure 1 Update
9
9
LVS1 Text Update
11
11
Figure 3 Update
21
21
Capter 2.4.2.1 Text Update and Figure 15 Update
24
24
PFC ON Time versus iZCD Signal
29
29
Update of Figure 26 and Text
38
38
Update 3.3 State Diagram
40
40
Update Protection Function Matrix HS Fil. Detection @ LVS1
53
53
BOM Update deleted Partnumbers of MOSFETs
54
54
Figure 42 Schematic of a serial Lamp Ballast Design
54
55
Figure 42 rename in Figure 43 and shift one page
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Datasheet
Page 2 from 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
2nd
Generation FL-Controller for
Fluorescent Lamp Ballasts
Product Highlights
Lowest Count of external Components
900V-Half-Bridge driver with coreless Transformer Technology
Supports Customer In-Circuit Test Mode for reduced Tester Time
Supports Multi-Lamp Designs
Integrated digital Timers up to 40 seconds
Numerous Monitoring and Protection Features for highest Reliability
All Parameter are valid over a wide Temperature Range of TJ = - 25°C until + 125°C
Features PFC
Discontinuous Mode PFC for Load Range 0 to 100%
Integrated digital Compensation of PFC Control Loop
Improved Compensation for low THD of AC Input Current also in DCM Operation
Adjustable PFC Current Limitation
Features Lamp Ballast Inverter
Adjustable Detection of Overload and Rectifier Effect (EOL)
Detection of Capacitive Load operation
Improved Ignition Control allows Operation close to the magnetic Saturation of the lamp Inductors
Restart with skipped Preheating at short interruptions of Line Voltage (for Emergency Lighting)
Parameters adjustable by Resistors only
Pb-free Lead Plating; RoHS compliant
Figure 1: Typical Application Circuit of Ballast for a single Fluorescent Lamp
Description
The FL-Controller ICB2FL01G is designed to control fluorescent lamp ballast including a
discontinuous mode Power Factor Correction (PFC), a lamp inverter control and a high voltage level
shift half-bridge driver.
The control concept covers requirements for T5 lamp ballasts for single and multi-lamp designs.
st
ICB2FL01G is based on the 1 Generation FL-Controller Technology, is easy to use and simply to
design in. Therefore a basis for a cost effective solution for fluorescent lamp ballasts of high reliability.
Figure 1 shows a typical application circuits of ballast for a single fluorescent T8 lamp with current
mode preheat.
Datasheet
Page 3 from 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
Table of Contents
1
2
Pin Configuration and Description............................................................................................... 6
1.1
Pin Configuration....................................................................................................................... 6
1.2
Pin Description .......................................................................................................................... 6
Functional Description ................................................................................................................ 11
2.1
Typical Application Circutry..................................................................................................... 11
2.2
Normal Start Up ...................................................................................................................... 12
2.2.1 Operating Levels from UVLO to Soft Start............................................................................ 13
2.2.2 Operating Levels from Soft Start to Run Mode ..................................................................... 15
2.3
Filament Detection during Start Up and Run Mode ................................................................ 17
2.3.1 Start Up with broken Low Side Filament............................................................................... 17
2.3.2 Low Side Filament Detection during Run Mode.................................................................... 18
2.3.3 Start Up with broken High Side Filament .............................................................................. 19
2.4
PFC Pre Converter.................................................................................................................. 20
2.4.1 Discontinuous Conduction and Critical Conduction Mode Operation ................................... 20
2.4.2 PFC Bus Voltage Sensing..................................................................................................... 21
2.4.2.1
Bus Over Voltage and PFC Open Loop ................................................................... 21
2.4.2.2
Bus Voltage 95% and 75% Sensing......................................................................... 21
2.4.3 PFC Structure of Mixed Signal.............................................................................................. 22
2.4.4 THD Correction via ZCD Signal ............................................................................................ 23
2.4.5 Optional THD Correction dedicated for DCM Operation....................................................... 24
2.5
Detection of End-of-Life and Rectifier Effect........................................................................... 25
2.5.1 Detection of End of Life 1 (EOL1) – Lamp Overvoltage........................................................ 25
2.5.2 Detection of End-of-Life (EOL2) – Rectifier Effect ................................................................ 26
2.6
Detection of Capacitive Load .................................................................................................. 27
2.6.1 Capacitive Load 1 (Idling Detection – Current Mode Preheating) ........................................ 28
2.6.2 Capacitive Load 2 (Over Current / Operation below Resonance) ........................................ 28
2.6.3 Adjustable self adapting Dead Time ..................................................................................... 29
2.7
Emergency Lighting ................................................................................................................ 30
2.7.1 Short Term PFC Bus Under Voltage..................................................................................... 31
2.7.2 Long Term PFC Bus Under Voltage ..................................................................................... 32
2.8
Built in Customer Test Mode Operation.................................................................................. 33
2.8.1 Pre Heating Test Mode ......................................................................................................... 33
2.8.1.1
Skip the Pre Heating Phase – Set RTPH Pin to GND.............................................. 33
2.8.1.2
IC remains in Pre Heating Phase ............................................................................. 34
2.8.2 Deactivation of the Filament Detection ................................................................................. 35
2.8.3 Built in Customer Test Mode (Clock Acceleration) ............................................................... 36
2.8.3.1
Enabling of the Clock Acceleration........................................................................... 36
2.8.3.2
Starting the Chip with accelerated Clock.................................................................. 36
3
4
State Diagram ............................................................................................................................... 37
3.1
Features during different operating modes ............................................................................. 37
3.2
Operating Flow of the Start UP Procedure into the Run Mode............................................... 38
3.3
Auto Restart and Latched Fault Condition Mode.................................................................... 39
Protection Functions Matrix........................................................................................................ 40
Datasheet
Page 4 from 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
5
Electrical Characteristics ............................................................................................................ 41
5.1
Absolute Maximum Ratings .................................................................................................... 41
5.2
Operating Range..................................................................................................................... 43
5.3
Characteristics ........................................................................................................................ 44
5.3.1 Power Supply Section ........................................................................................................... 44
5.3.2 PFC Section .......................................................................................................................... 45
5.3.2.1
PFC Current Sense (PFCCS)................................................................................... 45
5.3.2.2
PFC Zero Current Detection (PFCZCD)................................................................... 45
5.3.2.3
PFC Bus Voltage Sense (PFCVS) ........................................................................... 45
5.3.2.4
PFC PWM Generation.............................................................................................. 46
5.3.2.5
PFC Gate Drive (PFCGD) ........................................................................................ 46
5.3.2.6
Auxiliary (AUX) ......................................................................................................... 46
5.3.3 Inverter Section ..................................................................................................................... 47
5.3.3.1
Low Side Current Sense (LSCS).............................................................................. 47
5.3.3.2
Low Side Gate Drive (LSGD) ................................................................................... 48
5.3.3.3
Inverter Control Run (RFRUN) ................................................................................. 49
5.3.3.4
Inverter Control Preheating (RFPH, RTPH) ............................................................. 49
5.3.3.5
Restart after Lamp Removal (RES).......................................................................... 50
5.3.3.6
Lamp Voltage Sense (LVS1, LVS2) ......................................................................... 50
5.3.3.7
High Side Gate Drive (HSGD) .................................................................................. 51
5.3.3.8
Timer Section ........................................................................................................... 51
5.3.3.9
Built in Customer Test Mode .................................................................................... 51
6
7
Application Example .................................................................................................................... 52
6.1
Schematic Ballast 54W T5 Single Lamp................................................................................. 52
6.2
Bill of Material.......................................................................................................................... 53
6.3
Multi Lamp Ballast Topologies ................................................................................................ 54
Package Outlines ......................................................................................................................... 56
Datasheet
Page 5 from 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
1
Pin Configuration and Description
1.1
Pin Configuration
1.2
Pin Symbol
Function
1
LSCS
Low side current sense (inverter)
2
LSGD
Low side Gate drive (inverter)
3
VCC
Supply voltage
4
GND
Low side Ground
5
PFCGD
PFC Gate drive
6
PFCCS
PFC current sense
7
PFCZCD PFC zero current detector
8
PFCVS
PFC voltage sense
9
RFRUN
Set R for run frequency
10
RFPH
Set R for preheat frequency
11
RTPH
Set R for preheating time
12
RES
Restart after lamp removal
13
LVS1
Lamp voltage sense 1
14
LVS2
Lamp voltage sense 2
15
AUX
16
17
Auxiliary output
Creepage distance
HSGND
High side ground
18
HSVCC
High side supply voltage
19
HSGD
High side Gate drive (inverter)
20
Not connected
Figure 2: Package PG-DSO-19-1
Datasheet
Pin Description
LSCS (Low-side current sense, Pin 1)
This pin is directly connected to the shunt
resistor which is located between the Source
terminal of the low-side MOSFET of the inverter
and ground.
Internal clamping structures and filtering
measures allow for sensing the Source current
of the low side inverter MOSFET without
additional filter components.
There is a first threshold of 0.8V. If this
threshold is exceeded for longer than 500ns
during preheat or run mode, an inverter over
current is detected and causes a latched shut
down of the IC. The ignition control is activated
if the sensed slope at the LSCS pin reaches
typically 205 mV/µs ± 25 mV/µs and exceeds
the 0.8V threshold. This stops the decreasing of
the frequency and waits for ignition. The ignition
control is now continuously monitored by the
LSCS PIN. The Ignition control is designed to
handle a choke operation in saturation while
ignition in order to reduce the choke size.
If the sensed current signal exceeds a second
threshold of 1.6V for longer than 500ns during
start-up, soft start, ignition mode and pre-run,
the IC changes over into a latched shut down.
There are further thresholds active at this pin
during run mode that detects a capacitive mode
operation. A first threshold at 100mV needs to
sense a positive current during the second 50%
on-time of the low-side MOSFET for proper
operation (Capload 1). A second threshold of 100mV senses the current before the high-side
MOSFET is turned on. A voltage level below of
this threshold indicates a faulty operation
(Capload 2). Finally a third threshold at 2.0 V
senses even short overcurrent during turn-on of
the high-side MOSFET such as they are typical
for reverse recovery currents of a diode
(Capload 2). If one of these three comparator
thresholds indicate wrong operating conditions
for longer than 620µs (Capload 2) or 2500ms
(Capload 1) in run mode, the IC turns off the
Gates and changes into fault mode due to
detected capacitive mode operation (non-zero
voltage switching).
The threshold of -100mV is also used to adjust
the dead time between turn-off and turn-on of
the half-bridge drivers in a range of 1.25µs to
2.5µs during all operating modes.
Page 6 from 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
LSGD (Low-side Gate drive, Pin 2)
The Gate of the low-side MOSFET in a halfbridge inverter topology is controlled by this pin.
There is an active L-level during UVLO (under
voltage lockout) and a limitation of the max Hlevel at 11.0 V during normal operation. In order
to turn-on the MOSFET softly (with a reduced
diDRAIN/dt); the Gate voltage rises within 220ns
typically from L-level to H-level. The fall time of
the Gate voltage is less than 50ns in order to
turn off quickly. This measure produces
different switching speeds during turn-on and
turn-off as it is usually achieved with a diode
parallel to a resistor in the Gate drive loop. It is
recommended to use a resistor of typically 10Ω
between drive pin and Gate in order to avoid
oscillations and in order to shift the power
dissipation of discharging the Gate capacitance
into this resistor. The dead time between LSGD
signal and HSGD signal is self adapting
between 1.25µs and 2.5µs.
Vcc
(Supply voltage, Pin 3)
This pin provides the power supply of the
ground related section of the IC. There is a
turn-on threshold at 14.1V and an UVLO
threshold at 10.6V. Upper supply voltage level
is 17.5V. There is an internal zener diode
clamping VCC at 16.3V (at IVCC=2mA typically).
The maximum zener current is internally limited
to 5mA. For higher current levels an external
zener diode is required. Current consumption
during UVLO and during fault mode is less than
170µA. A ceramic capacitor close to the supply
and GND pin is required in order to act as a
low-impedance power source for Gate drive
and logic signal currents. In order to use a
skipped preheating after short interruptions of
mains supply it is necessary to feed the start-up
current (160µA) from the bus voltage. Note: for
external VCC supply see notes in flowchart
chapter 3.3.
GND (Ground, Pin 4)
This pin is connected to ground and represents
the ground level of the IC for supply voltage,
Gate drive and sense signals.
PFCGD (PFC Gate drive, Pin 5)
The Gate of the MOSFET in the PFC
preconverter designed in boost topology is
controlled by this pin. There is an active L-level
during UVLO and a limitation of the max H-level
at 11.0 V during normal operation. In order to
turn-on the MOSFET softly (with a reduced
diDRAIN/dt), the Gate drive voltage rises within
220ns
from
L-level
to
H-level.
Datasheet
The fall time of the Gate voltage is less than
50ns in order to turn off quickly.
A resistor of typically 10Ω between drive pin
and Gate in order to avoid oscillations and in
order to shift the power dissipation of
discharging the Gate capacitance into this
resistor is recommended.
The PFC section of the IC controls a boost
converter as a PFC preconverter in
discontinuous
conduction
mode
(DCM).
Typically the control starts with Gate drive
pulses with a fixed on-time of typically 4.0µs at
VACIN = 230V increasing up to 22.7µs and with
an off-time of 47µs. As soon as sufficient zero
current detector (ZCD) signals are available,
the operation mode changes from a fixed
frequent operation to an operation with variable
frequency. The PFC works in a critical
conduction mode operation (CritCM) when
rated and / or medium load conditions are
present. That means triangular shaped currents
in the boost converter choke without gaps and
variable operating frequency. During low load
(detected by an internal compensator) we get
an operation with discontinuous conduction
mode (DCM) that means triangular shaped
currents in the boost converter choke with gaps
when reaching the zero current level and
variable operating frequency in order to avoid
steps in the consumed line current.
PFCCS (PFC current sense, Pin 6)
The voltage drop across a shunt resistor
located between Source of the PFC MOSFET
and GND is sensed with this pin. If the level
exceeds a threshold of 1.0 V for longer than
200ns the PFC Gate drive is turned off as long
as the zero current detector (ZCD) enables a
new cycle. If there is no ZCD signal available
within 52µs after turn-off of the PFC Gate drive,
a new cycle is initiated from an internal start-up
timer.
PFCZCD (PFC zero current detector, Pin 7)
This pin senses the point of time when the
current through boost inductor becomes zero
during off-time of the PFC MOSFET in order to
initiate a new cycle.
The moment of interest appears when the
voltage of the separate ZCD winding changes
from positive to negative level which represents
a voltage of zero at the inductor windings and
therefore the end of current flow from lower
input voltage level to higher output voltage
level. There is a threshold with hysteresis, for
increasing level 1.5V, for decreasing level 0.5V,
which detects the change of inductor voltage.
Page 7 of 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
A resistor, connected between ZCD winding
and PIN 7, limits the sink and source current of
the sense pin when the voltage of the ZCD
winding exceeds the internal clamping levels
(6.3V and -2.9V typically @ 5mA) of the IC.
If the sensed voltage level of the ZCD winding
is not sufficient (e.g. during start-up), an internal
start-up timer will initiate a new cycle every
52µs after turn-off of the PFC Gate drive. The
source current out of this pin during the on-time
of the PFC-MOSFET indicates the voltage level
of the AC supply voltage. During low input
voltage levels the on-time of the PFC-MOSFET
is enlarged in order to minimize gaps in the line
current during zero crossing of the line voltage
and improve the THD (Total Harmonic
Distortion) of the line current. An optimization of
the THD is possible by trimming of the resistor
between this pin and the ZCD-winding.
RFRUN (Set R for run frequency, Pin 9)
A resistor from this pin to ground sets the
operating frequency of the inverter during run
mode. Typical run frequency range is 20 kHz to
120 kHz. The set resistor R_RFRUN can be
calculated based on the run frequency fRUN
according to the equation:
RFRUN =
5 ⋅ 108 ΩHz
f RUN
RFPH (Set R for preheat frequency, Pin 10)
A resistor from this pin to ground sets together
with the resistor at pin 9 the operating
frequency of the inverter during preheat mode.
Typical preheat frequency range is run
frequency (as a minimum) to 150 kHz. The set
resistor R_RFPH can be calculated based on
the preheat frequency fPH and the resistor
RRFRUN according to the equation:
PFCVS (PFC voltage sense, Pin 8)
The intermediate circuit voltage (bus voltage) at
the smoothing capacitor is sensed by a resistive
RRFRUN
RRFPH =
divider at this pin. The internal reference
⋅
f
PH R RFRUN
voltage for rated bus voltage is 2.5V. There are
−1
further thresholds at 0.3125V (12.5% of rated
5 ⋅ 108 ΩHz
bus voltage) for the detection of open control
loop and at 1.875V (75% of rated bus voltage)
RTPH (Set R for preheating time, Pin 11)
for the detection of an under voltage and at
A resistor from this pin to ground sets the
2.725V (109% of rated bus voltage) for the
preheating time of the inverter during preheat
detection of an overvoltage. The overvoltage
mode. A set resistor range from zero to 25kΩ
threshold operates with a hysteresis of 100mV
corresponds to a range of preheating time from
(4% of rated bus voltage). For the detection of a
zero to 2500ms subdivided in 127 steps.
successful start-up the bus voltage is sensed at
t Pr eHeating
95% (2.375V). It is recommended to use a
RRTPH =
ms
small capacitor between this pin and GND as a
100
spike suppression filter.
kΩ
In run mode, a PFC overvoltage stops the PFC
Gate drive within 5µs. As soon as the bus
RES (Restart, Pin 12)
voltage is less than 105% of rated level, the
A source current out of this pin via resistor and
Gate drives are enabled again. If the
filament to ground monitors the existence of the
overvoltage lasts for longer than 625ms, an
low-side filament of the fluorescent lamp for
inverter overvoltage is detected and turns off
restart after lamp removal. A capacitor from this
the inverter the gate drives also. This causes a
pin
directly
to
ground
eliminates
a
power down and a power up when VBUS<109%.
superimposed AC voltage that is generated as
A bus under- (VBUS>75%) or inverter
a voltage drop across the low-side filament.
overvoltage during run mode is handled as fault
With a second sense resistor the filament of a
U. In this situation the IC changes into power
paralleled lamp can be included into the lamp
down mode and generates a delay of 100ms by
removal sense. Note: during start up, the chip
an internal timer. Then start-up conditions are
supply voltage Vcc has to be below 14.1V
checked and if valid, a further start-up is
before VRES reaches the filament detection
initiated. If start-up conditions are not valid, a
level.
further delay of 100ms is generated.
This procedure is repeated maximum seven
times. If a start-up is successful within these
seven cycles, the situation is interpreted as a
short interruption of mains supply and the
preheating is skipped. Any further start-up
attempt is initiated including the preheating.
Datasheet
Page 8 of 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
During typical start-up with connected filaments
of the lamp a current source IRES3 (-21.3 µA) is
active as long as VCC > 10.6V and VRES < VRES1
(1.6V). An open low-side filament is detected,
when VRES > VRES1. Such a condition will
prevent the start-up of the IC. In addition the
comparator threshold is set to VRES2 (1.3V) and
the current source changes to IRES4 (-17.7 µA).
Now the system is waiting for a voltage level
lower than VRES2 at the RES pin that indicates a
connected low-side filament, which will enable
the start-up of the IC.
An open high-side filament is detected when
there is no sink current ILVSSINK (>18 µA) into
both of the LVS pins before the VCC Start-up
threshold is reached. Under these conditions
the current source at the RES pin is IRES1 (42.6µA) as long as VCC > 10.6V and VRES <
VRES1 (1.6V) and the current source is IRES2 (35.4 µA) when the threshold has changed to
VRES2 (1.3V). In this way the detection of the
high-side filament is mirrored to the levels on
the RES pin.
There is a further threshold of 3.2V active at the
RES pin during run mode. If the voltage level
rises above this threshold for longer than
620µs, the IC changes over into latched fault
mode.
In any case of fault detection with different
reaction times the IC turns-off the Gate drives
and changes into power down mode with a
current consumption of 170µA max. An internal
timer generates a delay time of 200ms, before
start-up conditions are checked again. As soon
as start-up conditions are valid, a second startup attempt is initiated. If this second attempt
fails, the IC remains in latched fault mode until
a reset is generated by UVLO or lamp removal.
The RES PIN can be deactivated via set the
PIN to GND (durable).
LVS1 (Lamp voltage sense 1, Pin 13)
Before start-up this pin senses a current fed
from the rectified line voltage via resistors
through the high-side filaments of the lamp for
the detection of an inserted lamp.
The sensed current fed into the LVS pin has to
exceed 12 µA typically at a voltage level of 6.0
V at the LVS pin. The reaction on the high side
filament detection is mirrored to the RES pin
(see pin 12). In addition the detection of
available mains supply after an interruption is
sensed by this pin. Together with pin LVS2 and
pin RES the IC can monitor the lamp removal of
totally four lamps. If the functionality of this pin
is not required, e.g. for single lamp designs, it
can be disabled by connecting this pin to
ground.
Datasheet
During run mode the lamp voltage is monitored
with this pin by sensing a current proportional to
the lamp voltage via resistors. An overload is
indicated by an excessive lamp voltage. If the
peak to peak lamp voltage effects a peak to
peak current above a threshold of 21.3µAPP for
longer than 620µs, a fault EOL1 (end-of-life) is
assumed. If the DC current at the LVS pin
exceeds a threshold of ±42µA for longer than
2500ms, a fault EOL2 (rectifier effect) is
assumed. The levels of AC sense current and
DC sense current can be set separately by
external RC network. Note, in case of a
deactivation of the LVS1/2 PIN, a reactivation
starts, when the current out the LVS1/2 PIN
exceeds VLVSEnable1 in RUN Mode.
LVS2 (Lamp voltage sense 2, Pin 14)
LVS2 has the same functionality as pin LVS1
for monitoring in parallel an additional lamp
circuitry.
AUX (Auxiliary output, Pin 15)
This pin provides a control current for a NPN
bipolar transistor during DCM operating mode
of the PFC section. There is a source current of
-450µA plus the current which is fed into pin
PFCZCD from the detector winding available
only during the enlarged off-time. That differ the
discontinuous conduction mode (DCM) from the
critical conduction mode (CritCM). With this
transistor a resistor for damping oscillations can
be switched to the ZCD winding in order to
minimize the line current harmonics during
DCM operating mode. If this function is not
used, this pin has to be not connected.
Pin 16 Not Existing
PIN 16 does not exist, in order to provide a
wider creepage distance to the high-side gate
driver. Please pay attention to relevant
standards.
HSGND (High-side ground, Pin 17)
This pin is connected to the Source terminal of
the high-side MOSFET which is also the node
of high-side and low-side MOSFET. This pin
represents the floating ground level of the highside driver and the high-side supply.
Page 9 of 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
HSVCC (High-side supply voltage, Pin 18)
This pin provides the power supply of the highside ground related section of the IC. An
external capacitor between pin 17 and pin 18
acts like a floating battery which has to be
recharged cycle by cycle via high voltage diode
from low-side supply voltage during on-time of
the low-side MOSFET. There is an UVLO
threshold with hysteresis that enables high-side
section at 10.1V and disables it at 8.4V.
HSGD (High-side Gate drive, Pin 19)
The Gate of the high-side MOSFET in a halfbridge inverter topology is controlled by this pin.
There is an active L-level during UVLO and a
Datasheet
limitation of the max H-level at 11.0 V during
normal operation. The switching characteristics
are the same as described for LSGD (pin 2). It
is recommended to use a resistor of about 10 Ω
between drive pin and Gate in order to avoid
oscillations and in order to shift the power
dissipation of discharging the Gate capacitance
into this resistor. The dead time between LSGD
signal and HSGD signal is self adapting
between 1.25µs and 2.5µs (typically).
Not connected (Pin 20)
This pin is internally not connected.
Page 10 of 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
2
2.1
Functional Description
Typical Application Circutry
Figure 3: Application Circuit of Ballast for a single Fluorescent Lamp (FL)
The schematic in Figure 3 shows a typical application for a T5 single fluorescence lamp. It is designed
for universal input voltage from 90 VAC until 270 VAC. The following chapters are explaining the
components and referring to this schematic.
Datasheet
Page 11 of 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
2.2
Normal Start Up
This chapter describes the basic operation flow (8 phases) from the UVLO (Under Voltage Lock Out)
into Run Mode without any error detection. For detailed infromation see the following chapters 2.2.1
and 2.2.2. Figure 4 shows the 8 different phases during a typical start form UVLO (phase 1 Figure 4)
to Run Mode (phase 8 Figure 4) into normal Operation (no failure detected).
In case the AC line input is switched ON, the VCC voltage rises to the UVLO threshold VCC = 10.6 V (no
IC activities during UVLO). If VCC exceeds the first threshold of VCC = 10.6 V, the IC starts the first level
of detection activity, the high and low side filament detection during the Start Up Hysteresis (phase 2
Figure 4).
Frequency /
Lamp Voltage
135 kHz
Frequency
100 kHz
50 kHz
42 kHz
1
2
3
60ms
35ms
80ms
4
11ms
5
Lamp Voltage
0 - 2500ms
6
40 - 237ms
7
625ms
0 kHz
Rated BUS
Voltage VBUS
8
Mode /
Time
100 %
Rated BUS Voltage
95 %
30 %
Mode /
Time
Chip Supply
Voltage VCC
VCC = 17.5 V
Chip Supply Voltage
VCC = 14.1 V
VCC = 10.6 V
VCC = 0 V
UVLO
Monitoring
Start Up Soft Start
Preheating
Ignition
Pre-Run
Mode /
Time
Run Mode
into normal Operation
Figure 4: Typical Start Up Procedure in Run Mode (in normal Operation)
Followed by the end of the Start Up Hysteresis (phase 2 Figure 4) VCC > 14.1 V and before phase 3 is
active, a second level of detection activity senses for 80 µs (propagation delay of the IC) whether the
rated bus voltage is below 12.5 % or above 105 %. If the previous bus voltage conditions are fulfilled
and the filaments are detected, the IC starts the operation with an internally fixed startup frequency of
typically 135 kHz (all gates are active). In case the bus voltage reaches a level of 95% of the rated bus
voltage within latest 80ms (phase 3 Figure 4), the IC enters the Soft Start. During the Soft Start (phase
4 Figure 4), the Start Up frequency shifts from 135 kHz down to the set preheating frequency (chapter
2.2.2). In the Soft Start phase, the lamp voltage rises and the chip supply voltage reaches its working
level from 10.6 V < VCC < 17.5 V. After finish the Soft Start, the IC enters the Preheating mode (phase
5 Figure 4) for preheating the filaments (adjustable time) in order to extend the life cycle of the FL
filaments. By finishing the preheating, the controller starts the Ignition (phase 6 Figure 4). During the
Ignition phase, the frequency decreases from the set preheating frequency down to the set operation
frequency (adjustable see chapter 2.2.2). If the Ignition is successful, the IC enters the Pre – Run
mode (phase 7 Figure 4).
Datasheet
Page 12 of 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
This mode is in order to prevent a malfunction of the IC due to an instable system e.g. the lamp
parameters are not in a steady state condition. After finish the 625 ms Pre Run phase, the IC switches
over to the Run mode (phase 8 Figure 4) with a complete monitoring.
2.2.1 Operating Levels from UVLO to Soft Start
This chapter describes the operating flow from phase 1 (UVLO) until phase 4 (Soft Start) in detail. The
control of the ballast is able to start the operation within less than 100 ms (IC in active Mode). This is
achieved by a small Start Up capacitor (about 1µF C12 and C13 – fed by start up resistors R11 and
R12 in Figure 3) and the low current consumption during the UVLO (IVCC = 130 µA – phase 1 Figure 5)
and Start Up Hysteresis (IVCC = 160 µA – defines the start up resistors – phase 2 Figure 5) phases.
The chip supply stage of the IC is protected against over voltage via an internal Zener clamping
network which clamps the voltage at 16.3 V and allows a current of 2.5 mA. For clamping currents
1
above 2.5 mA, an external Zener diode (D9 Figure 3) is required.
Figure 5: Progress of Level during a typical Start – UP
1
IGate depends on MOSFET
Datasheet
Page 13 of 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
In case of VCC exceeds the 10.6 V level and stays below 14.1 V (Start up Hysteresis – phase 2 Figure
5), the IC checks whether the lamps are assembled by detecting a current across the filaments.
The low side filaments are checked from a source current of typical IRES3 = - 21.3 µA out of PIN 12
RES
(Figure 5 IRES). This current produces a voltage drop of VRES < 1.6 V (filament is ok) at the low side
filament sense resistor (R 36 in Figure 3), connected to GND (via low side filament). An open low side
filament is detected (see chapter 2.3.2), when the voltage at the RES PIN exceeds the VRES > 1.6V
threshold (Figure 5 VRES).
The high side filaments are checked by a current of ILVS > 12 µA typically via resistors R41, R42 and
R43 (Figure 3) into the LVS1 PIN 13 (for a single lamp operation) and LVS2 PIN 14 for a multi lamp
operation. Note: in case of a single lamp operation, the unused LVS PIN has to be disabled via
connection to GND. An open high side filament is detected (see 2.3.3) when there is no sink current
into the LVS PIN. This causes a higher source current out of the RES PIN (typical 42.6 µA / 35.4 µA)
in order to exceed VRES > 1.6 V. In case of defect filaments, the IC keeps monitoring until there is an
adequate current from the RES or the LVS PIN present (e.g. in case of removal a defect lamp).
When VCC exceeds the 14.1 V threshold - by the end of the start up hysteresis in phase 2 Figure 5 the IC waits for 80µs and senses the bus voltage. When the rated bus voltage is in the corridor of
12.5% < VBUSrated < 105% the IC powers up the system and enters phase 3 (Figure 5 VBUSrated > 95 %
sensing) when not, the IC initiates an UVLO when the chip supply voltage is below VCC < 10.6 V. As
soon as the condition for a power up is fulfilled, the IC starts the inverter gate operation with an
internal fixed Start Up frequency of 135 kHz. The PFC gate drive starts with a delay of app. 300µs.
Now, the bus voltage will be checked for a rated level above 95 % for a duration of 80 ms (phase 3
Figure 5). When leaving phase 3, the IC enters the Soft Start phase and shifts the frequency from the
internal fixed Start Up frequency of 135 kHz down to the set Preheating frequency e.g. fRFPH = 100
kHz.
Datasheet
Page 14 of 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
2.2.2 Operating Levels from Soft Start to Run Mode
This chapter describes the operating flow from phase 5 (Preheating mode) until phase 8 (Run mode)
in detail. In order to extend the life time of the filaments, the controller enters - after the Soft Start
Phase - the Preheating mode (phase 5 Figure 6). The preheating frequency is set by resistors R22
PIN RFPH to GND in combination with R21 (Figure 3) typ. 100 kHz e.g. R22 = 8.2 kΩ in parallel to
R21 = 11.0 kΩ see Figure 3 at theRFRUN - PIN). The preheating time can be selected by the
programming resistor (R23 in Figure 3) at PIN RTPH from 0 ms up to 2500 ms (phase 5 Figure 6).
Figure 6: Typical Variation of Operating Frequency during Start Up
During Ignition (phase 6 Figure 6), the operating frequency of the inverter is shifted downward in ttyp =
40 ms (tmax = 237 ms) to the run frequency set by a resistor (R21 in Figure 3) at PIN RFRUN to GND
(typical 45 kHz with 11.0 kΩ resistor). During this frequency shifting, the voltage and current in the
resonant circuit will rise when the operation is close to the resonant frequency with increasing voltage
across the lamp. The ignition control is activated if the sensed slope at the LSCS pin reaches typically
205 mV/µs ± 25 mV/µs and exceeds the 0.8V threshold. This stops the decreasing of the frequency
and waits for ignition. The ignition control is now continuously monitored by the LSCS PIN. The
maximum duration of the Ignition procedure is limited to 237 ms. Is there no Ignition within this time
frame, the ignition control is disabled and the IC changes over into the latched fault mode.
Furthermore, in order to reduce the lamp choke, the ignition control is designed to operate with a lamp
choke in magnetic saturation during ignition. For an operation in magnetic saturation during ignition;
the voltage at the shunt at the LSCS pin 1 has to be VLSCS = 0.75V when ingition voltage is reached. If
the ignition is successful, the IC enters the Pre – Run mode (phase 7 Figure 6). The Pre Run mode is
a safety mode in order to prevent a malfunction of the IC due to an instable system e.g. the lamp
parameters are not in a steady state condition. After 625 ms Pre Run mode, the IC changes into the
Run Mode (phase 8 Figure 6). The Run mode monitors the complete system regarding bus over- and
under voltage, open loop, over current of PFC and / or Inverter, lamp over voltage (EOL1) and rectifier
effect (EOL2) see chapter 2.5) and capacitive load 1 and 2 (see chapter 2.6).
Datasheet
Page 15 of 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
Figure 7 shows the lamp voltage versus the frequency during the different phases from Preheating to
the Run Mode. The lamp voltage rises by the end of the Preheating phase with a decreasing
frequency (e.g. 100 kHz to 50 kHz) up to 700 V during Ignition. After Ignition, the lamp voltage drops
down to its working level with continuo decreasing the frequency (Figure 7) down to its working level
e.g. 45 kHz (set by a resistor at the RFRUN pin to ground). After stops the decreasing of the frequency,
the IC enters the Pre Run mode.
Lamp Voltage [V]
Lamp Voltage vs Frequency @ different Modes
1000
1000
900
900
800
800
700
700
600
600
500
500
400
400
300
300
200
200
100
100
0
10000
0
100000
Frequency [Hz]
After Ignition
Before Ignition
Figure 7: Lamp Voltage versus Frequency during the different Start up Phases
Datasheet
Page 16 of 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
2.3
Filament Detection during Start Up and Run Mode
The low and high side filament detection is sensed via the RES and the LVS pins. The low side
filament detection during start up and run mode is detected via the RES pin only. An open high side
filament during start up will be sensed via the LVS and the RES pins.
2.3.1 Start Up with broken Low Side Filament
A source current of IRES3 = - 21.3 µA out of the RES pin (12) monitors during a start up (also in Run
mode) the existence of a low side filament. In case of an open low side filament during the start up
hysteresis (10.6V < VCC < 14.1V) a capacitor (C19 in Figure 3) will be charged up via IRES3 = - 21.3 µA.
When the voltage at the RES pin (12) exceeds VRES1 = 1.6 V, the controller prevents a power up and
clamps the RES voltage internally at VRES = 5.0 V. The gate drives of the PFC and inverter stage do
not start working.
Figure 8: Startup with open Low Side
Filament
Figure 9: Restart from open Low Side
Filament
The IC comparators are set now to a threshold of VRES1 = 1.3V and to IRES4 = - 17.7µA, the controller
waits until the voltage at the RES pin drops below VRES1 = 1.3V.When a filament is present (Figure 9
section 2), the voltage drops below 1.3V and the value of the source current out of the RES pin is set
from IRES4 = - 17.7 µA up to IRES3 = - 21.3 µA. Now the controller powers up the system including Soft
Start and Preheating into the Run mode.
Datasheet
Page 17 of 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
2.3.2 Low Side Filament Detection during Run Mode
In case of an open low side filament during Run mode, the current out of the RES pin IRES3 = - 21.3 µA
charges up the capacitor C19 in Figure 3. If the voltage at the RES pin exceeds the VRES3 = 3.2V
threshold, the controller detects an open low side filament and stops the gate drives after a delay of t =
620µs of an internal timer.
Figure 10: Open Low Side Filament Run Mode
Figure 11: Restart from open LS Filament
A restart is initiated when a filament is detected e.g. in case of a lamp removal. In case of a filament is
present (Figure 11 section 2), the voltage drops below 1.3V and the value of the source current out of
the RES pin is set from IRES4 = - 17.7 µA up to IRES3 = - 21.3 µA. The controller powers up the system
including Soft Start and Preheating into the Run mode (Figure 11 section 3).
Datasheet
Page 18 of 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
2.3.3 Start Up with broken High Side Filament
An open high side filament during the start up hysteresis (10.6V < VCC < 14.1V) is detected, when the
current into the LVS pin 13 or 14 is below ILVS = 12 µA (typically). In that case, the current out of the
RES pin 12 rises up to IRES1 = - 42.6 µA. That causes a voltage at the RES pin crosses VRES1 = 1.6V.
The source current is now set to IRES2 = - 35.4 µA and another threshold of VRES2 = 1.3V is active. The
controller prevents a power up (see Figure 12), the gate drives of the PFC and inverter stage do not
start working.
VCC
VCC
Start UP with OPEN HIGH Side Filament
17.5 V
16.0 V
Chip Supply Voltage
14.1 V
14.1 V
10.6 V
10.6 V
Time
VRES UVLO Start Up
Hysteresis
2.0 V
1.6 V
1.3 V
No Power UP
42.6µA
35.4µA
IRES
Chip Supply Voltage
Time
VRES
2.0 V
1.6 V
1.3 V
Time
IRES
Restart from open HIGH Side Filament
17.5 V
16.0 V
No Power Up
Power UP (into RUN Mode)
IRES
42.6µA
35.4µA
Time
IRES
21.3µA
17.7µA
21.3µA
17.7µA
Time
ILVS
Time
ILVS
12µA
12µA
ILVS
VLamp
ILVS
Time
VLamp
Time
Time
Figure 12: Start Up with open high Side
Filament
Time
Figure 13: Restart from open high Side
Filament
When the high side filament is present, e.g. insert a lamp, the current of the active LVS pins exceeds
ILVS > 12 µA (typically), the res current drops from IRES2 = - 35.4 µA down to IRES4 = - 17.7 µA (Figure
13). Now the controller senses the low side filament. When a low side filament is also present, and the
controller drops (after a short delay due to a capacitor at the res pin) below VRES2 = 1.3V, the res
current is set to IRES3 = - 21.3 µA, the controller powers up the system.
Datasheet
Page 19 of 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
2.4
PFC Pre Converter
2.4.1 Discontinuous Conduction and Critical Conduction Mode Operation
The digital controlled PFC pre converter starts with an internally fixed ON time of typical tON = 4.0µs
and variable frequency. The ON – time is enlarged every 280 µs (typical) up to a maximum ON – time
of 22.7 µs. The control switches quite immediately from the discontinuous conduction mode (DCM)
over into critical conduction mode (CritCM) as soon as a sufficient ZCD signal is available. The
frequency range in CritCM is 22 kHz until 500 kHz, depending on the power (Figure 14) with a
variation of the ON time from 22.7 µs > tON > 0.5µs.
Discontinuous Conduction Mode (DCM) <> Critical Condution Mode (CritCM)
100,00
100,00
10,00
PFC - ON Time [µs]
PFC Frequency [kHz] 50% Duty Cycle
1000,00
10,00
1,00
1,00
0,10
0,01
0,01
0,10
0,10
1,00
10,00
100,00
Normalized Output Power [% ]
Frequency DCM
Frequency CritCM
Ton DCM
Ton CritCM
Figure 14: Operating Frequency and ON Time versus Power in DCM and CritCM Operation
2
For lower loads (POUTNorm < 8 % from the normalized load ) the control operates in discontinuous
conduction mode (DCM) with an ON – time from 4.0µs and increasing OFF – time. The frequency
during DCM is variable in a range from 144 kHz down to typically 22 kHz @ 0.1 % Load (Figure 14).
With this control method, the PFC converter enables a stable operation from 100 % load down to 0.1
%. Figure 14 shows the ON time range in DCM and CritCM (Critical Conduction Mode) operation. In
the overlapping area of CritCM and DCM is a hysteresis of the ON time which causes a negligible
frequency change.
2
Normalized Power @ Low Line Input Voltage and maximum Load
Datasheet
Page 20 of 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
2.4.2 PFC Bus Voltage Sensing
Over voltage, open loop, bus 95 % and under voltage states (Figure 15) of the PFC bus voltage are
sensed at the PFCVS pin via the network R14, R15, R20 and C11 Figure 3 (C11 acts as a spike
suppression filter).
2.4.2.1
Bus Over Voltage and PFC Open Loop
The bus voltage loop control is completely integrated (Figure 16) and provided by an 8 Bit sigma –
delta A/D – converter with a typical sampling rate of 280 µs and a resolution of 4 mV/Bit. After leaving
phase 2 (monitoring), the IC starts the power up (VCC > 14.1V). After power up, the IC senses for
80µs – 130µs the bus voltage below 12.5% (open loop) or above 105% (bus over voltage). In case of
a bus over voltage (VBUSrated > 109 %) or open loop (VBUSrated < 12.5 %) in phases 3 until 8 the IC shuts
off the gate drives of the PFC within 5µs respective in 1µs. In this case, the PFC restarts automatically
when the bus voltage is within the corridor (12.5% < VBUSrated < 105 %) again. Is the bus voltage after
the 80µs – 130µs valid, the bus voltage sensing is set to 12.5% < VBUSrated < 109 %. In case leaving
these thresholds for longer than 1µ (open loop) or 5µs (overvoltage) the PFC gate drive stops working
until the voltage drops below 105% or exceeds the 12.5% level. If the bus over voltage (> 109%) lasts
for longer than 625ms in run mode, the inverter gates also shut off and a power down with complete
restart is attempt (Figure 15).
Figure 15: PFC Bus Voltage Operating Level and Error Detection
2.4.2.2
Bus Voltage 95% and 75% Sensing
When the rated bus voltage is in the corridor of 12.5% < VBUSrated < 109 %, the IC will check whether
the bus voltage exceeds the 95 % threshold (Figure 15 phase 3) within 80 ms before entering the soft
start phase 4. Another threshold is activated when the IC enters the run mode (phase 8). When the
rated bus voltage drops below 75% for longer than 84 µs, a power down with a complete restart is
attempted when a counter exceeds 800 ms. In case of a short term bus under voltage (the bus voltage
reaches its working level in run mode before exceeding typically 800 ms (min. 500ms) the IC skips
phases 1 until 5 and starts with ignition (condition for emergency lighting see 2.7.1). The internal
reference level of the bus voltage sense VPFCVS is 2.5 V (100 % of the rated bus voltage) with a high
accuracy. A surge protection is activated in case of a rated bus voltage of VBUS > 109% and a low side
current sense voltage of VLSCS > 0.8V for longer as 500ns in PRE RUN and RUN Mode.
Datasheet
Page 21 of 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
2.4.3 PFC Structure of Mixed Signal
A digital NOTCH filter eliminates the input voltage ripple - independent from the mains frequency. A
subsequent error amplifier with PI characteristic cares for a stable operation of the PFC pre converter
(Figure 16).
Over Voltage
109%
Open Loop
12.5%
PFCGD
PFCVS
Σ∆-ADC
Notch Filter
PI Loop Control
PWM
Under Voltage
75%
Over Current
1V ± 5.0%
Bus Voltage
95%
ZCD Start Up
1.5V / 0.5V
Gate Drive
PFCCS
PFCZCD
THD
Correction
Int. Reference
VPFCVS = 2.5 V
Clock 870 kHz
Figure 16: Structure of the mixed digital and analog control of the PFC pre converter
The zero current detection (ZCD) is sensed by the PFCZCD pin via R13 (Figure 3). The information of
finished current flow during demagnetization is required in CritCM and in DCM as well. The input is
equipped with a special filtering including a blanking of typically 500 ns and a large hysteresis of
typically 0.5 V and 1.5 V VPFCZCD (Figure 16).
Datasheet
Page 22 of 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
2.4.4 THD Correction via ZCD Signal
An additional feature is the THD correction (Figure 16). In order to optimize the improved THD
(especially in the zones A shown in Figure 17 ZCD @ AC Input Voltage), there is a possibility to
extend pulse width of the gate signal (blue part of the PFC gate signal in Figure 17) via variable PFC
ZCD resistor (see Resistor R13 in Figure 3) in addition to the gate signal controlled by the VPFCVS
signal (gray part of the PFC gate signal in Figure 17).
ZCD @ AC Input Voltage
ZCD @ DC Input Voltage
Rectified
AC Input Voltage
A
DC Input Voltage
B
A
0
Voltage at
0
ZCD-Winding
PFC Gate
Drive Voltage 0
PFC gate signal (gray) controlled by the VPFCVS
PFC gate signal (blue) controlled by the ZCD
Figure 17: THD Optimization using adjustable Pulse Width Extension
In case of DC input voltage (see DC Input Voltage in Figure 17), the pulse width gate signal is fixed as
a combination of the gate signal controlled by the VPFCVS pin (gray) and the additional pulse width
signal controlled by the ZCD pin (blue) shown in Figure 17 ZCD @ DC Input Voltage.
The PFC current limitation at pin PFCCS interrupts the ON – time of the PFC MOSFET if the voltage
drop at the shunt resistors R18 (Figure 3) exceeds the VPFCCS = 1.0 V (Figure 16). This interrupt will
restart after the next sufficient signal from ZCD is available (Auto Restart). The first value of the
resistor can be calculated by the ratio of the PFC mains choke and ZCD winding the bus voltage and a
current of typically 1.5 mA (see equation below). An adjustment of the ZCD resistor causes an
optimized THD.
RZCD
N ZCD
* VBUS
N PFC
=
1.5mA
Equation 1: RZCD a good pratical Value
Datasheet
Page 23 of 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
The relationship between the extended PFC pulse width and the zero crossing detection current is
shown in Figure 19.
2.4.5 Optional THD Correction dedicated for DCM Operation
For applications with a wide input voltage range and / or for applications using a wide variation of the
power e.g. dimming, the application might work in the DCM (Discontinuous Conduction Mode). In
order to minimize the high order harmonics during DCM, the detection of the DCM should be as close
as possible at the point of inflection of the PFC drain source voltage shown in Figure 18. This can be
realized with an optional damping network (R4, D10 and Q4 from the AUX pin to the ZCD resistor
R13.
PFC Drain Source
Voltage
DCM
Detection
CritCM
Detection
0
t
Voltage at PFC 0
ZCD winding
with damping
t
Output current
at Pin AUX in DCM
PFC Gate Source
Voltage
0
t
0
t
Figure 18: Signal Shapes with optional damping
of oscillations during DCM operation of PFC
Figure 19: PFC ON Time Extension versus Zero
Crossing Current Signal
Figure 20: Optional Circuit for attenuating oscillations during DCM operation of PFC.
Datasheet
Page 24 of 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
2.5
Detection of End-of-Life and Rectifier Effect
Two effects are present by End of Life (EOL): lamp over voltage (EOL1) and a rectifier effect (EOL2).
After Ignition (see 1 in Figure 21), the lamp voltage breaks down to its run voltage level with
decreasing frequency. By reaching the run frequency, the IC enters the Pre Run Mode for 625 ms.
During this period, the EOL detection is still disabled. In the subsequent RUN Mode (2 in Figure 21)
the detection of EOL1 (lamp over voltage see 3 Figure 21) and EOL2 (rectifier effect see 4 Figure 21)
is complete enabled.
Figure 21: End of Life and Rectifier Effect
2.5.1 Detection of End of Life 1 (EOL1) – Lamp Overvoltage
The event of EOL1 is detected by measuring the positive and negative peak level of the lamp voltage
via an AC current fed into the LVS pin (Figure 22). This AC current is fed into the LVS pins (LVS1 for
single lamp and LVS2 for multi lamp applications) via Network R41, R42, R43 and the low pass filter
C40 and R45 see Figure 3. If the sensed AC current exceeds 210 µAPP for longer than 620 µs, the
status of end-of-life (EOL1) is detected (lamp overvoltage / overload see Figure 22 LVSAC Current).
The EOL1 fault results in a latched power down mode (after trying a single restart) the controller is
continuously monitoring the status until EOL1 status changes e.g. a new lamp is inserted.
Figure 22: End of Life (EOL1) Detection, Lamp Voltage versus AC LVS Current
Datasheet
Page 25 of 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
2.5.2 Detection of End-of-Life (EOL2) – Rectifier Effect
The rectifier effect (EOL2) is detected by measuring the positive and negative DC level of the lamp
voltage via a current fed into the LVS pin (Figure 23). This current is fed into the LVS pins (LVS1 for
single lamp and LVS2 for multi lamp applications) via Network R41, R42 and R43 (see Figure 3). If the
sensed DC current exceeds ± 42 µA (Figure 23 LVSDC Current) for longer than 2500 ms, the status of
end-of-life (EOL2) is detected. The EOL2 fault results in a latched power down mode (after trying a
single restart) the controller is continuously monitoring. Only the insert of a new lamp resets the status
of the IC.
Figure 23: End of Life (EOL2) Detection, Lamp Voltage versus DC LVS Current
Datasheet
Page 26 of 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
2.6
Detection of Capacitive Load
In order to prevent a malfunction in the area of Capacitive Load (see Figure 24) during Run Mode due
to certain deviations from the normal load (e.g. harmed lamp, sudden break of the lamp tube …), the
IC has three integrated thresholds – sensed only via the LSCS (pin 1). The controller distinguish
between two different states of capacitive load, the detection of working without load (idling detection,
CapLoad 1) and working with short over current (CapLoad 2). This state (CapLoad 2) is affecting an
operation below the resonance in the capacitive load area (Figure 24). In both cases, the IC results in
a latched power down mode after a single restart. After latching the power down mode, the controller
is continuously monitoring the status of the fault and restarts after the fault disappears e.g. in case of
inserting a new lamp.
Lamp Voltage vs Frequency @ different Modes
1000
1000
900
900
Area of Inductive
Load Behavior
Lamp Voltage [V]
800
700
600
Area of Capacitive
Load Behavior
800
700
IGNITION
600
500
500
400
400
300
300
200
100
0
10000
200
Load
PRE Run
and
RUN Mode
After
IGNITION
100
Pre Heating
0
100000
Frequency [Hz]
After Ignition
Before Ignition
Figure 24: Capacitive and Inductive Operation
Datasheet
Page 27 of 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
2.6.1 Capacitive Load 1 (Idling Detection – Current Mode Preheating)
A capacitive load 1 operation (idling) is detected when the voltage at the LSCS pin is below + 100 mV
during the second 50% ON – time of the low side MOSFET (see Capacitive Load 1 (Idling) in Figure
25). If this status is present for longer than 2500 ms, the controller results a latched power down mode
after trying a single restart. The controller is keep monitoring continuously the status until an adequate
load is present (e.g. lamp removal), than the IC changes into a normal operation.
Figure 25: Capacitive Mode 1 Operation without load during Run Mode
2.6.2 Capacitive Load 2 (Over Current / Operation below Resonance)
A capacitive load 2 operation is detected if the voltage at the LSCS pin drops below a second
threshold of VLSCS = – 100 mV directly before the high side MOSFET is turned on or exceeds a third
threshold of VLSCS = 2.0 V during ON switching of the high side MOSFET. If this over current is present
for longer than 620 µs, the IC results a latched power down mode after trying a single restart. The
controller keeps monitoring continuously the status until an adequate load is present e.g. a new lamp
is inserted, then the IC changes into a normal operation.
Normal Operation
Capacitive Load 2 (Over Current)
VDSLS
VDSLS
IDSLS
IDSLS
VGateHS
VGateHS
VGateLS
VGateLS
VLSCS
VLSCS
+ 2.0 V
+ 2.0 V
- 100 mV
- 100 mV
tCAPLOAD 1
tCAPLOAD 2
tCAPLOAD 2
Figure 26: Capacitive Mode 2 – Operation with Over Current
Datasheet
Page 28 of 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
2.6.3 Adjustable self adapting Dead Time
The dead time between the turn OFF and turn ON of the half – bridge drivers is adjustable (C16 see
Figure 3) and detected via a second threshold (– 100 mV) of the LSCS voltage. The range of the dead
time adjustment is 1.25 µs up to 2.5 µs during all operating modes. Start of the dead time
measurement is the OFF switching of the high side MOSFET. The finish of the dead time
measurement is, when VLSCS drops for longer than typical 280ns (internal fixed propagation delay)
below -100mV. This time will be stored (stored dead time) and the low side gate driver switches ON.
The high side gate driver turns ON again after OFF switching of the low side switch and the stored
dead time.
Normal Operation in RUN Mode
VDSLS
VLSCS
VLSCS = -100mV
END of Dead Time
Measurement
Gate LS
Gate HS
Dead Time
START of Dead Time
Measurement
Dead Time
280 ns
Propagation Delay
Stored Dead Time
Stored Dead Time
Figure 27: Dead Time of ON and OFF of the Half Bridge Drivers
Datasheet
Page 29 of 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
2.7
Emergency Lighting
Line interruptions (bus voltage drops) are detected by the PFCVS. If the rated PFC bus voltage drops
below VBUSRated < 75 % during run mode, the controller detects a PFC bus under voltage. In order to
meets the emergency lighting standards, the controller distinguishes two different states of a PFC bus
under voltage, a short and a long term PFC bus under voltage. A timer increases the time as long as a
bus under voltage is present. A short term bus under voltage is detected if the timer value stays below
t < 800ms typically (500ms min.) after the bus voltage reaches the nominal level again. These causes
a restart without preheating (emergency standard of VDE0108) see Figure 28. When the timer
exceeds t > 800 ms, the controller forces a complete restart of the system due to a long term bus
under voltage (Figure 29).
Datasheet
Page 30 of 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
2.7.1 Short Term PFC Bus Under Voltage
A short term PFC bus under voltage (Figure 28) is detected if the duration of the under voltage does
not exceed 800 ms (timer stays below t < 800ms see Figure 28). In that case, the PFC and inverter
drivers are immediately switched off and the controller is continuously monitoring the status of the bus
voltage in a latched power down mode (ICC < 170 µA). If the signal at the LVS PIN exceeds 18µA and
the rated bus voltage is above 12.5% within the timer is below t < 800 ms, the controller restarts from
power up without preheating. The timer resets to 0 when entering the Run Mode.
Bus Voltage Drop for t < 800 ms
Restart without Preheating
VBUSRated
Interrupt for
t < 800 ms
100%
75%
RUN Mode
Power Down
Mode
Pre Run
Run Mode
VCC
16V
ICC
< 6 mA +
IQGate
< 6 mA + IQGate
< 160 µA
Timer
t = 800ms
IPreheating
VLamp
Figure 28: BUS Voltage Drop below 75% (rated Bus Voltage) for t < 800 ms during RUN Mode
Datasheet
Page 31 of 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
2.7.2 Long Term PFC Bus Under Voltage
If the duration of the bus under voltage exceeds t > 800ms see Figure 29, the controller forces an
under voltage lock out (UVLO). The chip supply voltage drops below VCC = 10.6 V and the chip supply
current is below ICC < 130µA. When the Vcc voltage exceeds the 10.6V threshold again, the IC current
consumption is below ICC < 160µA. In that case, the controller resets the timer and restarts with the full
start up procedure including Monitoring, Power Up, Start Up, Soft Start, Preheating, Ignition, Pre Run
and Run Mode as shown in Figure 29.
Bus Voltage Drop for t > 800 ms
Restart with full Start Procedure
VBUSRated
Interrupt for t > 800 ms
95%
75%
RUN Mode
Power Down Mode
< 6 mA +
IGate
< 160 µA
Run Mode
VCC
16V
UVLO @ 10.6V
ICC
< 6 mA + IGate
<160 µA
Timer
t = 800ms
IPreheating
VLamp
Figure 29: BUS Voltage Drop below 75% (rated Bus Voltage) for t > 800 ms during RUN Mode
Datasheet
Page 32 of 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
2.8
Built in Customer Test Mode Operation
nd
In order to decrease the final ballast testing time for customers, the 2 generation of ballast IC
supports an integrated built in Customer Test Mode and several functions to disable some features
and states of the IC.
2.8.1 Pre Heating Test Mode
This feature forces the IC to stay in the pre heating mode (see chapter 2.8.1.2) or to starts the ignition
immediately without any preheating (see chapter 2.8.1.1 skip pre heating). A resistor at this pin
defines the duration of the pre heating phase. Normally, the pre heating phase is in a range of 0ms up
to 2500ms set via a resistor RRTPH = 0Ω up to 25kΩ from the RTPH pin to GND. The pre heating phase
is skipped when the RTHP pin is set to GND. If the signal at this pin is VRTPH > 5.0 V, the IC remains in
the pre heating mode.
2.8.1.1
Skip the Pre Heating Phase – Set RTPH Pin to GND
The Pre Heating phase can be skipped in set the RTPH pin 11 to GND. Figure 30 shows a standard
start up with a set pre heating time via resistor at the RTPH pin 11 to GND (e.g. 8.2 kΩ this is equal to
a pre heating phase of app. 820ms). The pre heating phase can be skipped in setting the RTPH pin 11
directly to GND. In that case, the ignition is directly after the soft start phase.
Figure 30: Start UP WITH Pre Heating
Datasheet
Figure 31: Start UP WITHOUT Pre Heating
Page 33 of 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
2.8.1.2
IC remains in Pre Heating Phase
This feature gives the customer the flexibility to align the pre heating frequency to the filament power
in the pre heating phase. Figure 32 shows a standard start up with the set preheating time of e.g.
820ms with an 8.2 kΩ resistor at the RTPH pin 11. To force the IC remains in pre heating, the voltage
level at the RTPH pin 11 has to set to 5.0 V. The duration of this 5.0 V signal defines the time of the
pre heating see IPreHeat in figure below.
VCC
17.5 V
16.0 V
Chip Supply Voltage
14.1 V
10.6 V
Time
Start Up
VRTPH UVLO Hysteresis
5.0 V
2.5 V
Duration is set by
Resistor only
Time
IPreHeat
Preheating
Time
t = 820 ms when using
RRTPH = 8.2kOhm
VLamp
IGNITION
Time
Figure 32: Start UP with Pre Heating
Datasheet
Figure 33: Start UP REMAINS in Pre Heating
Page 34 of 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
2.8.2 Deactivation of the Filament Detection
In order to deactivate the filament detection of the low or high side filament, set the RES pin 12 or the
LVS1 / LVS2 pin 13 / 14 to GND. In that case, the IC starts up into normal operation without checking
the filaments e.g. when using an equivalent lamp resistive load instead of a load.
VCC
17.5 V
16.0 V
Chip Supply Voltage
14.1 V
10.6 V
VRES
UVLO
5.0 V
1.6 V
1.3 V
Time
Start Up
Hysteresis
LVS1 or LVS2 PIN set to GND
VLSGD
10V
VLamp
Figure 34: Deactivation via RES PIN
Figure 35: Deactivation via LVS1 / LVS2 PIN
Figure 34 shows the deactivation of the low and high side filament via set the RES pin 12 to GND.
Figure 35 shows the deactivation of the high side filament detection via set the LVS1 or LVS2 pin to
GND.
Note
In case using just one path of a ballast design (single or dual lamp in series) one of the not used LVS
pins has to be set to GND.
Datasheet
Page 35 of 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
Functional Description
2.8.3 Built in Customer Test Mode (Clock Acceleration)
The built in customer test mode, supported by this IC, saves testing time for customers in terms of
ballast end test. In that mode, the IC accelerates the internal clock in order to reduce the time of the 4
different procedures by the following factors (see Table 1).
Phase
Preheating
Time Out Ignition
Pre Run Mode
EOL2
Duration for Test [ms]
625
118.5
41.7
41.7
Acceleration Factor
4
2
15
60
Nominal Duration [ms]
2500 (max)
237
625
2500
Table 1: Specified Acceleration Factors
2.8.3.1
Enabling of the Clock Acceleration
The clock acceleration (Built in Customer Test Mode) is activated when the chip supply voltage
exceeds VCC > 14.1V and the voltages at the Run Frequency and Preheating Frequency pin are set to
VRFRUN = VRFPH = 5.0 V (± 5 %) see Figure 35 “Enabling of Clock Acceleration”. A RES pin voltage of
VRES > 3.5 V up to 5.0 V (± 5 %) prevents a power up of the IC, the IC remains in a mode before
powering up. This status is hold as long as the voltage at the RES pin is at VRES > 3.5 V up to 5.0 V (±
5 %) – no power up. Note: after the activation of the clock acceleration mode, the voltage level of 5.0V
at the Run Frequency and Preheating Frequency pin (VRFRUN = VRFPH) can be released.
2.8.3.2
Starting the Chip with accelerated Clock
In order to start the IC with an accelerated clock, set the voltage at the RES pin to GND (VRES = 0 V).
Figure 36 “Starting the Chip with an accelerated Clock”. The IC powers up the system and starts
working with an accelerated clock. Now the duration of the different modes are accelerated by Factors
shown in Table 1
Figure 36: Clock Acceleration (Built in Customer Test Mode)
Datasheet
Page 36 of 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
State Diagram
3
3.1
State Diagram
Features during different operating modes
Figure 37: Monitoring Features during different operating Modes
Datasheet
Page 37 of 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
State Diagram
3.2
Operating Flow of the Start UP Procedure into the Run Mode
Vcc < 10.6V
UVLO
Vcc < 10.6V
Icc < 130µA
Vcc > 10.6V
Monitoring
Vcc > 10.6V
Icc < 160µA
Vcc > Vccon(14.1V)
& Filament detected
VBUS < 12,5%
or VBUS > 105%
Power-up
See
Timing and Handling of
Fault Conditions
Gate Drives off
14.1V < Vcc
Icc approx 6.0mA
after 130µs
& VBUS > 12,5%
& VBUS< 105%
Start-up
Inverter Gates on
PFC Gate on
17.5V> Vcc >10.6V
f_Inv = f_START
See
Protection
Functions
VBUS > 95%
within 80ms
Softstart
Fault
17.5V> Vcc >10.6V
Icc < 170µA
Gate Drives off
17.5V> Vcc >10.6V
f_START=> f_PH
after 10ms
after 10ms
& Flag Skip Preheat
& Flag Skip Preheat = Set
= Reset
// Reset Flag
Skip Preheat
Preheat
& Counter Skip PH // 17.5V> Vcc >10.6V
f = f_PH
after t_PH= 0...2500ms
Time set by R_TPH
Ignition*
Timeout 237ms
17.5V> Vcc >10.6V
f_PH => f_RUN
f_Inv= f_RUN within
t_IGN= 40...237ms
Pre-Run
17,5V> Vcc >10.6V
f = f_RUN
Reduced Monitoring
after
t_PRERUN=
625ms
Run
* NOTE:
Ignition will reset the
Flag Skip Preheating
17.5V> Vcc >10.6V
f = f_RUN
Complete Monitoring
Figure 38: Operating Flow during Start-up Procedure
Datasheet
Page 38 of 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
State Diagram
3.3
Auto Restart and Latched Fault Condition Mode
Fault A
Fault U
Fault F
BUS Voltage
Fault, single Restart
Auto Restart
BUS Undervoltage
(VBUS < 75%
during Run Mode
for t > 84µs);
BUS Overvoltage
(VBUS > 109%
for t > 625ms);
Open Filament LS;
Inverter Overcurrent;
Capacitive Load 1;
Capacitive Load 2;
Timeout Ignition;
EOL 1 (Overload);
EOL 2 (Rectifier Effect);
Surge;
Time OUT Start Up
(VBUS < 95% for t >
80 ms)
Increment
Fault Counter
NOTE
to Set Flag Skip Preheat:
When using external Vcc
Supply, no reset of Set Flag
Skip Preheat. 1st Restart
without Preheating while
Vcc > UVLO. When LVS
deactivated or not from Line.
INVERTER and PFC Gate OFF
Only at Inverter Over current PFC Gate
OFF appr. 150µs Delayed
Power down Icc < 160µA
Set Flag
Skip Preheat
Gate drives off
Power down
Icc < 160µA
Wait 200ms
Delay Timer A
Fault Counter
<2
Wait 100ms
Delay Timer A
Increment
Counter Skip PH
Y
N
Reset
Fault Counter
Y
N
Wait for
Lamp Removal
Start
Start-up
Gate drives off
IC remains
in active mode
Lamp removed
for min 100ms
Inverter Gates on
PFC Gate on
17.5V> Vcc >10.6V
f_Inv = f_START
Wait for
Lamp inserted
Lamp
inserted?
N
N
t > 80ms?
from Power-Up
Y
Fault A
Timeout 80ms
Start-up
N
Counter
Skip Preheat
>7?
Lamp inserted
for min 100ms
NOTE
For external Vcc
Supply, set Vcc
below UVLO.
Y
Y
Wait for
UVLO
VBUS > 95%?
Y
End
Start-up
Vcc > 14.1V?
N
Y
Power-up
Gate Drives off
Reset
Flag Skip Preheat
& Counter Skip PH
Vcc < 10.6V?
Y
Note:
Fault Counter reset
after 40s in Run Mode
Reset of Flag Skip
Preheat after Ignition
UVLO
Reset all Latches
Figure 39: Operating Process during Start-up Mode and Handling of Fault Conditions
Datasheet
N
Lamp Inserted?
Or
VBUS < 75%
Page 39 of 56
ICB2FL01G
V1.2
N
2nd Generation FL-Controller for FL-Ballasts
Bus voltage < 12.5% of rated
level 10µs after power up
Bus voltage < 12.5%
of rated level
Bus voltage < 12.5%
of rated level
Bus voltage < 75%
of rated level
add. shut down delay 120µs
Bus voltage < 95% of rated
level during start-up
Bus voltage > 105% of rated
level 10µs after power up
Bus voltage > 109% of rated
level in active operation
Bus voltage > 109% of rated
level in active operation
+/- peak level of lamp voltage
at Pin LVS above threshold
DC level of lamp voltage
above +/- threshold
Capacitive Load 1
S
1µs
S
5µs
S
100µs
S
100µs
S
100µs
F
620µs
S
1µs
N
1µs
U
625ms
U
84µs
Consequence
Run Mode
Below startup threshold
Below UVLO
threshold
open
filament HS
open
filament HS
open
filament LS
open
filament LS
Open Loop
detection
Open Loop
detection
Shut down
option
Undervoltage
Start-up until
VBUS > 95%
Softstart
10ms
Preheat Mode
0 – 2500ms
Ignition Mode
40 – 237ms
Pre-Run Mode
625ms
Supply voltage Vcc < 14.1V
before power up
Supply voltage Vcc < 10.6V
after power up
Current into LVS1 pin < 18µA
before power up
Current into LVS2 pin < 18µA
before power up
Voltage at RES pin > 1.6V
before power up
Voltage at RES pin > 3.2V
Power-up 130µs
Operating Mode Detection is active
Minimum
Duration
of effect
Characteristics of fault
Type of fault
Description of Fault
Monitoring
Protection Functions Matrix
Name of Fault
4
Prevents power up
X
X
X
X
X
X
X
X
X
X
Power down,
Reset failure latch
Prevents power up
Prevents power up
X
Prevents power up
X
X
Power down,latched
Fault Mode, 1 Restart
Keep Gate drives off, restart after Vcc hysteresis
X
X
X
X
X
X
X
X
X
Stops PFC FET until
VBUS > 12.5%
Power down, restart
when VBUS> 12.5%
Power down, 100ms
delay, restart, skip preheating max 7 times
Power down, 200ms
delay, restart
Timeout max A
80ms
X
start-up time
Keep Gate drives off, reOverS
5µs
X
start after Vcc hysteresis
voltage
Stops PFC FET until
PFC
N
5µs
X
X
X
X
X
X
VBUS< 105%
Overvoltage
Power down, restart
Inverter
U
625ms
X
when VBUS<105%
Overvoltage
Power down,latched
EOL 1
F
620µs
X
Fault Mode, 1 Restart
Overvoltage
Power down,latched
EOL 2
F
2500ms
X
Fault Mode, 1 Restart
Rect. Effect
Power down,latched
Cap Load 1
F
2500ms
X
Fault Mode, 1 Restart
Idling
Power down,latched
Capacitive Load 2,
Cap.Load 2
F
620µs
X
Fault Mode, 1 Restart
operation below resonance
Overload
Run frequency cannot be
Timeout
F
237ms
Power down,latched
X
achieved
Ignition
Fault Mode, 1 Restart
Stops on-time of PFC
Voltage at PFCCS pin > 1.0V PFC
N
200ns
X
X
X
X
X
X
FET immediately
Overcurrent
Voltage at LSCS pin > 0.8V
Inverter
N
200ns
Activates
X
current lim
Ignition control
Power down,latched
Voltage at LSCS pin > 0.8V
Inverter
F
500ns
X
X
Fault Mode, 1 Restart
overcurrent
Power down,latched
Voltage at LSCS pin > 1.6V
Inverter
F
500ns
X
X
X
X
Fault Mode, 1 Restart
overcurrent
Power down, restart
Voltage at LSCS pin > 0.8V
Inverter
A
500ns
X
X
when VBUS<109%
& VBUS > 109% (Surge)
overcurrent
After jump into latched fault mode F wait
200ms A single restart attempt after delay of internal timer
Reset of failure latch in run mode after
40s
Reset of failure latch by UVLO or 40s in run mode
S = Start-up condition,
N = No Fault,
A = Auto-Restart ,
U = Undervoltage
F = Fault with a single Restart, a second F leads to a latched fault / Note: all values @ typical 50 Hz mains frequency
Datasheet
Page 40 of 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
Electrical Characteristics
5
Electrical Characteristics
Note: All voltages without the high side signals are measured with respect to ground (pin 4). The high side
voltages are measured with respect to pin17. The voltage levels are valid if other ratings are not
violated.
Absolute Maximum Ratings
5.1
Absolute Maximum Ratings
Note: Absolute maximum ratings are defined as ratings, which when being exceeded may lead to
destruction of the integrated circuit. For the same reason make sure, that any capacitor that will be
connected to pin 3 (VCC) and pin 18 (HSVCC) is discharged before assembling the application
circuit.
Parameter
Symbol
Limit Values
min.
max.
Unit
Remarks
LSCS Voltage
VLSCS
-5
6
V
LSCS Current
ILSCS
-3
3
mA
LSGD Voltage
VLSGD
- 0.3
Vcc+0.3
V
LSGD Peak Source Current
ILSGDsomax
- 75
5
mA
< 500ns
LSGD Peak Sink Current
ILSGDsimax
- 50
400
mA
< 100ns
VVCC
- 0.3
18.0
V
VCC Zener Clamp Current
IVCCzener
-5
5
mA
PFCGD Voltage
VPFCGD
- 0.3
Vcc+0.3
V
PFCGD Peak Source Current
IPFCGDsomax
- 150
5
mA
< 500ns
PFCGD Peak Sink Current
IPFCGDsimax
- 100
700
mA
< 100ns
PFCCS Voltage
VPFCCS
-5
6
V
PFCCS Current
IPFCCS
-3
3
mA
PFCZCD Voltage
VPFCZCD
-3
6
V
PFCZCD Current
IPFCZCD
-5
5
mA
PFCVS Voltage
VPFCVS
- 0.3
5.3
V
RFRUN Voltage
VRFRUN
- 0.3
5.3
V
RFPH Voltage
VRFPH
- 0.3
5.3
V
RTPH Voltage
VRTPH
- 0.3
5.3
V
RES Voltage
VRES
- 0.3
5.3
V
LVS1 Voltage
VLVS1
-6
7
V
LVS1 Current1
ILVS1_1
-1
1
mA
IC in Power Down Mode
LVS1 Current2
ILVS1_2
-3
3
mA
IC in active Mode
LVS2 Voltage
VLVS2
-6
7
V
LVS2 Current1
ILVS2_1
-1
1
mA
IC in Power Down Mode
LVS2 Current2
ILVS2_2
-3
3
mA
IC in active Mode
VCC Voltage
Datasheet
Page 41 of 56
Internally clamped to 11V
IC in Power Down Mode
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
Unit
Remarks
min.
max.
VAUX
- 0.3
5.3
V
VHSGND
- 900
900
V
dVHSGND /dt
- 40
40
V/ns
HSVCC Voltage
VHSVCC
- 0.3
18.0
V
Referring to HSGND
HSGD Voltage
VHSGD
- 0.3
VHSVCC+0.3
V
Internally clamped to 11V
HSGD Peak Source Current
IHSGDsomax
- 75
0
mA
< 500ns
HSGD Peak Sink Current
IHSGDsimax
0
400
mA
< 100ns
Junction Temperature
TJ
- 25
150
°C
Storage Temperature
TS
- 55
150
°C
Maximum Power Dissipation
PTOT
—
2
W
Thermal Resistance (2 Chips)
RthJA
—
60
K/W
PG_DSO-19-1
Thermal Resistance (HS Chip)
RthJAHS
—
120
K/W
PG_DSO-19-1
Thermal Resistance (LS Chip)
RthJALS
—
120
K/W
PG_DSO-19-1
—
260
°C
Wave Soldoldering1)
—
2
kV
Human Body Model2)
1.9
2.0
mm
2.33
2.43
V
AUX Voltage
HSGND Voltage
HSGND Voltage Transient
Soldering Temperature
ESD Capability
VESD
Creepage Distance HS vs. LS
Rated Bus Voltage (95%)
1)
2)
VPFCVS95
Referring to GND
PG_DSO-19-1 Tamb=25°C
According to JESD22A111
According to EIA/JESD22-A114-B (discharging an 100 pF Capacitor through an 1.5kΩ series Resistor)
Datasheet
Page 42 of 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
Operating Range
5.2
Operating Range
Parameter
Symbol
Limit Values
Unit
min.
Max.
Remarks
HSVCC Supply Voltage
VHSVCC
VHSVCCOff
17.5
V
Referring to HSGND
HSGND Voltage
VHSGND
- 900
900
V
Referring to GND
VCC Voltage @ 25°C
VVCC
VVCCOff
17.5
V
TJ = 25°C
VCC Voltage @ 125°C
VVCC
VVCCOff
18.0
V
TJ = 125°C
LSCS Voltage Range
VLSCS
-4
5
V
In active Mode
PFCVS Voltage Range
VPFCVS
0
4
V
PFCCS Voltage Range
VPFCCS
-4
5
V
3
mA
In active Mode
PFZCD Current Range
IPFCZCD
LVS1, LVS2 Voltage Range
VLVS1,LVS2
LVS1, LVS2 Current Range
ILVS1,LVS2
2)
210
µA
IC Power Down Mode
LVS1, LVS2 Current Range
ILVS1,LVS2
- 2.5
2.5
mA
IC active Mode
FRFPHrange
FRUN
150
kHz
RFPH Source Current Range
IRFPH
- 500
0
µA
RTPH Voltage Range
VRTPH
0
2.5
V
Junction Temperature
Tj
- 25
125
°C
Adjustable Preheating Freq.
FRFPH
FRFRUN
150
kHz
Range set by RFPH
Adjustable Run Frequency
FRFRUN
20
120
kHz
Range set by RFRUN
Adjustable Preheating Time
tRTPH
0
2500
ms
Range set by RTPH
Set Resistor for Run Feq.
RRFRUN
4
25
kΩ
Set Resistor for Preheat Feq.
RRFPH
4
—
kΩ
Set Resistor for Preheat Time
RRTPH
0
25
kΩ
Mains Frequency
fMains
45
65
Hz
RFPH Frequency
1)
2)
-3
-6
6
1)
In active Mode
V
@ VRFPH = 2.5V
RRFRUN parallel to RRFPH
NOTCH Filter Operation
Limited by Maximum of Current Range at LVS1, LVS2
Limited by Minimum of Voltage Range at LVS1, LVS2
Datasheet
Page 43 of 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
Electrical Characteristics
5.3
Characteristics
5.3.1 Power Supply Section
Note: The electrical Characteristics involve the spread of values given within the specified supply voltage
and junction temperature range TJ from -25 °C to 125 °C. Typical values represent the median
values, which are related to 25 °C. If not otherwise stated, a supply voltage of 15V and VHSVCC = 15V
is assumed and the IC operates in active mode. Furthermore, all voltages are referring to GND if not
otherwise mentioned.
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Test Condition
VCC Quiescent Current1
IVCCqu1
—
90
130
µA
VVCC = VVCCOff – 0.5V
VCC Quiescent Current2
IVCCqu2
—
120
160
µA
VVCC = VVCCOn – 0.5V
IVCCSupply
—
4.2
6.0
mA
VPFCVS > 2.725V
2)
VCC Supply Current
VCC Supply Current in
Latched Fault Mode
LSVCC Turn-On Threshold
LSVCC Turn-Off Threshold
LSVCC Turn-On/Off Hyst.
VCC Zener Clamp Voltage
IVCCLatch
—
110
170
µA
VRES = 5V
VVCCOn
VVCCOff
VVCCHys
VVCCClamp
13.6
10.0
3.2
15.5
14.1
10.6
3.6
16.3
14.6
11.0
4.0
16.9
V
V
V
V
Hysteresis
IVCC = 2mA/VRES = 5V
VCC Zener Clamp Current
IVCCZener
2.5
—
5
mA
VVCC = 17.5V/VRES = 5V
High Side Leakage Current
IHSGNDleak
—
0.01
2
µA
VHSGND = 800V, VGND=0V
HSVCC Quiescent Current
1)
IHSVCCqu1
1)
IHSVCCqu2
1)
VHSVCCOn
1)
VHSVCCOff
1)
VHSVCCHy
—
170
250
µA
VHSVCC = VHSVCCOn – 0.5V
0.3
9.6
7.9
1.4
0.65
10.1
8.4
1.7
1.2
10.7
9.1
2.0
mA
V
V
V
VHSVCC > VHSVCCOn
2)
HSVCC Quiescent Current
HSVCC Turn-On Threshold
HSVCC Turn-Off Threshold
HSVCC Turn-On/Off Hyst.
Low Side Ground
1)
2)
Hysteresis
GND
Referring to High Side Ground (HSGND)
With inactive Gate
Datasheet
Page 44 of 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
Electrical Characteristics
5.3.2 PFC Section
5.3.2.1
PFC Current Sense (PFCCS)
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Turn – Off Threshold
Over Current Blanking +
1)
Propagation Delay
VPFCCSOff
0.95
1.0
1.05
V
tPFCCSOff
140
200
260
ns
Leading Edge Blanking
tBlanking
180
250
310
ns
IPFCCSBias
- 0.5
—
0.5
µA
PFCCS Bias Current
1)
Propagation Delay = 50ns
5.3.2.2
Test Condition
Pulse Width when
VPFCCS > 1.0V
VPFCCS = 1.5V
PFC Zero Current Detection (PFCZCD)
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Test Condition
Zero Crossing upper Thr.
1)
VPFCZCDUp
1.4
1.5
1.6
V
Zero Crossing lower Thr.
2)
VPFCZCDLow
0.4
0.5
0.6
V
Zero Crossing Hysteresis
VPFCZCDHys
—
1.0
—
V
Clamping of pos. Voltages
VPFCZCDpclp
4.1
4.6
5.1
V
IPFCZCDSink = 2mA
Clamping of neg. Voltages
VPFCZCDnclp
- 1.7
- 1.4
- 1.0
V
IPFCZCDSource = - 2mA
PFCZCD Bias Current
IPFCZCDBias
- 0.5
—
5.0
µA
VPFCZCD = 1.5V
PFCZCD Bias Current
IPFCZCDBias
- 0.5
—
0.5
µA
VPFCZCD = 0.5V
tRingsup
350
500
650
ns
∆t
500
700
900
pAxs
3)
PFCZCD Ringing Su. Time
Limit Value for ON Time
Extension
x IZCD
1)
Turn OFF Threshold
Turn ON Threshold
3)
Ringing Suppression Time
2)
5.3.2.3
PFC Bus Voltage Sense (PFCVS)
Parameter
Symbol
Trimmed Reference Voltage
Limit Values
Unit
min.
Typ.
max.
VPFCVSRef
2.47
2.50
2.53
V
Overvoltage turn Off (109%)
VPFCVSRUp
2.68
2.73
2.78
V
Overvoltage turn On (105%)
VPFCVSLow
2.57
2.63
2.68
V
Overvoltage Hysteresis
VPFCVSHys
70
100
130
mV
Under voltage (75%)
VPFCVSUV
1.835
1.88
1.915
V
Under voltage (12.5%)
VPFCVSUV
0.237
0.31
0.387
V
Rated Bus Voltage (95%)
VPFCVS95
2.325
2.38
2.425
V
PFCVS Bias Current
IPFCVSBias
- 1.0
—
1.0
µA
Datasheet
Page 45 of 56
Test Condition
± 1.2 %
4 % rated Bus Voltage
VPFCVS = 2.5V
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
Electrical Characteristics
5.3.2.4
PFC PWM Generation
Parameter
Initial ON – Time
Symbol
Typ.
max.
Unit
Test Condition
tPFCON_initial
—
4.0
—
µs
VPFCZCD = 0V
2)
tPFCON_max
18
22.7
26
µs
0.45V < VPFCVS < 2.45V
tPFCON_min
160
270
370
ns
tPFCRep
47
52
57
µs
tPFCOff
42
47
52
µs
Off Time
2)
min.
1)
Max. ON – Time
Switch Threshold from
CritCM into DCM
1)
Repetition Time
1)
Limit Values
VPFCZCD = 0V
When missing Zero Crossing Signal
At the Maxima of the AC Line Input Voltage
5.3.2.5
PFC Gate Drive (PFCGD)
Parameter
Symbol
PFCGD Low Voltage
PFCGD High Voltage
VPFCGDLow
VPFCGDHigh
Limit Values
Unit
Test Condition
min.
Typ.
max.
0.4
0.7
0.9
V
IPFCGD = 5mA
0.4
0.75
1.1
V
IPFCGD = 20mA
- 0.2
0.3
0.6
V
IPFCGD = -20mA
10.0
11.0
11.6
V
IPFCGD = -20mA
9.0
—
—
V
IPFCGD = -1mA / VVCC
1)
8.5
—
—
V
IPFCGD = -5mA / VVCC
1)
PFCGD active Shut Down
VPFCGASD
0.4
0.75
1.1
V
IPFCGD = 20mA VVCC=5V
PFCGD UVLO Shut Down
VPFCGDuvlo
0.3
1.0
1.5
V
IPFCGD = 5mA VVCC=2V
PFCGD Peak Source Current
IPFCGDSouce
—
- 100
—
mA
2) + 3)
2) + 3)
PFCGD Peak Sink Current
PFCGD Voltage during sink
Current
IPFCGDSink
—
500
—
mA
VPFCGDHigh
11.0
11.7
12.3
V
IPFCGDSinkH = 3mA
PFC Rise Time
VPFCGDRise
80
220
380
ns
2V > VLSGD > 8V
2)
PFC Fall Time
VPFCGDFall
20
45
70
ns
8V > VLSGD > 2V
2)
1)
VVCC = VVCCOff + 0.3V
RLoad = 4Ω and CLoad = 3.3nF
3)
The Parameter is not Subject to Production Test – verified by Design / Characterization
2)
5.3.2.6
Auxiliary (AUX)
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Test Condition
AUX Voltage OFF Level
VAUXOff
—
—
0.24
V
IAUX = 1mA
AUX Voltage ON Level 1
VAUXOn1
1.7
2.6
3.1
V
Ip = 0A
AUX Voltage ON Level 2
VAUXOn2
1.8
2.6
3.1
V
IAUX
- 0.60
-0.45
- 0.3
mA
Ip = 1mA
VAUX = 1V / IP = 0A
AUX Current
1)
1)
1)
IP = the positive Current into PIN ZCD
Datasheet
Page 46 of 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
Electrical Characteristics
5.3.3 Inverter Section
5.3.3.1
Low Side Current Sense (LSCS)
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Test Condition
Overcurrent Shut Down Volt.
VLSCSOvC1
1.5
1.6
1.7
V
1)
Overcurrent Shut Down Volt.
VLSCSOvC2
0.75
0.8
0.85
V
2)
tLSCSOvC
450
600
700
ns
VLSCSCap1
80
100
Duration of Overcurrent
Capacitive Mode Det. Level 1
123
mV
Capacitive Mode Duration 1
tLSCSCap1
—
280
—
ns
Capacitive Mode Det. Level 2
VLSCSCap2
1.8
2.0
2.2
V
During Run Mode
3)
During Run Mode
4)
Capacitive Mode Duration 2
tLSCSCap2
—
50
—
ns
Capacitive Mode Det. Level 3
VLSCSCap3
- 120
- 100
- 77
mV
Capacitive Mode Duration 3
tLSCSCap3
—
280
—
ns
5)
LSCS Bias Current
ILSCSBias
-1.0
—
1.0
µA
@ VLSCS = 1.5V
1)
Overcurrent Voltage Threshold active during: Start Up, Soft start, Ignition and Pre Run Mode
Overcurrent Voltage Threshold active during: Preheating and Run Mode
3)
Active during 2nd 50% Duty Cycle of LSGD in Run Mode
4)
Active during Turn ON of the HSGD in Run Mode
5)
Active before Turn ON of the HSGD in Run Mode
2)
Datasheet
Page 47 of 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
Electrical Characteristics
5.3.3.2
Low Side Gate Drive (LSGD)
Parameter
LSGD Low Voltage
LSGD High Voltage
Symbol
VLSGDLow
VLSGDHigh
Limit Values
Unit
Test Condition
min.
typ.
max.
0.4
0.7
1.0
V
ILSGD = 5mA
0.4
0.8
1.2
V
ILSGD = 20mA
- 0.3
0.2
0.5
V
10.0
10.8
11.6
V
ILSGD
1)
9.0
—
—
V
2)
8.5
—
—
V
3)
5)
5)
= - 20mA (Source)
5)
LSGD active Shut Down
VLSGDASD
0.4
0.75
1.1
V
VCC=5V / ILSGD = 20mA
LSGD UVLO Shut Down
VLSGDUVLO
0.3
1.0
1.5
V
VCC=2V / ILSGD = 5mA
LSGD Peak Source Current
ILSGDSource
—
- 50
—
mA
4) + 6)
LSGD Peak Sink Current
ILSGDSink
—
300
—
mA
4) + 6)
LSGD Voltage during 5)
VLSGDHigh
—
11.7
—
V
ILSGDsinkH = 3mA
LSGD Rise Time
tLSGDRise
80
220
380
ns
2V < VLSGD < 8V
LSGD Fall Time
tLSGDFall
20
35
60
ns
8V > VLSGD > 2V
5)
4)
4)
1)
ILSGD = - 20mA Source Current
VCCOFF + 0.3V and ILSGD = - 1mA Source Current
3)
VCCOFF + 0.3V and ILSGD = - 5mA Source Current
4)
Load: RLoad = 10Ω and CLoad = 1nF
5)
Sink Current
6)
The Parameter is not Subject to Production Test – verified by Design / Characterization
2)
Datasheet
Page 48 of 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
Electrical Characteristics
5.3.3.3
Inverter Control Run (RFRUN)
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Test Condition
Fixed Start – Up Frequency
FStartUp
121.5
135
148.5
kHz
Duration of Soft Start
tSoftStart
9
11
13.5
ms
RFRUN Voltage in Run Mode
VRFRUN
—
2.5
—
V
Run Frequency
FRFRUN
49
50
51
kHz
RRFRUN = 10kΩ
FRFRUN1
—
20
—
kHz
IRFRUN= - 100 µA
FRFRUN2
—
40
—
kHz
IRFRUN= - 200 µA
FRFRUN3
—
100
—
kHz
IRFRUN= - 500 µA
IRFRUNmax
—
-1000
- 650
µA
@ VRFRUN = 0V
Adjustable Run Frequency
RFRUN max. Current Range
1)
1)
@ 100µA<IRFRUN<600µA
Shift Start Up Frequency to Preheating Frequency
5.3.3.4
Inverter Control Preheating (RFPH, RTPH)
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Test Condition
RFPH Voltage Preheating
VRFPH
—
2.5
—
V
VRFPH = 0V in Run Mode
Preheating Frequency
FRFPH1
97
100
103
kHz
RRFPH = RRFRUN = 10kΩ
RFPH max. Current Range
IRFPHmax
—
-1000
- 550
µA
@ VRFPH = 0V
Current for set Preh. Time
IRTPH
—
- 100
—
µA
tRTPH1
950
1000
1050
ms
RRTPH1 = 10kΩ
tRTPH2
50
100
150
ms
RRTPH2 = 1kΩ
tRTPH3
—
500
—
ms
RRTPH3 = 5kΩ
tRTPH4
—
2000
—
ms
RRTPH4 = 20kΩ
tRTPH5
—
2500
—
ms
RRTPH5 = 25kΩ
Preheating Time
Datasheet
Page 49 of 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
Electrical Characteristics
5.3.3.5
Restart after Lamp Removal (RES)
Parameter
Symbol
High Side Filament In Det.
RES Current Source
5.3.3.6
Limit Values
Unit
min.
typ.
max.
VRES1
1.55
1.60
1.65
V
VRES2
1.25
1.30
1.35
V
VRES3
—
3.2
—
V
IRES1
- 53.2
-42.6
-32.0
µA
IRES2
-44.2
-35.4
-26.6
µA
IRES3
- 26.6
-21.3
- 16.0
µA
IRES4
- 22.1
-17.7
-13.3
µA
Test Condition
UVLO, VCC < VCCON
Run Mode
VRES = 1V ;
LVS1 = 5µA
VRES = 2V ;
LVS1 = 5µA
VRES = 1V ;
LVS1 = 30µA
VRES = 2V ;
LVS1 = 30µA
Lamp Voltage Sense (LVS1, LVS2)
Parameter
Symbol
Source Current before Startup
ILVSSource
Limit Values
min.
typ.
max.
- 5.0
- 3.0
- 2.0
Unit
Test Condition
µA
VLVS = 0V
VLVSEnable1
350
530
750
mV
1)
Sink Current for Lamp Det.
ILVSSink
8.0
12.0
18.0
µA
VLVS > VLVSClamp
Positive Clamping Voltage
VLVSClamp
—
6.5
—
V
@ ILVS = 300µA
AC EOLCurrent Threshold
ILVSSourceAC
190
210
230
µApp
ILVS > ILVSEOLpp EOL 1
Positive EOL Current Thr.
ILVSDCPos
34
42
50
µA
ILVS > ILVSDCPos EOL 2
Negative EOL Current Thr.
ILVSDCNeg
- 50
- 42
- 34
µA
ILVS > ILVSDCNeg EOL 2
Enable Lamp Monitoring
1)
If VLVS < VLVS1Enable1 Monitoring is disabled
Datasheet
Page 50 of 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
5.3.3.7
High Side Gate Drive (HSGD)
Parameter
Symbol
VHSGDLow
HSGD Low Voltage
Limit Values
Unit
Test Condition
Min.
typ.
max.
0.02
0.05
0.1
V
IHSGD = 5mA (sink)
0.5
1.1
2.5
V
IHSGD = 100mA (sink)
- 0.4
- 0.2
- 0.05
V
9.7
10.5
11.2
V
7.8
—
—
V
HSGD active Shut Down
VHSGDASD
0.05
0.22
0.5
V
HSGD Peak Source Current
IHSGDSource
—
- 50
—
mA
ILSGD = - 20mA (source)
VCCHS=15V
IHSGD = - 20mA (source)
VCCHSOFF + 0.3V
IHSGD = - 1mA (source)
VCCHS=5V
IHSGD = 20mA (sink)
RLoad = 10Ω+CLoad = 1nF 1)
HSGD Peak Sink Current
IHSGDSink
—
300
—
mA
RLoad = 10Ω+CLoad = 1nF 1)
HSGD Rise Time
THSGDRise
140
220
300
ns
HSGD Fall Time
THSGDFall
20
35
70
ns
VHSGDHigh
HSGD High Voltage
1)
2V < VLSGD < 8V
RLoad = 10Ω+CLoad = 1nF
8V > VLSGD > 2V
RLoad = 10Ω+CLoad = 1nF
The Parameter is not Subject to Production Test – verified by Design / Characterization
5.3.3.8
Timer Section
Delay Timer 1
tTIMER1
70
100
160
ms
For Lamp Detection
Delay Timer 2
tTIMER2
tInv
74
100
84
130
94
160
ms
µs
For VBUS > 95%
Inverter Time
Inverter Dead Time Max
tDeadMax
2.25
2.5
2.75
µs
Inverter Dead Time Min
tDeadMin
1.0
1.25
1.5
µs
∆ Inverter Dead Time Max
tDeadMax
- 200
—
200
ns
∆ Inverter Dead Time Min
tDeadMin
- 200
—
200
ns
Min. Duration of Ignition
tIgnition
34
40
48
ms
Max. Duration of Ignition
tNOIgnition
197
—
236
ms
Duration of Pre – Run
tPRERUN
565
625
685
ms
5.3.3.9
Built in Customer Test Mode
Voltage at RTPH Pin
VRTPH
0
V
Voltage at RTPH Pin
VRTPH
VLVS1,2
5.0
0
V
V
IC remains in Preheating
Disables Lamp Voltage Sense
VRES
0
V
Disable the Filament Detection
Voltage at LVS1 / LVS2 Pin
Voltage at RES Pin
Voltage at RFPH Pin
VRFPH
5.0
1)
V
1)
V
1)
VRFRUN
5.0
Voltage at VCC Pin
VCC
> 14.1
V
Voltage at RES Pin
VRES
0
V
Voltage at RFRUN Pin
Preheating Time = 0ms (Skipped Preheating)
Built in Customer Test Mode - Clock
Acceleration. Decreasing Time for the
following Procedures.
Preheating by Factor 4
Timeout Ignition by Factor 2
Pre RUN by Factor 15
EOL by 60
1) Tolerance for this voltage is: ± 5%
Datasheet
Page 51 of 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
Application Example
6
6.1
Application Example
Schematic Ballast 54W T5 Single Lamp
Figure 40: Application Circuit of Ballast for single Fluorescent Lamp Voltage Mode Preheating
Datasheet
Page 52 of 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
Application Example
6.2
Bill of Material
BOM
090402-1-L-54W-T5-FL2-VM
54W T5, single Lamp, Voltage Mode Preheat
ICB2FL01G
Input Voltage 180VAC...270V AC
V_BUS= 412V
Package
F1
K1/1
K1/2
K1/3
K2/1
K2/2
K2/3
K3/1
K3/2
K3/3
IC1
Q1
Q2
Q3
Q4
D1…4
D5
D6
D7
D8
D9
D10
D11
DR12
D13
D61
L101
L1 PFC
L2
L 21
L 22
L 23
C1
C2
C3
C4
C5
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C40
Fuse 1A fast
Fuse Holder
AC Input
AC Input
PE
not connected
High Side Filament
High Side Filament
Low Side Filament
Low Side Filament
not connected
ICB2FL01G
SPD03N60C3
SPD03N60C3
SPD03N60C3
not assembled
S1M
MURS160T3
BYG26J
BYG22D
BYG22D
BZX284C16
not assembled
not assembled
110kΩ
not assembled
not assembled
2x68mH/0,6A
1,58mH
total gap= 1.1mm
1,46mH
total gap= 2mm
100µH
100µH
not assembled
220nF/X2/305V
33nF/630V/MKT
3,3nF/Y2-RM10
220nF/X2/305V
not assembled
10µF/450V
2,2nF/50V
100nF/50V
1µF/63V/MKT
68nF/50V
33nF/630V/MKT
1nF/630V/MKT
100nF/630V
not assembled
22nF/50V
4,7nF/1600V/MKP
22nF/400V/MKT
22nF/400V/MKT
not assembled
not assembled
not assembled
220nF/25V
Datasheet
Wickmann
Typ 370
B-Nr: 250-203
R1
R2
R3
R4
R402
R403
470kΩ
470kΩ
not assembled
not assembled
not assembled
not assembled
R11
R12
R13
R14
R15
R16
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R30
R34
R35
R36
R36A
R61
470kΩ
470kΩ
33kΩ
820kΩ
820kΩ
22Ω
1Ω
not assembled
10kΩ
11kΩ (45,5kHz!)
8,2kΩ (106,4kHz!)
10kΩ (1000ms!)
0,68Ω
0,68Ω (Σ 0,34Ω)
22Ω
22Ω
33Ω
150kΩ
150kΩ
56kΩ
0Ω
0Ω
Gen-2
Package
.1206
.1206
.1206
.1206
.1206
.1206
B-Nr: 250-203
B-Nr: 250-203
Infineon
Infineon
Infineon
Infineon
Infineon
Fairchild
ON Semi
Philips
Philips
Philips
Philips
>GE834
SO-20
D-Pack
D-Pack
D-Pack
SOT-223
(1000V/1A/2µs)
(600V/1A/75ns)
(600V/1A/30ns)
(200V/1A/25ns)
(200V/1A/25ns)
DO-214AC
SMB
SOD124
DO214
DO214
SOD110
Philips
Epcos
Epcos
2 pcs
Epcos
2 pcs
Epcos
Epcos
Epcos
Epcos
Epcos
Epcos
Epcos
Epcos
Epcos
SOD110
B82732F2601B001
105turns/10turns EFD25/13/9
B78326P7373A005
T1904
EFD25/13/9
182turns
B78326P7374A005
T1905
B82144B1104J000
RM5
B82144B1104J000
RM5
B82144B1104J000
RM5
B32922C3224M000
RM15
B32521N8333K000
RM10
B32021A3332
RM10/15
B32922C3224M000
RM15
B32529C8102K000
RM5
B43888A5106M000 single ended
.0805
.0805
Epcos
B32529C0105K000
RM5
Epcos
.0805
Epcos
B32521N8333K000
RM10
Epcos
B32529C8102K000
RM5
Epcos
B32612A6104K008
RM15
RM7,5
.0805
Epcos
B32612-J1472J008
RM15
Epcos
B32620A4223J000 RM7,5/10
Epcos
B32620A4223J000 RM7,5/10
Epcos
B32620A4223J000 RM7,5/10
Epcos
B32612-J1472J008
RM15
Roederstein
RM7,5
.0805
Page 53 of 56
.1206
.1206
.1206
.1206
.1206
.0805
.1206
.1206
.0805
.0805
.0805
.0805
.1206
.1206
.1206
.0805
.1206
.1206
.1206
.1206
.1206
.1206
connect LVS2 (pin14) to GND
R41
R42
R43
R44
R45
68kΩ
68kΩ
68kΩ
68kΩ
6,8kΩ
.1206
.1206
.1206
.1206
.1206
R61
0Ω
.0805
EOL1 threshold
167Vpeak x 1.5=250V peak
5W
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
Application Example
6.3
Multi Lamp Ballast Topologies
Figure 41: Parallel 2 Lamp Ballast Circuit with Current Mode Preheating
Figure 42: Serial 2 Lamp Ballast Circuit with Voltage Mode Preheating
Datasheet
Page 54 of 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
Figure 43: 4 Lamp Ballast Circuit with Voltage Mode Preheating
Datasheet
Page 55 of 56
ICB2FL01G
V1.2
2nd Generation FL-Controller for FL-Ballasts
Application Example
7
Package Outlines
Figure 44: Package Outline with Creepage Distance
Datasheet
Page 56 of 56
ICB2FL01G
V1.2