IRF IRFPS43N50

PD- 93922B
SMPS MOSFET
IRFPS43N50K
HEXFET® Power MOSFET
Applications
l Switch Mode Power Supply (SMPS)
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency
Circuits
VDSS
RDS(on) typ.
ID
0.078Ω
47A
500V
Benefits
l Low Gate Charge Qg results in Simple
Drive Requirement
l Improved Gate, Avalanche and Dynamic
dv/dt Ruggedness
l Fully Characterized Capacitance and
Avalanche Voltage and Current
l Low RDS(on)
Super-247™
Absolute Maximum Ratings
Parameter
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
TJ
TSTG
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current 
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
dv/dtPeak Diode Recovery dv/dt ƒ
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case )
Max.
Units
47
29
190
540
4.3
± 30
9.0
-55 to + 150
A
W
W/°C
V
V/ns
300
°C
Avalanche Characteristics
Symbol
EAS
IAR
EAR
Parameter
Single Pulse Avalanche Energy‚
Avalanche Current
Repetitive Avalanche Energy
Typ.
Max.
Units
–––
–––
–––
910
47
54
mJ
A
mJ
Typ.
Max.
Units
–––
0.24
–––
0.23
–––
40
°C/W
Thermal Resistance
Symbol
RθJC
RθCS
RθJA
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Parameter
Junction-to-Case
Case-to-Sink, Flat, Greased Surface
Junction-to-Ambient
1
04/03/01
IRFPS43N50K
Static @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS
RDS(on)
VGS(th)
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
IDSS
Drain-to-Source Leakage Current
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
∆V(BR)DSS/∆TJ
Min. Typ. Max. Units
Conditions
500 ––– –––
V
VGS = 0V, ID = 250µA
––– 0.60 ––– V/°C Reference to 25°C, ID = 1mA†
––– 0.078 0.090
Ω
VGS = 10V, ID = 28A „
3.0
––– 5.0
V
VDS = V GS, ID = 250µA
––– ––– 50
µA
VDS = 500V, VGS = 0V
––– ––– 250
µA
VDS = 400V, VGS = 0V, TJ = 125°C
––– ––– 100
VGS = 30V
nA
––– ––– -100
VGS = -30V
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Coss
Coss
Coss eff.
Parameter
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
Min.
23
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ.
–––
–––
–––
–––
25
140
55
74
8310
960
120
10170
240
440
Max. Units
Conditions
–––
S
VDS = 50V, ID = 28A
350
ID = 47A
85
nC
VDS = 400V
180
VGS = 10V, See Fig. 6 and 13 „
–––
VDD = 250V
–––
ID = 47A
ns
–––
RG = 1.0Ω
–––
VGS = 10V,See Fig. 10 „
–––
VGS = 0V
–––
VDS = 25V
–––
pF
ƒ = 1.0MHz, See Fig. 5
–––
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
–––
VGS = 0V, VDS = 400V, ƒ = 1.0MHz
–––
VGS = 0V, VDS = 0V to 400V …
Diode Characteristics
Symbol
IS
ISM
VSD
trr
Q rr
IRRM
ton
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode) 
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Reverse RecoveryCurrent
Forward Turn-On Time
Min. Typ. Max. Units
–––
–––
47
–––
–––
190
A
Conditions
MOSFET symbol
showing the
G
integral reverse
p-n junction diode.
TJ = 25°C, IS = 47A, VGS = 0V
TJ = 25°C, IF = 47A
di/dt = 100A/µs „
D
S
––– ––– 1.5
V
„
––– 620 940
ns
––– 14
21
µC
––– 38 –––
A
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
 Repetitive rating; pulse width limited by
max. junction temperature. (See Fig. 11)
‚ Starting TJ = 25°C, L = 0.82mH, RG = 25Ω,
IAS = 47A (See Figure 12a).
„ Pulse width ≤ 400µs; duty cycle ≤ 2%.
… Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .
ƒ ISD ≤ 47A, di/dt ≤ 230A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 150°C.
2
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IRFPS43N50K
1000
1000
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
100
10
1
4.5V
0.1
20µs PULSE WIDTH
TJ = 25 °C
0.01
0.1
1
10
100
10
4.5V
1
100
RDS(on) , Drain-to-Source On Resistance
(Normalized)
I D , Drain-to-Source Current (A)
3.5
TJ = 150 ° C
10
TJ = 25 ° C
1
V DS = 50V
20µs PULSE WIDTH
5
6
7
8
9
10
11
VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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10
100
Fig 2. Typical Output Characteristics
1000
4
1
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
0.1
20µs PULSE WIDTH
TJ = 150 °C
0.1
0.1
VDS , Drain-to-Source Voltage (V)
100
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
TOP
I D , Drain-to-Source Current (A)
I D , Drain-to-Source Current (A)
TOP
12
ID = 48A
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-60 -40 -20
VGS = 10V
0
20
40
60
80 100 120 140 160
TJ , Junction Temperature ( ° C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRFPS43N50K
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
100000
C, Capacitance(pF)
Coss = Cds + Cgd
10000
Ciss
1000
Coss
100
Crss
20
ID = 48A
V DS= 400V
V DS= 250V
V DS= 100V
VGS , Gate-to-Source Voltage (V)
1000000
15
10
5
10
1
10
100
1000
0
0
50
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
ISD , Reverse Drain Current (A)
150
200
250
300
350
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
1000
1000
OPERATION IN THIS AREA LIMITED
BY RDS(on)
ID , Drain Current (A)
100
TJ = 150 ° C
100
10
TJ = 25 ° C
10us
100us
10
1ms
1
0.1
0.2
4
100
QG , Total Gate Charge (nC)
V GS = 0 V
0.7
1.2
1.7
2.2
1
TC = 25 °C
TJ = 150 °C
Single Pulse
10
10ms
100
1000
VSD ,Source-to-Drain Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
Fig 8. Maximum Safe Operating Area
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IRFPS43N50K
50
VGS
40
ID , Drain Current (A)
RD
VDS
D.U.T.
RG
+
-VDD
30
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
20
Fig 10a. Switching Time Test Circuit
10
VDS
90%
0
25
50
75
100
125
150
TC , Case Temperature ( ° C)
10%
VGS
Fig 9. Maximum Drain Current Vs.
Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJC )
1
0.1
D = 0.50
0.20
0.10
0.05
0.01
0.02
0.01
0.001
0.00001
PDM
t1
SINGLE PULSE
(THERMAL RESPONSE)
t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak TJ = P DM x ZthJC + TC
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRFPS43N50K
EAS , Single Pulse Avalanche Energy (mJ)
2000
TOP
BOTTOM
1500
ID
22A
30A
47A
1 5V
D R IV E R
L
VDS
1000
D .U .T
RG
+
- VD D
IA S
500
20V
tp
A
0 .0 1 Ω
Fig 12c. Unclamped Inductive Test Circuit
0
25
50
75
100
125
150
Starting TJ , Junction Temperature ( °C)
Fig 12a. Maximum Avalanche Energy
Vs. Drain Current
V (B R )D SS
tp
IAS
Fig 12d. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
QG
50KΩ
12V
VGS
.2µF
.3µF
D.U.T.
QGS
+
V
- DS
QGD
VG
VGS
3mA
IG
ID
Current Sampling Resistors
Fig 13a. Gate Charge Test Circuit
6
Charge
Fig 13b. Basic Gate Charge Waveform
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IRFPS43N50K
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
ƒ
+
‚
-
-
„
+

•
•
•
•
RG
Driver Gate Drive
P.W.
+
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Period
D=
-
VDD
P.W.
Period
VGS=10V
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFET® Power MOSFETs
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7
IRFPS43N50K
SUPER -247AC Package Outline
Dimensions are shown in millimeters (inches)
0.13 [.005]
16.10 [.632]
15.10 [.595]
2X R 3.00 [.118]
2.00 [.079]
0.25 [.010]
5.50 [.216]
4.50 [.178]
A
B A
13.90 [.547]
13.30 [.524]
2.15 [.084]
1.45 [.058]
1.30 [.051]
0.70 [.028]
4
20.80 [.818]
19.80 [.780]
16.10 [.633]
15.50 [.611]
4
C
1
2
3
B
14.80 [.582]
13.80 [.544]
5.45 [.215]
2X
Ø 1.60 [.063]
MAX.
4.25 [.167]
3.85 [.152]
3X
1.60 [.062]
1.45 [.058]
0.25 [.010]
B A
3X
1.30 [.051]
1.10 [.044]
2.35 [.092]
1.65 [.065]
S ECT ION E-E
NOT ES :
1. DIMENS IONING AND T OLE RANCING PER AS ME Y14.5M-1994.
2. DIMENS IONS ARE S HOWN IN MILLIMET ERS [INCHES ]
3. CONT ROLLING DIMENS ION: MILLIMET ER
4. OUT LINE CONF ORMS T O JEDEC OUT LINE T O-274AA
E
E
LE AD AS S IGNMENT S
MOS FET
1 - GATE
2 - DRAIN
3 - S OURCE
4 - DRAIN
IGBT
1 - GATE
2 - COLLECT OR
3 - EMIT T ER
4 - COLLECT OR
Data and specifications subject to change without notice.
This product has been designed and qualified for the industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.04/01
8
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