PD - 94444
SMPS MOSFET
Applications
l Switch Mode Power Supply (SMPS)
l UninterruptIble Power Supply
l High Speed Power Switching
IRFIB8N50K
HEXFET® Power MOSFET
VDSS
RDS(on) typ.
ID
500V
290mΩ
6.7A
Benefits
l Low Gate Charge Qg results in Simple
Drive Requirement
l Improved Gate, Avalanche and Dynamic
dv/dt Ruggedness
l Fully Characterized Capacitance and
Avalanche Voltage and Current
TO-220
FULL-PAK
Absolute Maximum Ratings
Parameter
Max.
Units
Continuous Drain Current, VGS @ 10V
6.7
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
IDM
4.2
PD @TC = 25°C
Power Dissipation
45
W
VGS
Linear Derating Factor
Gate-to-Source Voltage
0.36
±30
W/°C
V
17
V/ns
ID @ TC = 25°C
c
e
dv/dt
TJ
Peak Diode Recovery dv/dt
TSTG
Storage Temperature Range
A
27
-55 to + 150
Operating Junction and
°C
Soldering Temperature, for 10 seconds
300 (1.6mm from case )
1.1(10)
Mounting torqe, 6-32 or M3 screw
N•m (lbf•in)
Avalanche Characteristics
EAS
Parameter
Single Pulse Avalanche Energy
IAR
Avalanche Current
EAR
Repetitive Avalanche Energy
c
d
c
Typ.
Max.
Units
–––
290
mJ
–––
6.7
A
–––
4.5
mJ
Thermal Resistance
Typ.
Max.
Units
RθJC
Junction-to-Case
Parameter
–––
2.76
°C/W
RθJA
Junction-to-Ambient
–––
65
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1
4/21/04
IRFIB8N50K
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
Conditions
V(BR)DSS
Drain-to-Source Breakdown Voltage
500
–––
–––
∆V(BR)DSS/∆TJ
Breakdown Voltage Temp. Coefficient
–––
0.59
–––
RDS(on)
Static Drain-to-Source On-Resistance
–––
290
350
VGS(th)
Gate Threshold Voltage
3.0
–––
5.0
V
VDS = VGS, ID = 250µA
IDSS
Drain-to-Source Leakage Current
–––
–––
50
µA
VDS = 500V, VGS = 0V
–––
–––
250
Gate-to-Source Forward Leakage
–––
–––
100
Gate-to-Source Reverse Leakage
–––
–––
-100
IGSS
V
VGS = 0V, ID = 250µA
V/°C Reference to 25°C, ID = 1mA
mΩ VGS = 10V, ID = 4.0A
f
VDS = 400V, VGS = 0V, TJ = 125°C
nA
VGS = 30V
VGS = -30V
Dynamic @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
4.7
–––
–––
V
Conditions
VDS = 50V, ID = 4.0A
gfs
Forward Transconductance
Qg
Total Gate Charge
–––
–––
89
Qgs
Gate-to-Source Charge
–––
–––
24
Qgd
Gate-to-Drain ("Miller") Charge
–––
–––
44
VGS = 10V
td(on)
Turn-On Delay Time
–––
17
–––
VDD = 250V
tr
Rise Time
–––
16
–––
ID = 6.7A
td(off)
Turn-Off Delay Time
–––
28
–––
tf
Fall Time
–––
8.4
–––
VGS = 10V
Ciss
Input Capacitance
–––
2160
–––
VGS = 0V
Coss
Output Capacitance
–––
240
–––
Crss
Reverse Transfer Capacitance
–––
27
–––
Coss
Output Capacitance
–––
2600
–––
ƒ = 1.0MHz
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Coss
Output Capacitance
–––
62
–––
VGS = 0V, VDS = 400V, ƒ = 1.0MHz
Coss eff.
Effective Output Capacitance
–––
120
–––
VGS = 0V, VDS = 0V to 400V
ID = 6.7A
nC
ns
VDS = 400V
RG = 38Ω
f
f
VDS = 25V
pF
e
Diode Characteristics
Parameter
Min. Typ. Max. Units
IS
Continuous Source Current
–––
–––
6.7
ISM
(Body Diode)
Pulsed Source Current
–––
–––
27
ch
A
(Body Diode)
VSD
Diode Forward Voltage
–––
–––
2.0
V
trr
Reverse Recovery Time
–––
430
640
ns
Qrr
Reverse RecoveryCharge
–––
2840
4270
nC
ton
Forward Turn-On Time
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See Fig. 11).
Starting TJ = 25°C, L = 13mH, RG = 25Ω,
IAS = 6.7A, dv/dt = 17V/ns (See Figure 12a).
ISD ≤ 6.7A, di/dt ≤ 330A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 150°C.
2
Conditions
MOSFET symbol
D
showing the
integral reverse
G
S
p-n junction diode.
TJ = 25°C, IS = 6.7A, VGS = 0V
f
TJ = 25°C, IF = 6.7A
di/dt = 100A/µs
f
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Pulse width ≤ 300µs; duty cycle ≤ 2%.
Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .
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IRFIB8N50K
100
1000
VGS
15V
12V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
100
10
BOTTOM
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
1
0.1
5.0V
0.01
10
BOTTOM
VGS
15V
12V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
5.0V
1
0.1
20µs PULSE WIDTH
Tj = 150°C
20µs PULSE WIDTH
Tj = 25°C
0.01
0.001
0.1
1
10
0.1
100
3.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current (Α)
100.00
T J = 150°C
1.00
T J = 25°C
0.10
VDS = 50V
20µs PULSE WIDTH
0.01
4.0
5.0
6.0
7.0
8.0
9.0
VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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10
100
Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
10.00
1
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
10.0
ID = 6.7A
2.5
2.0
1.5
1.0
0.5
0.0
-60 -40 -20
VGS = 10V
0
20
40
60
80 100 120 140 160
TJ , Junction Temperature ( °C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRFIB8N50K
100000
10000
ID = 6.7A
400V
250V
100V
10
Coss = Cds + Cgd
8
Ciss
1000
VGE (V)
C, Capacitance(pF)
12
VGS = 0V,
f = 1 MHZ
Ciss = C gs + Cgd, C ds SHORTED
Crss = Cgd
Coss
100
6
4
Crss
2
10
0
1
1
10
100
0
1000
30
40
50
60
70
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
100
ID, Drain-to-Source Current (A)
100.00
ISD, Reverse Drain Current (A)
20
Q G , Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
T J = 150°C
10.00
TJ = 25°C
1.00
VGS = 0V
0.0
0.5
1.0
VSD, Source-toDrain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
OPERATION IN THIS AREA
LIMITED BY R DS(on)
10
100µsec
1msec
1
Tc = 25°C
Tj = 150°C
Single Pulse
10msec
0.1
0.10
4
10
1.5
1
10
100
1000
10000
VDS, Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRFIB8N50K
7.0
V DS
VGS
ID , Drain Current (A)
6.0
RG
5.0
RD
D.U.T.
+
-VDD
10V
4.0
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
3.0
Fig 10a. Switching Time Test Circuit
2.0
VDS
1.0
90%
0.0
25
50
75
100
125
150
TC , Case Temperature ( °C)
10%
VGS
Fig 9. Maximum Drain Current Vs.
Case Temperature
tr
td(on)
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJC )
10
D = 0.50
1
0.20
0.10
0.05
0.1
PDM
t1
0.02
0.01
t2
SINGLE PULSE
(THERMAL RESPONSE)
0.01
0.00001
0.0001
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.001
0.01
0.1
1
10
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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IRFIB8N50K
EAS , Single Pulse Avalanche Energy (mJ)
700
ID
3.0A
4.2A
BOTTOM 6.7A
TOP
600
500
15V
400
DRIVER
L
VDS
300
D.U.T
RG
200
+
- VDD
IAS
20V
tp
100
A
0.01Ω
Fig 12c. Unclamped Inductive Test Circuit
0
25
50
75
100
125
150
Starting T J , Junction Temperature (°C)
Fig 12a. Maximum Avalanche Energy
Vs. Drain Current
V(BR)DSS
tp
I AS
Fig 12d. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
QG
50KΩ
12V
VGS
.2µF
.3µF
D.U.T.
QGS
+
V
- DS
QGD
VG
VGS
3mA
IG
ID
Current Sampling Resistors
Fig 13a. Gate Charge Test Circuit
6
Charge
Fig 13b. Basic Gate Charge Waveform
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IRFIB8N50K
Peak Diode Recovery dv/dt Test Circuit
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D.U.T
+
-
-
+
RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Driver Gate Drive
P.W.
Period
D=
+
-
VDD
P.W.
Period
VGS=10V
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFET® Power MOSFETs
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7
IRFIB8N50K
TO-220 Full-Pak Package Outline
Dimensions are shown in millimeters (inches)
10.60 (.417)
10.40 (.409)
ø
3.40 (.133)
3.10 (.123)
4.80 (.189)
4.60 (.181)
- A3.70 (.145)
3.20 (.126)
16.00 (.630)
15.80 (.622)
2.80 (.110)
2.60 (.102)
LEAD ASSIGNMENTS
1 - GATE
2 - DRAIN
3 - SOURCE
7.10 (.280)
6.70 (.263)
1.15 (.045)
MIN.
NOTES:
1 DIMENSIONING & TOLERANCING
PER ANSI Y14.5M, 1982
1
2
3
2 CONTROLLING DIMENSION: INCH.
3.30 (.130)
3.10 (.122)
-B-
13.70 (.540)
13.50 (.530)
C
A
3X
1.40 (.055)
1.05 (.042)
3X
0.90 (.035)
0.70 (.028)
0.25 (.010)
3X
M A M
B
2.54 (.100)
2X
0.48 (.019)
0.44 (.017)
2.85 (.112)
2.65 (.104)
D
B
MINIMUM CREEPAGE
DISTANCE BETW EEN
A-B-C-D = 4.80 (.189)
TO-220 Full-Pak Part Marking Information
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TO-22O Full-Pak package is not recommended for Surface Mount Application.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 04/04
8
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